H CAT24FC32A EE GEN FR ALO 32K-Bit Fast Mode I2C Serial CMOS EEPROM LE FEATURES A D F R E ETM ■ Output slope control to eliminate ground ■ Fast mode I2C bus compatible* bounce ■ Max clock frequency: ■ Zero standby current 400 kHz for VCC=1.8V to 3.6V ■ Commercial temperature range ■ Hardware write protect for entire array ■ 1,000,000 program/erase cycles ■ Cascadable for up to eight devices ■ 100 years data retention ■ 32-Byte page or byte write modes ■ 8-pin PDIP, 8-pin SOIC (150 and 200 mil) and ■ Self-timed write cycle with autoclear 8-pin TSSOP packages ■ 5 ms max write cycle time ■ "Green" package options available ■ Random and sequential read modes ■ Schmitt trigger and spike suppression at SDA and SCL inputs DESCRIPTION The CAT24FC32A is a 32K-bit Serial CMOS EEPROM internally organized as 4Kx8 bits. The device is compatible with Fast-mode I2C bus specification and operates down to 1.8V with a bit rate up to 400 kbit/s. Extended addressing capability allows up to 8 devices to share the same bus. Catalyst's advanced CMOS technology substantially reduces device power requirements. The device is optimized for high performance applications, where low power, low voltage and high speed operation are required. CAT24FC32A is available in 8-pin DIP, 8-pin SOIC (JEDEC and EIAJ) and 8-pin TSSOP packages. PIN CONFIGURATION DIP Package (P, L) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA BLOCK DIAGRAM EXTERNAL LOAD TSSOP Package (U, Y) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 WP VCC SCL VSS SDA WORD ADDRESS BUFFERS START/STOP LOGIC SOIC Package (J,W) (K, X) VSS 1 2 3 4 8 7 6 5 COLUMN DECODERS 256 SDA A0 A1 A2 SENSE AMPS SHIFT REGISTERS DOUT ACK VCC XDEC WP VCC WP SCL SDA 128 EEPROM 128 X 256 CONTROL LOGIC DATA IN STORAGE HIGH VOLTAGE/ TIMING CONTROL SCL A0 A1 A2 STATE COUNTERS SLAVE ADDRESS COMPARATORS * Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol. © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice 1 Doc. No. 1048, Rev. F CAT24FC32A PIN FUNCTIONS Pin Name Function A0, A1, A2 Device Address Inputs SDA Serial Data/Address SCL Serial Clock WP Write Protect VCC Power Supply VSS Ground ABSOLUTE MAXIMUM RATINGS* *COMMENT Temperature Under Bias ................. –55°C to +125°C Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. Storage Temperature ....................... –65°C to +150°C Voltage on Any Pin with Respect to Ground(1) ........... –2.0V to +VCC + 2.0V VCC with Respect to Ground ............... –2.0V to +7.0V Package Power Dissipation Capability (TA = 25°C) ................................... 1.0W Lead Soldering Temperature (10 secs) ............ 300°C Output Short Circuit Current(2) ........................ 100mA RELIABILITY CHARACTERISTICS Symbol Units Reference Test Method 1,000,000 Cycles/Byte MIL-STD-883, Test Method 1033 Data Retention 100 Years MIL-STD-883, Test Method 1008 VZAP(3) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015 ILTH(3)(4) Latch-up 100 mA NEND TDR (3) (3) Parameter Min. Endurance Max. JEDEC Standard 17 RECOMMENDED OPERATING CONDITIONS Temperature Range Minimum Maximum Commercial 0˚C +70˚C Supply Voltage Range Device 1.8V to 3.6V CAT24FC32A Note: (1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time. (3) This parameter is tested initially and after a design or process change that affects the parameter. (4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V. Doc. No. 1048, Rev. F 2 CAT24FC32A D.C. OPERATING CHARACTERISTICS Over recommended operating conditions, unless otherwise specified Symbol Parameter Min. Typ. Max. Units Test Conditions ILI Input Leakage Current(4) -10 10 µA VIN = GND to VCC ILO Output Leakage Current(4) -10 10 µA VIN = GND to VCC ICC1 Power Supply Current 3 mA fSCL = 400kHz (Operating Write) ICC2 VCC = 3.6V Power Supply Current 400 µA (Operating Read) ISB(1) fSCL = 400kHz VCC = 3.6V Standby Current 0 µA VCC = 3.6V VIN = GND or VCC VIL(2) Input Low Voltage -0.5 0.3VCC V VIH(2) Input High Voltage 0.7VCC VCC + 0.5 V VOL1 Output Low Voltage 0.4 V 2.5V ≤ VCC ≤ 3.6V IOL = 3.0 mA VOL2 Output Low Voltage 0.2VCC V 1.8V ≤ VCC < 2.5V IOL = 3 mA CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 3.6V Symbol CI/O(3) CIN (3) Test Max. Units Conditions Input/Output Capacitance (SDA) 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL, WP) 6 pF VIN = 0V Note: (1) Standby current, ISB < 900 nA; A0, A1, A2, WP connected to GND; SCL, SDA = GND or VCC. (2) VIL min and VIH max are reference values only and are not tested. (3) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (4) I/O pins, SDA and SCL do not obstruct the bus lines if VCC is switched off. 3 Doc. No. 1048, Rev. F CAT24FC32A A.C. CHARACTERISTICS Over recommended operating conditions, unless otherwise specified (Note 1). VCC=1.8V - 3.6V Symbol Min Parameter Typ Max Units fSCL Clock Frequency 400 kHz tSP Input Filter Spike Suppression (SDA, SCL) 50 ns tLOW Clock Low Period 1.3 tHIGH Clock High Period 0.6 tR(2) SDA and SCL Rise Time 20 300 ns tF(2) SDA and SCL Fall Time 20 300 ns tHD:STA Start Condition Hold Time 0.6 tSU:STA Start Condition Setup Time (for a Repeated Start) 0.6 tHD:DAT Data Input Hold Time tSU:DAT µs µs µs µs 0 ns Data In Setup Time 100 ns tSU:STO Stop Condition Setup Time 0.6 µs tSU:WP WP Setup Time 0 µs tHD:WP WP Hold Time 2.5 µs tAA SCL Low to Data Out Valid 900 ns tDH Data Out Hold Time 50 ns tBUF(2) Time the Bus must be Free Before a New Transmission Can Start 1.3 µs tOF(2) Output Fall Time from VIH min to VIL max 20 tWC(3) Write Cycle Time (Byte or Page) 250 ns 5 ms Power-Up Timing (2)(4) Symbol Parameter Min Typ Max Units tPUR Power-Up to Read Operation 1 ms tPUW Power-Up to Write Operation 1 ms Note: (1) Test Conditions according to "AC Test Conditions" Table. (2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested. (3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address. (4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. Doc. No. 1048, Rev. F 4 CAT24FC32A AC TEST CONDITIONS Input pulse voltages 0.2VCC to 0.8VCC Input rise and fall times ≤ 50 ns Input reference voltages 0.3VCC, 0.7VCC Output reference voltages 0.5VCC Output load Current source: IOL = 3mA; CL: 400pF for fSCl max = 400kHz / 100pF for fSCL max = 1 MHz Figure 1. Bus Timing tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tBUF tDH SDA OUT Figure 2. WP Timing 2nd Byte Address 1 8 A7 A0 Data 9 1 8 D7 D0 SCL SDA tSU:WP WP tHD:WP Figure 3. Write Cycle Timing SCL SDA 8TH BIT ACK BYTE n tWR STOP CONDITION 5 START CONDITION ADDRESS Doc. No. 1048, Rev. F CAT24FC32A PIN DESCRIPTION WP: Write Protect SCL: Serial Clock This input controls the device write protect feature. WP pin connected to VSS allows write operations to the entire memory. When this pin is connected to Vcc, the entire memory is write protected. When left floating, an internal pull-down resistor on this input will keep the memory unprotected. Read operations are not affected. The serial clock input clocks all data transferred into or out of the device. The SCL line requires a pull-up resistor if it is driven by an open drain output. SDA: Serial Data/Address A0, A1, A2: Device Address Inputs The bidirectional serial data/address pin is used to transfer all data into and out of the device. The SDA pin is an open drain output and can be wire-ORed with other open drain or open collector outputs. A pull-up resistor must be connected from SDA line to Vcc. The value of the pull-up resistor, Rp, can be calculated based on minimum and maximum values from Figure 4 and Figure 5. (see Note). These inputs are used for extended addressing capability. The A0, A1, A2 pins can be hardwired to VCC or VSS, or left unconnected. When hardwired, up to eight CAT24FC32As may be addressed on a single bus system. When the pins are left unconnected, the default values are zero. The levels on these inputs are compared with corresponding bits, A2, A1, A0, from the slave address byte. Minimum RP as a Function of Supply Voltage (IOL = 3mA @ VOLmax) Minimum RP Value versus Bus Capacitance (Fast Mode I2C Bus / tr max = 300ns) RP max (Kohm) RP min (Kohm) 8.00 1 0.5 0 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 1.6 2 2.4 2.8 3.2 50 3.6 VCC (V) 100 150 200 250 300 350 400 Cbus (pF) Figure 4 Figure 5 Note: According to the Fast Mode I2C bus specification, for bus capacitance up to 200pF, the pull up device can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source (Imax=3mA) or a switched resistor circuit. Doc. No. 1048, Rev. F 6 CAT24FC32A FUNCTIONAL DESCRIPTION SDA when SCL is HIGH. The CAT24FC32A monitors the SDA and SCL lines and will not respond until this condition is met. The CAT24FC32A supports the I 2 C Bus data transmission protocol. This Inter-Integrated Circuit Bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. The transfer is controlled by the Master device which generates the serial clock and all START and STOP conditions for bus access. The CAT24FC32A operates as a Slave device. Both the Master device and Slave device can operate as either transmitter or receiver, but the Master device controls which mode is activated. STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition. DEVICE ADDRESSING After the bus Master sends a START condition, a slave address byte is required to enable the CAT24FC32A for a read or write operation (Figure 7). The four most significant bits of the 8-bit slave address are fixed as binary 1010. The CAT24FC32A uses the next three bits as address bits. The address bits A2, A1 and A0 are used to select which device is accessed from maximum eight devices on the same bus. These bits must compare to their hardwired input pins. The last bit of the slave address specifies whether a read or write operation is to be performed. When this bit is set to “1”, a read operation is initiated, and when set to “0”, a write operation is selected. 2 I C Bus Protocol The features of the I2C bus protocol are defined as follows: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a START or STOP condition (Figure 6). Following the START condition and the slave address byte, the CAT24FC32A monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The CAT24FC32A then performs a read or write operation depending on the state of the R/W bit. START Condition The START condition precedes all commands to the device, and is defined as a HIGH to LOW transition of Figure 6. Start/Stop Timing SDA SCL START BIT STOP BIT Figure 7. Slave Address Bits 1 0 1 0 A2 7 A1 A0 R/W Doc. No. 1048, Rev. F CAT24FC32A Acknowledge WRITE OPERATIONS After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The SDA line remains stable LOW during the HIGH period of the acknowledge related clock pulse (Figure 8). Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address words that are to be written into the address pointers of the CAT24FC32A. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT24FC32A acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to nonvolatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. The CAT24FC32A responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8bit byte. The CAT24FC32A does not generate acknowledge if an internal write cycle is in progress. When the CAT24FC32A begins a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT24FC32A will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. The master must then issue a stop condition to return the CAT24FC32A to the standby power mode and place the device in a known state. Page Write The CAT24FC32A writes up to 32 bytes of data, in a single write cycle, using the Page Write operation. The page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the Master is allowed to send up to 31 additional bytes. After each byte has Figure 8. Acknowledge Timing SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE START Figure 9. Byte Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15—A 8 A7—A 0 S DATA P X XX X A C K A C K X = Don't care bit Doc. No. 1048, Rev. F S T O P 8 A C K A C K CAT24FC32A WRITE PROTECTION been transmitted, CAT24FC32A will respond with an acknowledge, and internally increment the five low order address bits by one. The high order bits remain unchanged. The Write Protection feature allows the user to protect against inadvertent programming of the memory array. If the WP pin is connected to VCC, the entire memory array is protected and becomes read only. The CAT24FC32A will accept both slave and byte addresses, but the memory location accessed is protected from programming by the device’s failure to send an acknowledge after the first byte of data is received. The WP input is sampled in the end of acknowledge pulse after second address byte, accordingly with setup and hold times relative to negative clock edge (Figure 2). If the Master transmits more than 32 bytes before sending the STOP condition, the address counter ‘wraps around’, and previously transmitted data will be overwritten. When all 32 bytes are received, and the STOP condition has been sent by the Master, the internal programming cycle begins. At this point, all received data is written to the CAT24FC32A in a single write cycle. Acknowledge Polling READ OPERATIONS Disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host’s write operation, CAT24FC32A initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If CAT24FC32A is still busy with the write operation, no ACK will be returned. If CAT24FC32A has completed the write operation, an ACK will be returned and the host can then proceed with the next read or write operation. The READ operation for the CAT24FC32A is initiated in the same manner as the write operation with one exception, that R/W bit is set to one. Three different READ operations are possible: Immediate/Current Address READ, Selective/Random READ and Sequential READ. Immediate/Current Address Read The CAT24FC32A’s address counter contains the address of the last byte accessed, incremented by one. In other words, if the last READ or WRITE access was Figure 10. Page Write Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS BYTE ADDRESS A15—A 8 A7—A 0 S DATA DATA n S T O P DATA n+31 P X XX X A C K A C K A C K A C K A C K A C K A C K X=Don't care bit Figure 11. Immediate Address Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS DATA P S A C K SCL SDA S T O P 8 N O A C K 9 8TH BIT DATA OUT NO ACK 9 STOP Doc. No. 1048, Rev. F CAT24FC32A to address N, the READ immediately following would access data from address N+1. If N=E (where E=4095), then the counter will ‘wrap around’ to address 0 and continue to clock out data. After the CAT24FC32A receives its slave address information (with the R/W bit set to one), it issues an acknowledge, then transmits the 8 bit byte requested. The master device does not send an acknowledge, but will generate a STOP condition. Sequential Read The Sequential READ operation can be initiated by either the Immediate Address READ or Selective READ operations. After the CAT24FC32A sends the initial 8-bit byte requested, the Master will respond with an acknowledge which tells the device it requires more data. The CAT24FC32A will continue to output an 8-bit byte for each acknowledge sent by the Master. The operation will terminate when the Master fails to respond with an acknowledge, thus sending the STOP condition. Selective/Random Read Selective/Random READ operations allow the Master device to select at random any memory location for a READ operation. The Master device first performs a ‘dummy’ write operation by sending the START condition, slave address and byte addresses of the location it wishes to read. After CAT24FC32A acknowledges, the Master device sends the START condition and the slave address again, this time with the R/W bit set to one. The CAT24FC32A then responds with its acknowledge and sends the 8-bit byte requested. The master device does not send an acknowledge but will generate a STOP condition. The data being transmitted from CAT24FC32A is outputted sequentially with data from address N followed by data from address N+1. The READ operation address counter increments all of the CAT24FC32A address bits so that the entire memory array can be read during one operation. After the last memory address is read out, the counter will ‘wrap around’ and continue to clock out data bytes. Figure 12. Selective Read Timing BUS ACTIVITY: MASTER SDA LINE S T A R T SLAVE ADDRESS S T A R T BYTE ADDRESS A15—A8 A7—A0 S SLAVE ADDRESS S T O P DATA P S XXXX A C K A C K A C K A C K N O A C K X = Don't care bit Figure 13. Sequential Read Timing BUS ACTIVITY: MASTER SLAVE ADDRESS DATA n DATA n+1 DATA n+2 S T O P DATA n+x SDA LINE P A C K A C K A C K A C K N O A C K Doc. No. 1048, Rev. F 10 CAT24FC32A ORDERING INFORMATION Prefix Device # CAT Suffix 24FC32A Optional Company ID TE13 K Rev A(2) Tape & Reel Product Number Package P: PDIP K: SOIC (EIAJ) J: SOIC (JEDEC) U: TSSOP L: PDIP (Lead free, Halogen free) X: SOIC (EIAJ, Lead free, Halogen free) W: SOIC (JEDEC, Lead free, Halogen free) Y: TSSOP (Lead free, Halogen free) Die Revision Notes: (1) The device used in the above example is a CAT24FC32AK-TE13 (SOIC, Commercial Temperature, Tape & Reel) (2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA). For additional information, please contact your Catalyst sales office. REVISION HISTORY Date Revision Comments 12/10/2003 C Eliminated Commercial temperature range 04/18/2004 D Delete data sheet designation Add Lead Free Logo Update Features Update Ordering Information Add Revision History Update Rev Number 7/7/2004 E Add die revision to Ordering Information 11/04/2004 F Update Features Update Recommended Operating Conditions Update Ordering Information 11 Doc. No. 1048, Rev. F Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following: DPP ™ AE2 ™ Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000. 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Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete. Catalyst Semiconductor, Inc. Corporate Headquarters 1250 Borregas Avenue Sunnyvale, CA 94089 Phone: 408.542.1000 Fax: 408.542.1200 www.catalyst-semiconductor.com Publication #: Revison: Issue date: 1048 F 11/04/04