AVAGO ACPL-K73L-000E Single-channel and dual-channel high speed 15 mbd cmos optocoupler with glitch-free power-up feature Datasheet

ACPL-W70L-000E and ACPL-K73L-000E
Single-channel and Dual-channel High Speed 15 MBd
CMOS optocoupler with Glitch-Free Power-Up Feature
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Features
The ACPL-W70L (single-channel) and ACPL-K73L (dualchannel) are 15 MBd CMOS optocouplers in SSOIC-6 and
SSOIC-8 package respectively. The optocouplers utilize the
latest CMOS IC technology to achieve outstanding performance with very low power consumption. Basic building
blocks of ACPL-W70L and ACPL-K73L are high speed LEDs
and CMOS detector ICs. Each detector incorporates an integrated photodiode, a high speed transimpedance amplifier, and a voltage comparator with an output driver.
• +3.3V and 5 V CMOS compatibility
• 25ns max. pulse width distortion
• 55ns max. propagation delay
• 40ns max. propagation delay skew
• High speed: 15 MBd min
• 10 kV/µs minimum common mode rejection
• –40 to 105°C temperature range
• Glitch-Free Power-UP Feature
Component Image
• Safety and regulatory approvals:
ACPL-W70L
6 VDD
Anode 1
- UL recognized: 5000 V rms for 1 min. per UL 1577
- CSA component acceptance Notice #5
- IEC/EN/DIN EN 60747-5-2 approved Option 060
5 Vo
NC* 2
Applications
• Digital field bus isolation:
Cathode 3
4 GND
SHIELD
- CANBus, RS485, USB
• Multiplexed data transmission
• Computer peripheral interface
ACPL-K73L
Anode1 1
8 VDD
7 Vo 1
• Microprocessor system interface
• DC/DC converter
Cathode1 2
Cathode2 3
6 Vo 2
Anode2 4
5 GND
SHIELD
TRUTH TABLE
LED
OFF
ON
VO, OUTPUT
L
H
A 0.1µF bypass capacitor must be connected between pins 4 and 6 for
ACPL-W70L and pins 5 and 8 for ACPL-K73L.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Ordering Information
ACPL-W70L and ACPL-K73L will be UL Recognized with 5000 Vrms for 1 minute per UL1577.
Option
Part number
RoHS
Compliant
Package
Surface
Mount
ACPL-W70L
-000E
SSO-6
X
ACPL-K73L
-500E
X
-060E
X
-560E
X
-000E
SSO-8
Gull Wing
Tape&
Reel
X
X
X
-500E
X
-060E
X
-560E
X
X
X
UL 5000 Vrms/
1 Minute
rating
IEC/EN/DIN EN
60747-5-2
Quantity
X
100 per tube
X
1000 per reel
X
X
100 per tube
X
X
1000 per reel
X
80 per tube
X
1000 per reel
X
X
80 per tube
X
X
1000 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
ACPL-W70L-500E to order product of stretched SO-6 package in Tape and Reel packaging in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
2
Package Dimensions
ACPL-W70L (Stretched SO-6 Package)
LAND PATTERN RECOMMENDATION
12.65 (0.498)
1.27 (0.050) BSG
0.381 0.127
(0.015 0.005)
1
6
2
5
3
4
+0.127
6.807 0
(0.268 +0.005)
- 0.000
0.45 (0.018)
7
45
+0.254
4.580 0
+0.010
(0.180
)
- 0.000
0.76 (0.030)
1.91 (0.075)
1.590 0.127
(0.063 0.005)
7
3.180 0.127
(0.125 0.005)
0.20 0.10
(0.008 0.004)
0.750 0.250
(0.0295 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.1 mm (0.004 INCHES).
11.50 0.250
(0.453 0.010)
ACPL-K73L (Stretched S0-8 Package)
LAND PATTERN RECOMMENDATION
0.381 0.13
(0.015 0.005)
0.450 (0.018)
1
8
2
7
3
6
4
5
7
45
3
+0.25
5.850 0
+0.010
(0.230
)
- 0.000
1.905 (0.1)
1.590 0.127
(0.063 0.005)
7
3.180 0.127
(0.125 0.005)
0.200 0.100
(0.008 0.004)
0.750 0.250
(0.0295 0.010)
12.650 (0.5)
1.270 (0.050) BSG
6.807 0.127
(0.268 0.005)
11.5 0.250
(0.453 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.1 mm (0.004 INCHES).
Solder Reflow Thermal Profile
300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
200
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
TEMPERATURE (°C)
2.5 C ± 0.5 °C/SEC.
30
SEC.
160°C
150°C
140°C
SOLDERING
TIME
200°C
30
SEC.
3°C + 1°C/–0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
50
0
100
150
Recommended Pb-Free IR Profile
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
TEMPERATURE
Tsmax
Tsmin
tp
20-40 SEC.
RAMP-UP
3 °C/SEC. MAX.
RAMP-DOWN
6 °C/SEC. MAX.
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
The ACPL-W70L and ACPL-K73L are approved by the following organizations:
UL
Recognized under UL 1577, component recognition program, File E55361.
CSA
Approved under CSA Component Acceptance Notice #5,
File CA88324.
IEC/EN/DIN EN 60747-5-2
Approval under:
IEC 60747-5-2:1997 + A1:2002
t 25 °C to PEAK
TIME
Notes:
The time from 25 °C to peak temperature = 8 minutes max.
Tsmax = 200 °C, Tsmin = 150 °C
Non-halide flux should be used
4
250
Regulatory Information
260 +0/-5 °C
150 - 200 °C
200
TIME (SECONDS)
Note: Non-halide flux should be used.
Tp
217 °C
TL
PEAK
TEMP.
230°C
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884Teil 2):2003-01 (Option 060 only)
Parameter
Symbol
Value
Units
Conditions
Minimum External Air
Gap (Clearance)
L(I01)
8.0
mm
Measured from input terminals to output
terminals, shortest distance through air.
Minimum External
Tracking (Creepage)
L(I02)
8.0
mm
Measured from input terminals to output terminals, shortest distance path along body.
0.08
mm
Insulation thickness between emitter and
detector; also known as distance through
insulation.
≥175
Volts
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic
Gap (Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
IIIa
All Avago Technologies data sheets report the creepage
and clearance inherent to the optocoupler component itself. These dimensions are needed as a starting point for
the equipment designer when determining the circuit
insulation requirements. However, once mounted on a
printed circuit board, minimum creepage and clearance
requirements must be met as specified for individual
equipment standards. For creepage, the shortest distance
Material Group (DIN VDE 0110, 1/89, Table 1)
path along the surface of a printed circuit board between
the solder fillets of the input and output leads must be
considered.
There are recommended techniques such as grooves
and ribs which may be used on a printed circuit board to
achieve desired creepage and clearances. Creepage and
clearance distances will also change depending on factors
such as pollution degree and insulation level.
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics*
Description
Symbol
Option 060 Units
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage 150 Vrms
for rated mains voltage 300 Vrms
for rated mains voltage 450 Vrms
for rated mains voltage 600 Vrms
for rated mains voltage 1000 Vrms
I – IV
I - III
I – III
I – III
I – III
Climatic Classification
55/105/21
Pollution Degree (DIN VDE 0110/1.89)
2
Maximum Working Insulation Voltage
VIORM
1140
Vpeak
Input to Output Test Voltage, Method b**
VPR
2137
Vpeak
Input to Output Test Voltage, Method a**
VIORM x 1.5=VPR, Type and Sample Test, tm=60 sec, Partial discharge < 5 pC
VPR
1710
Vpeak
Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec)
VIOTM
8000
Vpeak
Safety-limiting values – maximum values allowed in the event of a failure, also see Figure 2.
Case Temperature
Input Current
Output Power
TS
IS, INPUT
PS, OUTPUT
175
230
600
°C
mA
mW
Insulation Resistance at TS, VIO = 500 V
RIO
>109
W
VIORM x 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
Note:
* Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application.
Surface mount classification is class A in accordance with CECCOO802.
** Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles.
These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be ensured by
means of protective circuits. The surface mount classification is Class A in accordance with CECC 00802.
5
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
–55
+125
°C
Ambient Operating Temperature
TA
–40
+105
°C
Supply Voltages
VDD
0
6
Volts
Output Voltage
VO
–0.5
VDD +0.5
Volts
Average Forward Input Current
IF
-
10
mA
Average Output Current
Io
-
10
mA
Lead Solder Temperature
260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile
See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Ambient Operating Temperature
TA
–40
+105
°C
Supply Voltages
VDD
4.5
5.5
V
3.0
3.6
V
Input Current (ON)
IF
4
8
mA
Supply Voltage Slew Rate[1]
SR
0.5
500
V/ms
Electrical Specifications
Over recommended temperature (TA = –40°C to +105°C), 3.0V≤VDD ≤ 3.6V and 4.5 V ≤VDD ≤ 5.5 V.
All typical specifications are at TA=+25°C , VDD= +3.3V.
Parameter
Symbol
Part Number Min.
Typ.
Max.
Units
Test Conditions
1.5
1.85
V
IF = 6 mA
V
IR = 10 µA
Input Forward Voltage VF
1.2
Input Reverse
Breakdown Voltage
BVR
5.0
Logic High Output
Voltage
VOH
VDD-1
VDD-0.3
V
IF = 6 mA, IO = -4 mA, VDD=3.3 V
VDD-1
VDD-0.2
V
IF = 6 mA, IO = -4 mA, VDD=5 V
Logic Low Output
Voltage
VOL
Input Threshold
Current
ITH
Logic Low Output
Supply Current
IDDL
Logic Low Output
Supply Current
IDDH
6
0.2
0.8
V
IF = 0 mA, IO = 4 mA, VDD=3.3 V
0.2
0.8
V
IF = 0 mA, IO = 4 mA, VDD=5 V
1
3
mA
IOL = 20 µA
ACPL-W70L
4.1
6.5
mA
IF = 0 mA
ACPL-K73L
8.2
13
mA
IF = 0 mA
ACPL-W70L
3.8
6
mA
IF = 6 mA
ACPL-K73L
7.6
12
mA
IF = 6 mA
Switching Specifications
Over recommended temperature (TA = –40°C to +105°C), 3.0V≤VDD ≤ 3.6V and 4.5 V ≤VDD ≤ 5.5 V.
All typical specifications are at TA=+25°C, VDD = +3.3V.
Parameter
Symbol
Propagation Delay Time
to Logic Low Output[2]
Min.
Typ.
Max.
Units
Test Conditions
tPHL
23
55
ns
IF = 6 mA, CL= 15pF
CMOS Signal Levels
Propagation Delay Time
to Logic High Output[2]
tPLH
27
55
ns
IF = 6 mA, CL= 15pF
CMOS Signal Levels
Pulse Width
tPW
66.7
Pulse Width Distortion[3]
|PWD|
0
Propagation Delay Skew[4]
tPSK
Output Rise Time
(10% – 90%)
tR
Output Fall Time
(90% - 10%)
tF
Common Mode Transient Immunity
at Logic High Output[5]
| CMH |
Common Mode Transient Immunity
at Logic Low Output[6]
ns
4
25
ns
IF = 6 mA, CL= 15pF
CMOS Signal Levels
40
ns
IF = 6 mA, CL= 15pF
CMOS Signal Levels
3.5
ns
IF = 6 mA, CL= 15pF
CMOS Signal Levels
3.5
ns
IF = 0 mA, CL= 15pF
CMOS Signal Levels
10
15
kV/µs
VCM = 1000 V, TA = 25°C, IF = 6 mA
| CML |
10
15
kV/µs
VCM = 1000 V, TA = 25°C, IF = 0 mA
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Input-Output Insulation
II-O
1.0
µA
45% RH, t = 5 s
VI-O = 3 kV DC,
TA = 25°C
Input-Output Momentary
Withstand Voltage
VISO
Vrms
RH ≤ 50%, t = 1 min.,
TA = 25°C
Input-Output Resistance
R I-O
10 12
W
V I-O = 500 V dc
Input-Output Capacitance
C I-O
0.6
pF
f = 1 MHz, TA = 25°C
Package Characteristics
All Typical at TA = 25°C.
5000
Notes:
1. Slew rate of supply voltage ramping is recommended to ensure no glitch more than 1V to appear at the output pin.
2. tPHL propagation delay is measured from the 50% level on the rising edge of the input pulse to the 50% level on the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the falling edge of the input pulse to the 50% level on the rising edge of the VO signal.
3. PWD is defined as |tPHL - tPLH|.
4. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
5. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
6. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
7
1.600
10
Ith - INPUT THRESHOLD CURRENT-mA
VF
0.1
0.01
I DDH -LOGIC HIGH OUTPUT SUPPLY CURRENT-mA
tp – PROPAGATION DELAY; PWD-Pulse Width
h
Distortion – ns
1.4
1.5
VF - FORWARD VOLTAGE-V
Figure 1. Typical input diode forward characteristic
12
35
1.2
1.3
1.6
10
8
6
4
VDD=5V
VDD=3.3V
2
0
-40
20
40
60
80
100
T A -TEMPERATURE- oC
Figure 3. Typical logic high output supply current vs. temperature for dual
channel (ACPL-K73L)
30
-20
0
t PHL CH1
20
t PHL CH2
10
5 VDD=5V
TA=25°C
0
5
4
t PLH CH1
|PWD| CH1
|PWD| CH2
6
7
8
IF – PULSE INPUT CURRENT – mA
9
10
Figure 5. Typical switching speed vs. pulse input current at 5V supply voltage
8
1.000
0.800
I OL =20uA
0.600
5V
3.3V
0.400
0.200
-40
-20
20
40
60
80
T A-TEMPERATURE- oC
Figure 2. Typical input threshold current vs. temperature
0
100
120
12
10
8
6
4
VDD=5V
VDD=3.3V
2
0
-40
-20
20
40
60
80
100
T A-TEMPERATURE- oC
Figure 4. Typical logic low output supply current vs. temperature for dual
channel (ACPL-K73L)
35
t PLH CH2
25
15
1.200
0.000
IDDL -LOGIC LOW OUTPUT SUPPLY CURRENT-mA
TA=25°C
1
1.400
tp – PROPAGATION DELAY; PWD-Pulse
Width Distortion – ns
IF - FORWARD CURRENT-mA
IF
0
t PLH CH2
30
t PHL CH1
25
20
15
t PLH CH1
t PHLCH2
10
5 VDD=5V
TA=25°C
0
5
4
|PWD| CH1
|PWD| CH2
6
7
8
IF – PULSE INPUT CURRENT – mA
9
Figure 6. Typical switching speed vs. pulse input current at 3.3V supply
voltage
10
1.8
V F FORWARD VOLTAGE-V
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
-40
-20
0
20
40
60
T A-TEMPERATURE- o C
80
100
Figure 7. Typical VF vs. temperature.
Application Information
Bypassing and PC Board Layout
The ACPL-W70L and ACPL-K73L optocouplers are extremely easy to use. ACPL-W70L and ACPL-K73L provide
CMOS logic output due to the high-speed CMOS IC technology used.
The external components required for proper operation
are the input limiting resistor and the output bypass capacitor. Capacitor values should be between 0.01 µF and
0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm.
Propagation Delay, Pulse-Width Distortion and Propagation Delay
Skew
Propagation delay is a figure of merit which describes how
quickly a logic signal propagates through a system. The
propagation delay from low to high (tPLH) is the amount
of time required for an input signal to propagate to the
output, causing the output to change from low to high.
Similarly, the propagation delay from high to low (tPHL) is
the amount of time required for the input signal to propagate to the output, causing the output to change from
high to low (see Figure 9).
9
Pulse-width distortion (PWD) results when tPLH and tPHL
differ in value. PWD is defined as the difference between
tPLH and tPHL and often PWD is defined as the difference
between tPLH and tPHL and often determines the maximum data rate capability of a transmission system. PWD
can be expressed in percent by dividing the PWD (in ns)
by the minimum pulse width (in ns) being transmitted.
Typically, PWD on the order of 20-30% of the minimum
pulse width is tolerable; the exact figure depends on the
particular application (RS232, RS422, T-1, etc.).
Propagation delay skew, tPSK, is an important parameter
to consider in parallel data applications where synchronization of signals on parallel data lines is a concern.
If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the
data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large
enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers.
Propagation delay skew is defined as the difference between the minimum and maximum propagation delays,
either tPLH or tPHL, for any given group of optocouplers
which are operating under the same conditions (i.e., the
same supply voltage, output load, and operating temperature). As illustrated in Figure 10, if the inputs of a group of
optocouplers are switched either ON or OFF at the same
IF
1
3
C
5
4
Vo
GND2
IF1
1
8
GND 1
2
7
GND 1
3
IF2
4
ACPL-W70L
XXX
YWW
GND1
XXX
YWW
2
V DD
6
VDD
C
VO1
VO2
6
5
GND 2
ACPL-K73L
C=0.01µF to 0.1µF
Figure 8. Recommended printed circuit board layout
VI
DATA
50%
INPUTS
2.5 V,
CMOS
VO
CLOCK
tPSK
VI
50%
DATA
OUTPUTS
VO
2.5 V,
CMOS
tPSK
CLOCK
tPSK
Figure 9. Propagation delay skew waveform
Figure 10. Parallel data transmission example.
time, tPSK is the difference between the shortest propagation delay, either tPHL or tPHL, and the longest propagation
delay, either tPHL or tPHL. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate.
Figure 10 shows that there will be uncertainty in both the
data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal
might arrive before all of the data outputs have settled, or
some of the data outputs may start to change before the
clock signal has arrived.
Figure 10 is the timing diagram of a typical parallel data
application with both the clock and the data lines being
sent through optocouplers. The figure shows data and
clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both
edges of the clock signal are being used to clock the data;
if only one edge were used, the clock signal would need
to be twice as fast.
Propagation delay skew represents the uncertainty of
where an edge might be after being sent through an optocoupler.
10
From these considerations, the absolute minimum pulse
width that can be sent through optocouplers in a parallel
application is twice tPSK. A cautious design should use a
slightly longer pulse width to ensure that any additional
uncertainty in the rest of the circuit does not cause a
problem.
The tPSK specified optocouplers offer the advantages of
guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, and power supply ranges.
Powering Sequence
Speed Improvement
VDD needs to achieve a minimum level of 3V before powering up the output connecting component.
A peaking capacitor can be placed across the input current limit resistor (Figure 11) to achieve enhanced speed
performance. The value of the peaking cap is dependent
to the rise and fall time of the input signal and supply voltages and LED input driving current (If ). Figure 12 shows
significant improvement of propagation delay and pulse
with distortion with added 100pF peak capacitor at driving current of 6mA and 5V power supply.
Input Limiting Resistor
ACPL-W70L and ACPL-K73L are direct current driven (Figure 8), and thus eliminate the need for input power supply.
To limit the amount of current flowing through the LED, it
is recommended that a 530ohm resistor is connected in
series with anode of LED (i.e. Pin 1 for ACPL-W70L, Pin 1
and P4 for ACPL-K73L) at 5V input signal. At 3.3V input
signal, it is recommended to connect 250ohm resistor in
series with anode of LED. The recommended limiting resistors is based on the assumption that the driver output
impedence is 50Ω (as shown in Figure 11).
R drv =
50Ω
Vi
+
C peak
Rlimit
0.1µF
-
t PHL
25
VO
5
-40
-20
0
40
5
60
80
40
60
80
100
tPLH
30
25
t PHL
20
t PLH
5
40
20
tPHL
35
10
|PWD|
20
10
|PWD|
15
t PLH
10
100
0
With peaking cap
Without peaking cap
|PWD|
-40
-20
0
20
40
60
80
100
(ii) VDD2=3.3V, Cpeak=100pF, Rlimit=250Ω
Figure 12. Improvement of tp and PWD with added 100pF peaking capacitor
in parallel of input limiting resistor.
11
25
15
t PLH
(i) VDD2=5V, Cpeak=100pF, Rlimit=530Ω
15
30
20
5
GND 2
SHIELD
0
With peaking cap
Without peaking cap
t PHL
20
0
-20
35
30
10
35
Figure 11. Connection
t PLH of peaking capacitor (Cpeak) in parallel of the input
limiting
resistor (Rllimit) to improve speed performance
30
t PHL
With peaking cap
25
Without peaking cap
t PHL
20
-40
40
t PLH
15
VDD2
GND1
0
35
0
-40
-
Common Mode Rejection for ACPL-W70L AND ACPL-K73L
Figure 13 shows the recommended driving circuit for the
ACPL-W70L and ACPL-K73L for optimal common-mode rejection performance. Two LED-current setting resistors are
used instead of one. This is to balance the common mode
impedance at LED anode and cathode. Common-mode
transients can capacitively couple from the LED anode (or
cathode) to the output-side ground causing current to be
shunted away from the LED (which can be bad if the LED
is on) or conversely cause current to be injected into the
LED (bad if the LED is meant to be off ). Figure14 shows the
parasitic capacitances which exists between LED anode/
cathode and output ground (CLA and CLC). Also shown in
Figure 14 on the input side is an AC-equivalent circuit.
Table 1 indicates the directions of ILP and ILN flow depending on the direction of the common-mode transient. For
transients occurring when the LED is on, common-mode
rejection (CML, since the output is in the “low” state) depends upon the amount of LED current drive (IF). For conditions where IF is close to the switching threshold (ITH),
CML also depends on the extent which ILP and ILN balance
1/2R total
each other. In other words, any condition where commonmode transients cause a momentary decrease in IF (i.e.
when dVCM/dt>0 and |IFP| > |IFN|, referring to Table 1) will
cause common-mode failure for transients which are fast
enough.
Likewise for common-mode transients which occur when
the LED is off (i.e. CMH, since the output is “high”), if an imbalance between ILP and ILN results in a transient IF equal
to or greater than the switching threshold of the optocoupler, the transient “signal” may cause the output to spike
below 2V (which constitutes a CMH failure).
By using the recommended circuit in Figure 13, good CMR
can be achieved. The resistors recommended in Figure 13
include both the output impedence of the logic driver circuit and the external limiting resistor. The balanced ILEDsetting resistors help equalize the common mode voltage
change at anode and cathode to reduce the amount by
which ILED is modulated from transient coupling through
CLA and CLC.
Rtotal =300Ω for VDD=3.3V
= 580Ω for VDD=5V
V DD2
V DD1
0.1µF
1/2R total
74LS04 OR ANY TOTEMPOLE OUTPUT LOGIC GATE
VO
GND 2
SHIELD
GND 1
VDD
ACPL-W70L
Figure 13. Recommended drive circuit for ACPL-W70L and ACPL-K73L for high-CMR
½ R total
ILP
VO
C LA
½ R total
530 Ω
VDD2
0.1µF
15pF
ILN
C LC
SHIELD
74L504
(ANY
TTL/CMOS
GATE)
1
2N3906
(ANY PNP)
LED
3
GND 2
Figure 14. AC equivalent of ACPL-W70L and ACPL-K73L
VDD
12
ACPL-W70L
VDD
ACPL-W70L
530 Ω
1
1
½ R total
VDD2
ILP
VO
C LA
½ R total
0.1µF
Table 1. Effects of Common Mode Pulse Direction on Transient ILED
15pF
ILN
Is Momentarily:
If |ILP| < |ILN|,
LED IF CurrentGND
2
Is Momentarily:
away from LED cathode through CLC
increased
decreased
toward LED cathode through CLC
decreased
increased
If
dVCM/dt Is:
then
ILP Flows:
and
ILN Flows:
positive (>0)
away from LED anode through CLA
negative (<0) toward LED anode through CLA
If |I | < |I |,
LP
LN
C LC
LED
I
Current
F
SHIELD
74L504
(ANY
TTL/CMOS
GATE
VDD
ACPL-W70L
CMR with Other Drive Circuits
CMR performance with drive circuits other than that
½ R total
shown
in Figure 13 may be enhanced by followingVthese
DD2
ILP
guidelines:
VO the
1. Use of drive circuitsC where
current is shunted from
LA
½ R total
LED
in the LED “off” state (as shown 0.1µF
in Figures 15 and
16). This is beneficial for good CMH.
15pF
ILN
2. Use of typical
I
C LC FH
recommendation.
SHIELD
=
6mA
per
datasheet
GND 2
Using any one of the drive circuits in Figures 15-17 with
IF = 6 mA will result in a typical CMR of 10 kV/μs for ACPLW70L AND ACPL-K73L, as long as the PC board layout
practices are followed. Figure 15 shows a circuit which can
be used with any totem-pole-output TTL/LSTTL/HCMOS
logic gate. The buffer PNP transistor allows the circuit to
be used with logic devices which have low current-sinking
capability. It also helps maintain the driving-gate powersupply
ground
VDD current at a constant level to minimize
ACPL-W70L
shifting for other devices connected to the input-supply
ground.
530 Ω
VDD
VDD2
VO
5pF
74HC00
(OR ANY
OPEN-COLLECTOR
/OPEN-DRAIN
LOGIC GATE)
74L504
(ANY
TTL/CMOS
GATE)
VDD
530 Ω
74L504
(ANY
TTL/CMOS
74HC00
GATE)
(OR ANY
OPEN-COLLECTOR
/OPEN-DRAIN
LOGIC GATE)
ACPL-W70L LED
1
2N3906
(ANY PNP)
LED
1
3
LED
3
VDD
ACPL-W70L
530 Ω
3
1
Figure 16. TTL open-collector/open drain gate drive circuit for ACPL-W70L
families.
1
530 Ω
530 Ω
2N3906
(ANY PNP)
VD
ACPL-W70L
74HC04
(OR ANY
TOTEM-POLE
OUTPUT LOGIC
GATE)
1
LED
3
LED
3
Figure 17. CMOS gate drive circuit for ACPL-W70L families.
GND 2
When using an open-collector TTL or open-drain CMOS
logic gate, the circuit in Figure 16 may be used. When
using a CMOS gate to drive the optocoupler, the circuit
shown in Figure 17, where the resistor is recommended to
connect to the anode of the LED, may be used.
Figure 15. TTL interface circuit for the ACPl-W70L families.
VDD
-W70L
ACPL-W70L
13
530 Ω
1
74HC0
(OR AN
TOTEM-POL
OUTPUT LOGI
GATE
F
Rlimit
VCM
A
B
IF
VCM
0.1µF
VO
VCM (PEAK)
0V
VDD
SWITCH AT A: I F = 0 mA
SWITCH AT B: I F = 6 mA
VO
SHIELD
Pulse Gen.
VCM
VO
+
VCM (PEAK)
0V
VDD
SWITCH AT A: I F = 0 mA
SWITCH AT B: I F = 6 mA
VO
GND2
VO (min.)
CM H
VO (max.)
GND2
CM L
Figure 18. Test circuit for common mode transient immunity and typical
waveforms.
For product information and a complete list of distributors, please go to our web site:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved.
AV02-1267EN - October 29, 2012
VO (min.)
CM H
VO (max.)
CM L