AD AD8092ARMZ Low cost, high speed rail-to-rail amplifier Datasheet

Low Cost, High Speed
Rail-to-Rail Amplifiers
AD8091/AD8092
APPLICATIONS
NC 1
AD8091
8
NC
–IN 2
7
+VS
+IN 3
6
VOUT
–VS 4
5
NC
NC = NO CONNECT
02859-001
CONNECTION DIAGRAMS
Figure 1. SOIC-8 (R-8)
VOUT 1
AD8091
5
+VS
4
–IN
–VS 2
+IN 3
02859-003
Low cost single (AD8091), dual (AD8092) amplifiers
Fully specified at +3 V, +5 V, and ±5 V supplies
Single-supply operation
Output swings to within 25 mV of either rail
High-speed and fast settling on 5 V
110 MHz, −3 dB bandwidth (G = +1)
145 V/µs slew rate
50 ns settling time to 0.1%
Good video specifications (G = +2)
Gain flatness of 0.1 dB to 20 MHz; RL = 150 Ω
0.03% differential gain error; RL = 1 kΩ
0.03° differential phase error; RL = 1 kΩ
Low distortion
−80 dBc total harmonic @ 1 MHz; RL = 100 Ω
Outstanding load drive capability
Drives 45 mA, 0.5 V from supply rails
Drives 50 pF capacitive load (G = +1)
Low power of 4.4 mA/Amplifier
Figure 2. SOT23-5 (RT-5)
OUT1 1
AD8092
8
+VS
–IN1 2
7
OUT
+IN1 3
6
–IN2
–VS 4
5
+IN2
NC = NO CONNECT
02859-002
FEATURES
Figure 3. MSOP-8 and SOIC-8 (RM-8, R-8)
Coaxial cable drivers
Active filters
Video switchers
Professional cameras
CCD imaging systems
CDs/DVDs
GENERAL DESCRIPTION
The AD8091 (single) and AD8092 (dual) are low cost, voltage
feedback, high speed amplifiers designed to operate on +3 V,
+5 V, or ±5 V supplies. They have true single-supply capability,
with an input voltage range extending 200 mV below the
negative rail and within 1 V of the positive rail.
Despite their low cost, the AD8091/AD8092 provide excellent
overall performance and versatility. The output voltage swing
extends to within 25 mV of each rail, providing the maximum
output dynamic range with excellent overdrive recovery. This
makes the AD8091/AD8092 useful for video electronics, such
as cameras, video switchers, or any high speed portable
equipment. Low distortion and fast settling make them ideal for
active filter applications.
The AD8091/AD8092 offer a low power supply current and can
operate on a single 3 V power supply. These features are ideally
suited for portable and battery-powered applications where size
and power are critical.
The wide bandwidth and fast slew rate make these amplifiers
useful in many general-purpose, high speed applications where
dual power supplies of up to ±6 V and single supplies from +3
V to +12 V are needed.
This low cost performance is offered in an 8-lead SOIC
(AD8091/AD8092), along with a tiny SOT23-5 (AD8091) and a
MSOP (AD8092).
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
A8091/AD8092
TABLE OF CONTENTS
Specifications..................................................................................... 3
Input-to-Output Coupling ........................................................ 13
Absolute Maximum Ratings............................................................ 7
Driving Capacitive Loads .............................................................. 14
Maximum Power Dissipation ..................................................... 7
Overdrive Recovery ................................................................... 14
ESD Caution.................................................................................. 7
Active Filters ............................................................................... 14
Typical Performance Characteristics ............................................. 9
Sync Stripper ............................................................................... 15
Layout, Grounding, and Bypassing Considerations .................. 13
Single-Supply Composite Video Line Driver ......................... 15
Power Supply Bypassing ............................................................ 13
Outline Dimensions ....................................................................... 17
Grounding ................................................................................... 13
Ordering Guide .......................................................................... 18
Input Capacitance....................................................................... 13
REVISION HISTORY
3/05—Rev. A to Rev. B
Changes to Format .............................................................Universal
Changes to Features.......................................................................... 1
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 18
5/02–Rev. 0 to Rev. A
Edits to Product Description ...........................................................1
Edit to TPC 6 .....................................................................................7
Edits to TPCs 21–24........................................................................10
Edits to Figure 3 ...............................................................................11
2/02—Revision 0: Initial Version
Rev. B | Page 2 of 20
AD8091/AD8092
SPECIFICATIONS
TA = 25°C, VS = 5 V, RL = 2 kΩ to 2.5 V, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion (See Figure 11)
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
AD8091A/AD8092A
Typ
Conditions
Min
G = +1, VO = 0.2 V p-p
G = −1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V, RF = 806 Ω
G = −1, VO = 2 V step
G = +1, VO = 2 V p-p
G = −1, VO = 2 V step
70
110
50
20
MHz
MHz
MHz
100
145
35
50
V/µs
MHz
ns
−67
16
850
0.09
0.03
0.19
0.03
−60
dB
nV/√Hz
fA/√Hz
%
%
Degrees
Degrees
dB
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω to 2.5 V
RL = 1 kΩ to 2.5 V
G = +2, RL = 150 Ω to 2.5 V
RL = 1 kΩ to 2.5 V
f = 5 MHz, G = +2
1.7
TMIN to TMAX
Offset Drift
Input Bias Current
10
1.4
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short-Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
RL = 2 kΩ to 2.5 V
TMIN to TMAX
RL = 150 Ω to 2.5 V
TMIN to TMAX
VCM = 0 V to 3.5 V
RL = 10 kΩ to 2.5 V
RL = 2 kΩ to 2.5 V
RL = 150 Ω to 2.5 V
VOUT = 0.5 V to 4.5 V
TMIN to TMAX
Sourcing
Sinking
G = +1
86
76
72
0.100 to 4.900
0.300 to 4.625
0.1
98
96
82
78
70
−40
Rev. B | Page 3 of 20
10
25
2.5
3.25
0.75
Unit
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
290
1.4
−0.2 to +4
88
kΩ
pF
V
dB
0.015 to 4.985
0.025 to 4.975
0.200 to 4.800
45
45
80
130
50
V
V
V
mA
mA
mA
mA
pF
3
∆VS = ±1 V
Max
4.4
80
12
5
+85
V
mA
dB
°C
A8091/AD8092
TA = 25°C, VS = +3 V, RL = 2 kΩ to +1.5 V, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion (see Figure 11)
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
AD8091A/AD8092A
Typ
Conditions
Min
G = +1, VO = 0.2 V p-p
G = −1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω to 2.5 V, RF = 402 Ω
G = −1, VO = 2 V step
G = +1, VO = 1 V p-p
G = −1, VO = 2 V step
70
110
50
17
MHz
MHz
MHz
90
135
65
55
V/µs
MHz
ns
−47
dB
16
600
nV/√Hz
fA/√Hz
0.11
0.09
%
%
0.24
0.10
−60
Degrees
Degrees
dB
fC = 5 MHz, VO = 2 V p-p, G = −1,
RL = 100 Ω to 1.5 V
f = 10 kHz
f = 10 kHz
G = +2, VCM = 1 V
RL = 150 Ω to 1.5 V
RL = 1 kΩ to 1.5 V
G = +2, VCM = 1 V
RL = 150 Ω to 1.5 V
RL = 1 kΩ to 1.5 V
f = 5 MHz, G = +2
1.6
TMIN to TMAX
Offset Drift
Input Bias Current
10
1.3
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
RL = 2 kΩ
TMIN to TMAX
RL = 150 Ω
TMIN to TMAX
80
74
VCM = 0 V to 1.5 V
RL = 10 kΩ to 1.5 V
RL = 2 kΩ to 1.5 V
RL = 150 Ω to 1.5 V
VOUT = 0.5 V to 2.5 V
TMIN to TMAX
Sourcing
Sinking
G = +1
Rev. B | Page 4 of 20
72
0.075 to 2.9
0.20 to 2.75
0.15
96
94
82
76
Max
10
25
2.6
3.25
0.8
Unit
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
290
1.4
−0.2 to +2.0
88
kΩ
pF
V
dB
0.01 to 2.99
0.02 to 2.98
0.125 to 2.875
45
45
60
90
45
V
V
V
mA
mA
mA
mA
pF
AD8091/AD8092
Parameter
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
Conditions
Min
AD8091A/AD8092A
Typ
3
∆VS = +0.5 V
Rev. B | Page 5 of 20
68
−40
4.2
80
Max
Unit
12
4.8
V
mA
dB
°C
+85
A8091/AD8092
TA = 25°C, VS = ±5 V, RL = 2 kΩ to ground, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Full Power Response
Settling Time to 0.1%
NOISE/DISTORTION PERFORMANCE
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
Differential Gain Error (NTSC)
Differential Phase Error (NTSC)
Crosstalk
DC PERFORMANCE
Input Offset Voltage
AD8091A/AD8092A
Typ
Conditions
Min
G = +1, VO = 0.2 V p-p
G = −1, +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p,
RL = 150 Ω, RF = 1.1 kΩ
G = −1, VO = 2 V step
G = +1, VO = 2 V p-p
G = −1, VO = 2 V step
70
110
50
20
MHz
MHz
MHz
105
170
40
50
V/µs
MHz
ns
−71
16
900
0.02
0.02
0.11
0.02
−60
dB
nV/√Hz
fA/√Hz
%
%
Degrees
Degrees
dB
fC = 5 MHz, VO = 2 V p-p, G = +2
f = 10 kHz
f = 10 kHz
G = +2, RL = 150 Ω
RL = 1 kΩ
G = +2, RL = 150 Ω
RL = 1 kΩ
f = 5 MHz, G = +2
1.8
TMIN to TMAX
Offset Drift
Input Bias Current
10
1.4
TMIN to TMAX
Input Offset Current
Open-Loop Gain
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Short Circuit Current
Capacitive Load Drive
POWER SUPPLY
Operating Range
Quiescent Current/Amplifier
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
RL = 2 kΩ
TMIN to TMAX
RL = 150 Ω
TMIN to TMAX
88
78
VCM = −5 V to +3.5 V
RL = 10 kΩ
RL = 2 kΩ
RL = 150 Ω
VOUT = −4.5 V to +4.5 V
TMIN to TMAX
Sourcing
Sinking
G = +1 (AD8091/AD8092)
72
−4.85 to +4.85
−4.45 to +4.30
0.1
96
96
82
80
68
−40
Rev. B | Page 6 of 20
11
27
2.6
3.5
0.75
Unit
mV
mV
µV/°C
µA
µA
µA
dB
dB
dB
dB
290
1.4
−5.2 to +4.0
88
kΩ
pF
V
dB
−4.98 to +4.98
−4.97 to +4.97
−4.60 to +4.60
45
45
100
160
50
V
V
V
mA
mA
mA
mA
pF
3
∆VS = ±1 V
Max
4.8
80
12
5.5
+85
V
mA
dB
°C
AD8091/AD8092
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range
Operating Temperature Range
Lead Temperature Range (Soldering 10 sec)
Rating
12.6 V
See Figure 4
±VS
±2.5 V
See Figure 4
−65°C to +125°C
−40°C to +85°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
The still-air thermal properties of the package (θJA), ambient
temperature (TA), and the total power dissipated in the package
(PD) can be used to determine the junction temperature of the die.
The junction temperature can be calculated as
TJ = TA + (PD × θ JA )
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). Assuming the load (RL) is referenced to
midsupply, then the total drive power is VS/2 × IOUT, some of
which is dissipated in the package and some in the load
(VOUT × IOUT). The difference between the total drive power and
the load power is the drive power dissipated in the package.
PD = quiescent power + (total drive power − load power )
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8091/AD8092
package is limited by the associated rise in junction temperature
(TJ) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the AD8091/AD8092.
Exceeding a junction temperature of 175°C for an extended
period of time can result in changes in the silicon devices,
potentially causing failure.
⎛V V
⎞ ⎛V 2 ⎞
PD = (VS × I S ) + ⎜ S × OUT ⎟ − ⎜⎜ OUT ⎟⎟
RL ⎠ ⎝ RL ⎠
⎝ 2
RMS output voltages should be considered. If RL is referenced to
VS−, as in single-supply operation, then the total drive power is
VS × IOUT.
If the rms signal levels are indeterminate, then consider the
worst case, when VOUT = VS/4 for RL to midsupply
⎛ VS ⎞
⎜ ⎟
4
PD = (VS × I S ) + ⎝ ⎠
RL
2
In single-supply operation with RL referenced to VS−, worst case
is VOUT = VS/2.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. B | Page 7 of 20
A8091/AD8092
TJ = 150°C
1.5
SOIC-8
MSOP-8
1.0
SOT23-5
0.5
0
–40 –30 –20 –10 0 10 20 30 40 50 60
AMBIENT TEMPERATURE (°C)
Figure 4. Maximum Power Dissipation vs.
Temperature for a Four-Layer Board
Rev. B | Page 8 of 20
02859-004
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the SOIC-8
(125°C/W), SOT23-5 (180°C/W), and MSOP-8 (150°C/W) on a
JEDEC standard four-layer board.
2.0
MAXIMUM POWER DISSIPATION (W)
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA. Care must be taken to minimize parasitic capacitances
at the input leads of high speed op amps as discussed in the
board layout section.
70
80
90
AD8091/AD8092
TYPICAL PERFORMANCE CHARACTERISTICS
3
6.3
1
6.1
G = +5
RF = 2kΩ
–1
G = +1
RF = 0Ω
G = +10
RF = 2kΩ
–2
GAIN FLATNESS (dB)
0
–3
–4
VS = 5V
GAIN AS SHOWN
RF AS SHOWN
RL = 2kΩ
VO = 0.2V p-p
–6
–7
0.1
1
10
FREQUENCY (MHz)
100
6.0
5.9
5.8
5.7
5.6
VS = 5V
5.5 G = +2
RL = 150kΩ
5.4 RF = 806Ω
VO = 0.2V p-p
5.3
0.1
500
Figure 5. Normalized Gain vs. Frequency; VS = +5 V
10
FREQUENCY (MHz)
100
Figure 8. 0.1 dB Gain Flatness vs. Frequency; G = +2
3
9
2
8
VS = +3V
VS = +5V
1
7
0
6
–1
5
GAIN (dB)
GAIN (dB)
1
VS = ±5V
–2
–3
VS = ±5V
VO = 4V p-p
4
VS = +5V
VO = 2V p-p
3
–4
2
VS AS SHOWN
1 G = +2
RL = 2kΩ
0 RF = 2kΩ
VO AS SHOWN
–1
0.1
1
02859-006
–5 VS AS SHOWN
G = +1
–6 RL = 2kΩ
VO = 0.2V p-p
–7
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 6. Gain vs. Frequency vs. Supply
02859-009
–5
02859-005
NORMALIZED GAIN (dB)
6.2
G = +2
RF = 2kΩ
02859-008
2
10
FREQUENCY (MHz)
100
500
Figure 9. Large Signal Frequency Response; G = +2
3
70
2
60
VS = 5V
RL = 2kΩ
–40°C
1
–2
–3
–4
VS = 5V
–5 G = +1
RL = 2kΩ
–6 VO = 0.2V p-p
TEMPERATURE AS SHOWN
–7
0.1
1
10
FREQUENCY (MHz)
40
GAIN
30
0
20
10
–45
PHASE
–90
0
100
500
Figure 7. Gain vs. Frequency vs. Temperature
–135
50° PHASE
MARGIN
–10
–20
0.1
1
10
FREQUENCY (MHz)
–180
100
Figure 10. Open-Loop Gain and Phase vs. Frequency
Rev. B | Page 9 of 20
PHASE (Degrees)
+25°C
02859-007
GAIN (dB)
+85°C
–1
500
02859-010
OPEN-LOOP GAIN (dB)
50
0
A8091/AD8092
–30
VS = 5V, G = +2
RF = 2kΩ, RL = 100Ω
–40
VS = 5V, G = +1
RL = 100Ω
–50
–70
VS = 5V, G = +1
RL = 2kΩ
–80
VS = 5V, G = +2
RF = 2kΩ, RL = 2kΩ
–90
–100
–110
1
2
3
4
5
6
FUNDAMENTAL FREQUENCY (MHz)
7
DIFFERENTIAL
PHASE ERROR (Degrees)
–60
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
0
NTSC SUBSCRIBER (3.58MHz)
RL = 150Ω
VS = 5, G = +2
RF = 2kΩ, RL AS SHOWN
RL = 1kΩ
10
20
30
40
50
60
70
80
90
100
90
100
0.10
RL = 1kΩ
0.05
0
–0.05
RL = 150Ω
–0.10
–0.15
VS = 5, G = +2
RF = 2kΩ, RL AS SHOWN
–0.20
–0.25
8 9 10
02859-014
VS = 3V, G = –1
RF = 2kΩ, RL = 100Ω
02859-011
TOTAL HARMONIC DISTORTION (dBc)
VO = 2V p-p
DIFFERENTIAL
GAIN ERROR (%)
–20
0
10
20
30
40
50
60
70
80
MODULATING RAMP LEVEL (IRE)
Figure 11. Total Harmonic Distortion
Figure 14. Differential Gain and Phase Errors
–30
1000
VS = 5V
–40
10MHz
VOLTAGE NOISE (nA Hz)
WORST HARMONIC (dBc)
–50
–60
–70
–80
5MHz
–90
1MHz
–100
100
10
02859-012
VS = 5V
RL = 2kΩ
G = +2
–120
–130
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V p-p)
4.0
4.5
1
10
5.0
Figure 12. Worst Harmonic vs. Output Voltage
1k
10k
100k
FREQUENCY (Hz)
1M
10M
100
VS = 5V
CURRENT NOISE (pA Hz)
VS = 5V
G = –1
RF = 2kΩ
RL = 2kΩ
3.5
3.0
2.5
2.0
1.5
10
1
0.5
0
0.1
1
FREQUENCY (MHz)
10
50
Figure 13. Low Distortion Rail-to-Rail Output Swing
0.1
10
02859-016
1.0
02859-013
OUTPUT VOLTAGE SWING (THD ≤ 0.5%) (V p-p)
4.0
100
Figure 15. Input Voltage Noise vs. Frequency
5.0
4.5
02859-015
–110
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 16. Input Current Noise vs. Frequency
Rev. B | Page 10 of 20
10M
AD8091/AD8092
–10
20
VS = 5V
10
0
–10
–40
–PSRR
PSRR (dB)
–50
–60
–70
–20
+PSRR
–30
–40
–50
–80
02859-017
–60
–90
–100
0.1
1
10
FREQUENCY (MHz)
100
02859-020
CROSSTALK (dB)
VS = 5V
RF = 2kΩ
–20
RL = 2kΩ
VO = 2V p-p
–30
–70
–80
0.01
500
0.1
Figure 17. AD8092 Crosstalk (Output-to-Output) vs. Frequency
VS = 5V
G = –1
RL = 2kΩ
–10
60
SETTLING TIME TO 0.1% (ns)
–30
–40
–50
–60
–70
–90
–100
0.03
0.1
1
10
FREQUENCY (MHz)
100
40
30
20
10
02859-018
–80
50
02859-021
–20
CMRR (dB)
500
70
VS = 5V
0
0.5
500
Figure 18. CMRR vs. Frequency
1.0
1.5
INPUT STEPS (V p-p)
2.0
Figure 21. Setting Time vs. Input Step
100.000
1.0
VS = 5V
G = +1
VS = 5V
10.000
3.100
1.000
0.310
0.100
0.031
0.010
0.1
1
10
FREQUENCY (MHz)
100
500
Figure 19. Closed-Loop Output Resistance vs. Frequency
0.8
VOH = +85°C
VOH = +25°C
0.7
VOH = –40°C
0.6
VOL = +85°C
0.5
0.4
0.3
VOL = +25°C
0.2
VOL = –40°C
02859-022
OUTPUT SATURATION VOLTAGE (V)
0.9
02859-019
OUTPUT RESISTANCE (Ω)
100
Figure 20. PSRR vs. Frequency
0
31.000
1
10
FREQUENCY (MHz)
0.1
0
0
5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
LOAD CURRENT (mA)
Figure 22. Output Saturation Voltage vs. Load Current
Rev. B | Page 11 of 20
A8091/AD8092
100
VS = 5V
G = +2
RL = 2kΩ
VIN = 1V p-p
OPEN-LOOP GAIN (dB)
RL = 2kΩ
90
3.5V
RL = 150Ω
2.5V
80
1.5V
02859-023
VS = 5V
60
0
0.5
02859-026
70
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
4.0
4.5
5.0
Figure 26. Large Signal Step Response; VS = +5 V, G = +2
Figure 23. Open-Loop Gain vs. Output Voltage
VS = 5V
G = –1
RF = 2kΩ
RL = 2kΩ
VIN = 0.1V p-p
G = +1
RL = 2kΩ
VS = 3V
5V
2.5V
20mV
20ns
02859-024
1V
2µs
02859-027
1.50V
Figure 27. Output Swing; G = −1, RL = 2 kΩ
Figure 24. 100 mV Step Response; G = +1
4V
3V
VS = 5V
G = +1
RL = 2kΩ
VS = ±5V
G = +1
RL = 2kΩ
2V
1V
2.60V
–1V
2.50V
–2V
–4V
50mV
20ns
02859-025
1V
Figure 25. 200 mV Step Response; VS = +5 V, G = +1
Rev. B | Page 12 of 20
20ns
Figure 28. Large Signal Step Response; VS = ±5 V, G = +1
02859-028
–3V
2.40V
AD8091/AD8092
LAYOUT, GROUNDING, AND BYPASSING CONSIDERATIONS
POWER SUPPLY BYPASSING
Power supply pins are actually inputs and care must be taken so
that a noise-free stable dc voltage is applied. The purpose of
bypass capacitors is to create low impedances from the supply
to ground at all frequencies, thereby shunting or filtering a
majority of the noise.
Decoupling schemes are designed to minimize the bypassing
impedance at all frequencies with a parallel combination of
capacitors. Chip capacitors of 0.01 µF or 0.001 µF (X7R or
NPO) are critical and should be as close as possible to the
amplifier package. Larger chip capacitors, such as the 0.1 µF
capacitor, can be shared among a few closely spaced active
components in the same signal path. A 10 µF tantalum
capacitor is less critical for high frequency bypassing and, in
most cases, only one per board is needed at the supply inputs.
GROUNDING
A ground plane layer is important in densely packed PC boards
to spread the current-minimizing parasitic inductances.
However, an understanding of where the current flows in a
circuit is critical to implementing effective high speed circuit
design. The length of the current path is directly proportional to
the magnitude of parasitic inductances and thus the high
frequency impedance of the path. High speed currents in an
inductive ground return create an unwanted voltage noise.
The length of the high frequency bypass capacitor leads are
most critical. A parasitic inductance in the bypass grounding
works against the low impedance created by the bypass
capacitor. Place the ground leads of the bypass capacitors at the
same physical location. Because load currents flow from the
supplies as well, the ground for the load impedance should be at
the same physical location as the bypass capacitor grounds. For
the larger value capacitors, which are intended to be effective at
lower frequencies, the current return path distance is less
critical.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can
be sensitive to parasitic capacitance between the inputs and
ground. A few pF of capacitance reduces the input impedance
at high frequencies, in turn increasing the amplifier’s gain,
causing peaking of the frequency response or even oscillations,
if severe enough. It is recommended that the external passive
components, which are connected to the input pins, be placed
as close as possible to the inputs to avoid parasitic capacitance.
The ground and power planes must be kept at a distance of at
least 0.05 mm from the input pins on all layers of the board.
INPUT-TO-OUTPUT COUPLING
The input and output signal traces should not be parallel to
minimize capacitive coupling between the inputs and output
and to avoid any positive feedback.
Rev. B | Page 13 of 20
A8091/AD8092
DRIVING CAPACITIVE LOADS
10000
A highly capacitive load reacts with the output of the amplifiers,
causing a loss in phase margin and subsequent peaking or even
oscillation, as shown in Figure 29 and Figure 30. There are two
methods to effectively minimize its effect.
Put a small value resistor in series with the output to isolate
the load capacitor from the amplifier’s output stage.
Increase the phase margin with higher noise gains or by
adding a pole with a parallel resistor and capacitor from
−IN to the output.
RS = 3Ω
1000
RS = 0Ω
100
RG
10
RS
VIN
100mV STEP
VOUT
CL
50Ω
8
6
1
1
4
2
3
4
5
6
ACL (V/V)
2
GAIN (dB)
RF
02859-031
•
CAPACITIVE LOAD (pF)
•
VS = 5V
≤30%
OVERSHOOT
Figure 31. Capacitive Load Drive vs. Closed-Loop Gain
0
OVERDRIVE RECOVERY
–2
Overdrive of an amplifier occurs when the output and/or input
range is exceeded. The amplifier must recover from this
overdrive condition. The AD8091/AD8092 recover within 60 ns
from negative overdrive and within 45 ns from positive
overdrive, as shown in Figure 32.
–4
–6
–10
–12
0.1
VS = 5V
G = +1
RL = 2kΩ
CL = 50pF
VO = 200mV p-p
1
02859-029
–8
10
FREQUENCY (MHz)
100
500
Figure 29. Closed-Loop Frequency Response: CL = 50 pF
VS = ±5V
G = +5
RF = 2kΩ
RL = 2kΩ
INPUT 1V/DIV
OUTPUT 2V/DIV
VS = 5V
G = +1
RL = 2kΩ
CL = 50pF
2.60V
2.55V
V/DIV AS SHOWN
100ns
2.40V
02859-032
2.50V
2.45V
50mV
100ns
02859-030
Figure 32. Overdrive Recovery
ACTIVE FILTERS
Figure 30. 200 mV Step Response: CL = 50 pF
As the closed-loop gain is increased, the larger phase margin
allows for large capacitor loads with less peaking. Adding a low
value resistor in series with the load at lower gains has the same
effect. Figure 31 shows the effect of a series resistor for various
voltage gains. For large capacitive loads, the frequency response
of the amplifier is dominated by the series resistor and
capacitive load.
Active filters at higher frequencies require wider bandwidth op
amps to work effectively. Excessive phase shift produced by
lower frequency op amps can significantly impact active filter
performance.
Figure 33 shows an example of a 2 MHz biquad bandwidth filter
that uses three op amps. Such circuits are sometimes used in
medical ultrasound systems to lower the noise bandwidth of the
analog signal before A/D conversion. Note that the unused
amplifiers’ inputs should be tied to ground.
Rev. B | Page 14 of 20
AD8091/AD8092
C1
50pF
VIN
2
R4
2kΩ
R3
1 2kΩ
C2
50pF
6
7
3
R5
2kΩ
6
3
AD8092
VOUT
AD8091
GROUND
+0.4V
GROUND
2
5
AD8092
VBLANK
02859-033
R2
2kΩ
R1
3kΩ
VIDEO WITHOUT SYNC
VIDEO WITH SYNC
R6
1kΩ
3V OR 5V
0.1µF
VIN
3
Figure 33. 2 MHz Biquad Band-Pass Filter
AD8091
2
The frequency response of the circuit is shown in Figure 34.
+
10µF
7
TO A/D
6
100Ω
4
R2
1kΩ
0
+0.8V
(OR 2 × VBLANK)
–10
02859-035
R1
1kΩ
GAIN (dB)
Figure 35. Sync Stripper
–20
The video signal plus sync is applied to the noninverting input
with the proper termination. The amplifier gain is set equal to 2
via the two 1 kΩ resistors in the feedback circuit. A bias voltage
must be applied to R1 for the input signal to have the sync
pulses stripped at the proper level.
02859-034
–30
–40
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 34. Frequency Response of 2 MHz Band-Pass Biquad Filter
SYNC STRIPPER
Synchronizing pulses are sometimes carried on video signals so
as not to require a separate channel to carry the synchronizing
information. However, for some functions, such as A/D
conversion, it is not desirable to have the sync pulses on the
video signal. These pulses reduce the dynamic range of the
video signal and do not provide any useful information for such
a function.
A sync stripper removes the synchronizing pulses from a video
signal while passing all the useful video information. Figure 35
shows a practical single-supply circuit that uses only a single
AD8091. It is capable of directly driving a reverse terminated
video line.
The blanking level of the input video pulse is the desired place
to remove the sync information. The amplifier multiplies this
level by 2. This level must be at ground at the output in order
for the sync stripping action to take place. Because the gain of
the amplifier from the input of R1 to the output is −1, a voltage
equal to 2 × VBLANK must be applied to make the blanking level
come out at ground.
SINGLE-SUPPLY COMPOSITE VIDEO LINE DRIVER
Many composite video signals have their blanking level at
ground and have video information that is both positive and
negative. Such signals require dual-supply amplifiers to pass
them. However, by ac level-shifting, a single-supply amplifier
can be used to pass these signals. The following complications
may arise from such techniques.
Signals of bounded peak-to-peak amplitude that vary in duty
cycle require larger dynamic swing capacity than their
(bounded) peak-to-peak amplitude after they are ac-coupled.
As a worst case, the dynamic signal swing approaches twice the
peak-to-peak value. One of two conditions that define the
maximum dynamic swing requirements is a signal that is
mostly low but goes high with a duty cycle that is a small
fraction of a percent. The opposite condition defines the second
condition.
The worst case of composite video is not quite this demanding.
One bounding condition is a signal that is mostly black for an
entire frame but has a white (full amplitude) minimum width
spike at least once in a frame.
Rev. B | Page 15 of 20
A8091/AD8092
5V
The other extreme is a full white video signal. The blanking
intervals and sync tips of such a signal have negative-going
excursions in compliance with the composite video
specifications. The combination of horizontal and vertical
blanking intervals limit such a signal to being at the highest
(white) level for a maximum of about 75% of the time.
4.99kΩ
+
10µF
0.1µF
COMPOSITE
VIDEO IN
47µF
+
RT
75Ω
7
3
AD8091
10kΩ
2
The input to the circuit in Figure 36 is a standard composite
(1 V p-p) video signal that has the blanking level at ground. The
input network level shifts the video signal by means of ac
coupling. The noninverting input of the op amp is biased to half
of the supply voltage.
1000µF
+
RBT
75Ω
RL
75Ω
4
RF
1kΩ
As a result of the duty cycles between the two extremes, a 1 V pp composite video signal that is multiplied by a gain of 2
requires about 3.2 V p-p of dynamic voltage swing at the output
for an op amp to pass a composite video signal of arbitrary
varying duty cycle without distortion.
Some circuits use a sync tip clamp to hold the sync tips at a
relatively constant level to lower the amount of dynamic signal
swing required. However, these circuits can have artifacts like
sync tip compression unless they are driven by a source with a
very low output impedance. The AD8091/AD8092 have
adequate signal swing when running on a single 5 V supply to
handle an ac-coupled composite video signal.
6
+
10µF
VOUT
0.1µF
RG
1kΩ
220µF
02859-036
4.99kΩ
Figure 36. Single-Supply Composite Video Line Driver
The feedback circuit provides unity gain for the dc biasing of
the input and provides a gain of 2 for any signals that are in the
video bandwidth. The output is ac-coupled and terminated to
drive the line.
The capacitor values were selected for providing minimum tilt
or field time distortion of the video signal. These values would
be required for video that is considered to be studio or
broadcast quality. However, if a lower consumer grade of video,
sometimes referred to as consumer video, is all that is desired,
the values and the cost of the capacitors can be reduced by as
much as a factor of 5 with minimum visible degradation in the
picture.
Rev. B | Page 16 of 20
AD8091/AD8092
OUTLINE DIMENSIONS
3.00
BSC
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497) 1
5
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
8
6.20 (0.2440)
3.00
BSC
4 5.80 (0.2284)
0.50 (0.0196)
× 45°
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
1
5
4.90
BSC
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
0.38
0.22
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
0.23
0.08
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 37. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
Figure 38. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
2.90 BSC
5
4
2.80 BSC
1.60 BSC
1
2
3
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.15 MAX
8°
0°
0.50
0.30
0.22
0.08
SEATING
PLANE
10°
5°
0°
COMPLIANT TO JEDEC STANDARDS MO-178AA
Figure 39. 5-Lead Small Outline Transistor Package [SOT-23]
(RT-5)
Dimensions shown in millimeters
Rev. B | Page 17 of 20
0.60
0.45
0.30
0.80
0.60
0.40
A8091/AD8092
ORDERING GUIDE
Model
AD8091AR
AD8091AR-REEL
AD8091AR-REEL7
AD8091ARZ1
AD8091ARZ-REEL1
AD8091ARZ-REEL71
AD8091ART-R2
AD8091ART-REEL
AD8091ART-REEL7
AD8091ARTZ-R21
AD8091ARTZ-R71
AD8091ARTZ-RL1
AD8092AR
AD8092AR-REEL
AD8092AR-REEL7
AD8092ARZ1
AD8092ARZ-REEL1
AD8092ARZ-REEL71
AD8092ARM
AD8092ARM-REEL
AD8092ARM-REEL7
AD8092ARMZ1
AD8092ARMZ-REEL1
AD8092ARMZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead SOIC
8-Lead SOIC, 13” Tape and Reel
8-Lead SOIC, 7” Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13” Tape and Reel
8-Lead SOIC, 7” Tape and Reel
5-Lead SOT-23
5-Lead SOT-23, 13” Tape and Reel
5-Lead SOT-23, 7” Tape and Reel
5-Lead SOT-23
5-Lead SOT-23, 7” Tape and Reel
5-Lead SOT-23, 13” Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13” Tape and Reel
8-Lead SOIC, 7” Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13” Tape and Reel
8-Lead SOIC, 7” Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
Z = Pb-free part. # denotes lead-free, may be top or bottom marked.
Rev. B | Page 18 of 20
Package Outline
R-8
R-8
R-8
R-8
R-8
R-8
RT-5
RT-5
RT-5
RT-5
RT-5
RT-5
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding Information
HVA
HVA
HVA
HVA#
HVA#
HVA#
HWA
HWA
HWA
HWA#
HWA#
HWA#
AD8091/AD8092
NOTES
Rev. B | Page 19 of 20
A8091/AD8092
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02859–0–3/05(B)
Rev. B | Page 20 of 20