ATMEL AT49F512-90PC 512k 64k x 8 5-volt only flash memory Datasheet

Features
• Single Voltage Operation
•
•
•
•
•
•
•
•
•
– 5V Read
– 5V Reprogramming
Fast Read Access Time - 70 ns
Internal Program Control and Timer
8K bytes Boot Block With Lockout
Fast Erase Cycle Time - 10 seconds
Byte By Byte Programming - 10 µs/Byte
Hardware Data Protection
DATA Polling For End Of Program Detection
Low Power Dissipation
– 30 mA Active Current
– 100 µA CMOS Standby Current
Typical 10,000 Write Cycles
512K (64K x 8)
5-volt Only
Flash Memory
Description
The AT49F512 is a 5-volt-only in-system programmable and erasable Flash Memory.
Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with
Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 70
ns with a power dissipation of just 165 mW over the commercial temperature range.
When the device is deselected, the CMOS standby current is less than 100 µA.
To allow for simple in-system reprogrammability, the AT49F512 does not require high
input voltages for programming. Five-volt-only commands determine the read and
programming operation of the device. Reading data out of the device is similar to
reading from an EPROM. Reprogramming the AT49F512 is performed by erasing the
entire 512K of memory and then programming on a byte by byte basis. The typical
byte programming time is a fast 10 µs. The end of a program cycle can be optionally
(continued)
Pin Configurations
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
I/O0 - I/O7
Data Inputs/Outputs
NC
No Connect
NC
NC
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
VSOP Top View (8 x 14 mm) or
TSOP Top View (8 x 20 mm)
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
WE
NC
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
512K (64K x 8)
5-volt Only
CMOS Flash
Memory
PLCC Top View
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
A12
A15
NC
NC
VCC
WE
NC
A11
A9
A8
A13
A14
NC
WE
VCC
NC
NC
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
4
3
2
1
32
31
30
A0 - A15
DIP Top View
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
14
15
16
17
18
19
20
Function
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
Rev. 1027C–09/98
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
Pin Name
AT49F512
1
detected by the DATA polling feature. Once the end of a
byte program cycle has been detected, a new access for a
read or program can begin. The typical number of program
and erase cycles is in excess of 10,000 cycles.
The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity.
The boot sector is designed to contain user secure code,
and when the feature is enabled, the boot sector is permanently protected from being reprogrammed.
Block Diagram
FFFFH
2000H
1FFFH
0000H
Device Operation
READ: The AT49F512 is accessed like an EPROM. When
CE and OE are low and WE is high, the data stored at the
memory location determined by the address pins is
asserted on the outputs. The outputs are put in the high
impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
ERASURE: Before a byte can be reprogrammed, the 64K
bytes memory array (or 56K bytes if the boot block featured
is used) must be erased. The erased state of the memory
bits is a logical “1”. The entire device can be erased at one
time by using a 6-byte software code. The chip erase code
consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip
Erase Cycle Waveforms).
After the chip erase has been initiated, the device will internally time the erase operation so that no external clocks
are required. The maximum time needed to erase the
whole chip is tEC. If the boot block lockout feature has been
enabled, the data in the boot sector will not be erased.
BYTE PROGRAMMING: Once the memory array is
erased, the device is programmed (to a logical “0”) on a
byte-by-byte basis. Please note that a data “0” cannot be
programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the
internal device command register and is a 4 bus cycle
operation (please refer to the Command Definitions table).
The device will automatically generate the required internal
program pulses.
The program cycle has addresses latched on the falling
edge of WE or CE, whichever occurs last, and the data
2
AT49F512
latched on the rising edge of WE or CE, whichever occurs
first. Programming is completed after the specified tBP cycle
time. The DATA polling feature may also be used to indicate
the end of a program cycle.
BOOT BLOCK PROGRAMMING LOCKOUT: The device
has one designated block that has a programming lockout
feature. This feature prevents programming of data in the
designated block once the feature has been enabled. The
size of the block is 8K bytes. This block, referred to as the
boot block, can contain secure code that is used to bring up
the system. Enabling the lockout feature will allow the boot
code to stay in the device while data in the rest of the
device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is
optional to the user. The address range of the boot block is
0000H to 1FFFH.
Once the feature is enabled, the data in the boot block can
no longer be erased or programmed. Data in the main
memory block can still be changed through the regular programming method. To activate the lockout feature, a series
of six program commands to specific addresses with specific data must be performed. Please refer to the Command
Definitions table.
BOOT BLOCK LOCKOUT DETECTION: A software
method is available to determine if programming of the boot
block section is locked out. When the device is in the software product identification mode (see Software Product
Identification Entry and Exit sections) a read from address
location 00002H will show if programming the boot block is
locked out. If the data on I/O0 is low, the boot block can be
programmed; if the data on I/O0 is high, the program lock-
AT49F512
out feature has been activated and the block cannot be
programmed. The software product identification code
should be used to return to standard operation.
PRODUCT IDENTIFICATION: The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external programmer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING: The AT49F512 features DATA polling to
indicate the end of a program cycle. During a program
cycle an attempted read of the last byte loaded will result in
the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all
outputs and the next cycle may begin. DATA polling may
begin at any time during the program cycle.
TOGGLE BIT: In addition to DATA polling the AT49F512
provides another method for determining the end of a program or erase cycle. During a program or erase operation,
successive attempts to read data from the device will result
in I/O6 toggling between one and zero. Once the program
cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time
during a program cycle.
HARDWARE DATA PROTECTION: Hardware features
protect against inadvertent programs to the AT49F512 in
the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit:
holding any one of OE low, CE high or WE high inhibits
program cycles. (c) Noise filter: Pulses of less than 15 ns
(typical) on the WE or CE inputs will not initiate a program
cycle.
Command Definition (in Hex)
Command
Sequence
Bus
Cycles
1st Bus
Cycle
Addr
Data
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
6th Bus
Cycle
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
2AAA
55
5555
10
2AAA
55
5555
40
Read
1
Addr
DOUT
Chip Erase
6
5555
AA
2AAA
55
5555
80
5555
AA
Byte Program
4
5555
AA
2AAA
55
5555
A0
Addr
DIN
Boot Block
Lockout(1)
6
5555
AA
2AAA
55
5555
80
5555
AA
Product ID
Entry
3
5555
AA
2AAA
55
5555
90
Product ID
Exit(2)
3
5555
AA
2AAA
55
5555
F0
Product ID
Exit(2)
1
XXXX
F0
Notes:
5th Bus
Cycle
1. The 8K byte boot sector has the address range 0000H to 1FFFH.
2. Either one of the Product ID exit commands can be used.
Absolute Maximum Ratings*
Temperature Under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages
(including NC pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Voltage on OE
with Respect to Ground ...................................-0.6V to +13.5V
3
DC and AC Operating Range
Com.
Operating
Temperature (Case)
Ind.
VCC Power Supply
AT49F512-70
AT49F512-90
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-40°C - 85°C
5V ± 10%
5V ± 10%
Operating Modes
Mode
CE
OE
WE
Ai
I/O
Read
VIL
VIL
VIH
Ai
DOUT
Program(2)
VIL
VIH
VIL
Ai
DIN
X
High Z
Standby/Write Inhibit
(1)
VIH
X
X
Program Inhibit
X
X
VIH
Program Inhibit
X
VIL
X
Output Disable
X
VIH
X
VIL
VIL
VIH
High Z
Product Identification
Hardware
A1 - A15 = VIL, A9 = VH, A0 = VIL(3)
Manufacturer Code(4)
A1 - A15 = VIL, A9 = VH, A0 = VIH(3)
Device Code(4)
Software(5)
Notes:
A0 = VIL, A1 - A15 = VIL
Manufacturer Code(4)
A0 = VIH, A1 - A15 = VIL
Device Code(4)
1. X can be VIL or VIH.
2. Refer to AC Programming Waveforms.
3. VH = 12.0V ± 0.5V.
4. Manufacturer Code: 1FH, Device Code: 03H
5. See details under Software Product Identification Entry/Exit.
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
10
µA
Output Leakage Current
VI/O = 0V to VCC
10
µA
Com.
100
ISB1
VCC Standby Current CMOS
CE = VCC - 0.3V to VCC
µA
Ind.
300
µA
ISB2
VCC Standby Current TTL
CE = 2.0V to VCC
3
mA
ICC(1)
Com.
30
mA
VCC Active Current
f = 5 MHz; IOUT = 0 mA
Ind.
40
mA
VIL
Input Low Voltage
0.8
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH1
Output High Voltage
IOH = -400 µA
2.4
V
VOH2
Output High Voltage CMOS
IOH = -100 µA; VCC = 4.5V
4.2
V
Note:
4
1. In the erase mode, ICC is 90 mA.
AT49F512
Min
2.0
V
0.45
V
AT49F512
AC Read Characteristics
AT49F512-70
Symbol
Parameter
tACC
tCE
Min
AT49F512-90
Max
Min
Max
Units
Address to Output Delay
70
90
ns
(1)
CE to Output Delay
70
90
ns
(2)
OE to Output Delay
35
0
40
ns
25
0
25
ns
tOE
tDF(3)(4)
CE or OE to Output Float
0
tOH
Output Hold from OE, CE or
Address, whichever occurred first
0
0
ns
AC Read Waveforms(1)(2)(3)(4)
Notes:
1.
CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2.
OE may be delayed up to tCE - tOE, after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3.
tDF is specified from OE or CE whichever occurs first (CL = 5 pF).
4.
This parameter is characterized and is not 100% tested.
Input Test Waveforms and
Measurement Level
Output Test Load
tR, tF < 5 ns
Pin Capacitance
f = 1 MHz, T= 25°C(1)
Typ
Max
Units
CIN
4
6
pF
VIN = 0V
COUT
8
12
pF
VOUT = 0V
Note:
Conditions
1. This parameter is characterized and is not 100% tested.
5
AC Word Load Characteristics
Symbol
Parameter
tAS, tOES
Address, OE Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tCS
Chip Select Set-up Time
0
ns
tCH
Chip Select Hold Time
0
ns
tWP
Write Pulse Width (WE or CE)
90
ns
tDS
Data Set-up Time
50
ns
tDH, tOEH
Data, OE Hold Time
0
ns
tWPH
Write Pulse Width High
90
ns
AC Byte Load Waveforms
WE Controlled
CE Controlled
6
AT49F512
Min
Max
Units
AT49F512
Program Cycle Characteristics
Symbol
Parameter
Min
Typ
Max
Units
tBP
Byte Programming Time
10
50
µs
tAS
Address Set-up Time
0
ns
tAH
Address Hold Time
50
ns
tDS
Data Set-up Time
50
ns
tDH
Data Hold Time
0
ns
tWP
Write Pulse Width
90
ns
tWPH
Write Pulse Width High
90
ns
tEC
Erase Cycle Time
10
seconds
Program Cycle Waveforms
PROGRAM CYCLE
OE
CE
t
t
WP
t
WPH
BP
WE
t
A0-A15
t
AH
AS
t
5555
5555
2AAA
t
DATA
DH
ADDRESS
DS
55
AA
INPUT
DATA
A0
Chip Erase Cycle Waveforms
OE
CE
t
t
WP
WPH
WE
t
A0-A15
AS
t
t
AH
5555
Note:
5555
5555
2AAA
t
DATA
DH
5555
2AAA
t
DS
AA
55
80
AA
55
10
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
EC
OE must be high only when WE and CE are both low.
7
Data Polling Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
tOEH
OE Hold Time
Min
Max
OE to Output Delay
tWR
Write Recovery Time
Units
10
ns
10
ns
(2)
tOE
Notes:
Typ
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Data Polling Waveforms
WE
CE
tOEH
OE
tDH
tOE
A0-A15
tWR
HIGH Z
I/O7
An
An
An
An
An
Toggle Bit Characteristics(1)
Symbol
Parameter
tDH
Data Hold Time
10
ns
tOEH
OE Hold Time
10
ns
tOE
OE to Output Delay(2)
tOEHP
OE High Pulse
tWR
Write Recovery Time
Notes:
Min
Typ
Max
Units
ns
150
ns
0
ns
1. These parameters are characterized and not 100% tested.
2. See tOE spec in AC Read Characteristics.
Toggle Bit Waveforms(1)(2)(3)
Notes:
8
1.
Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling
input(s)
2.
Begining and ending state of I/O6 will vary.
3.
Any address location may be used but the address should not vary.
AT49F512
AT49F512
Software Product
Identification Entry(1)
Boot Block
Lockout Enable Algorithm(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 90
TO
ADDRESS 5555
LOAD DATA 80
TO
ADDRESS 5555
ENTER PRODUCT
IDENTIFICATION
MODE(2)(3)(5)
LOAD DATA AA
TO
ADDRESS 5555
Software Product
Identifcation Exit(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
OR
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA F0
TO
ANY ADDRESS
LOAD DATA 40
TO
ADDRESS 5555
EXIT PRODUCT
IDENTIFICATION
MODE(4)
PAUSE 1 second(2)
LOAD DATA F0
TO
ADDRESS 5555
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. Boot block lockout feature enabled.
EXIT PRODUCT
IDENTIFICATION
MODE(4)
Notes:
1. Data Format: I/O7 - I/O0 (Hex);
Address Format: A14 - A0 (Hex).
2. A1 - A15 = VIL.
Manufacture Code is read for A0 = VIL;
Device Code is read for A0 = VIH.
3. The device does not remain in identification mode if powered down.
4. The device returns to standard operation mode.
5. Manufacturer Code: 1FH
Device Code: 03H
9
Ordering Information(1)
tACC
(ns)
70
90
Note:
Active
30
ICC (mA)
Standby
0.1
Ordering Code
Package
AT49F512-70JC
AT49F512-70PC
AT49F512-70TC
AT49F512-70VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
40
0.3
AT49F512-70JI
AT49F512-70PI
AT49F512-70TI
AT49F512-70VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
30
0.1
AT49F512-90JC
AT49F512-90PC
AT49F512-90TC
AT49F512-90VC
32J
32P6
32T
32V
Commercial
(0° to 70°C)
40
0.3
AT49F512-90JI
AT49F512-90PI
AT49F512-90TI
AT49F512-90VI
32J
32P6
32T
32V
Industrial
(-40° to 85°C)
1. The AT49F512 has as optional boot block feature. The part number shown in the Ordering Information table is for devices
with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher
address range should contact Atmel.
Package Type
32J
32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC)
32P6
32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
32T
32-Lead, Thin Small Outline Package (TSOP) (8 x 20 mm)
32V
32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm)
10
Operation Range
AT49F512
AT49F512
Packaging Information
32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-016 AE
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.050(1.27) TYP
1.67(42.4)
1.64(41.7)
.025(.635) X 30° - 45°
.012(.305)
.008(.203)
.553(14.0)
.547(13.9)
.595(15.1)
.585(14.9)
.032(.813)
.026(.660)
32P6, 32-Lead, 0.600” Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
.300(7.62) REF
.430(10.9)
.390(9.90)
AT CONTACT
POINTS
.530(13.5)
.490(12.4)
.566(14.4)
.530(13.5)
.021(.533)
.013(.330)
.030(.762)
.015(3.81)
.095(2.41)
.060(1.52)
.140(3.56)
.120(3.05)
.022(.559) X 45° MAX (3X)
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
0 REF
15
.012(.305)
.008(.203)
32T, 32-Lead, Plastic Thin Small Outline Package
(TSOP)
Dimensions in Millimeters and (Inches)
.090(2.29)
MAX
1.500(38.10) REF
.453(11.5)
.447(11.4)
.495(12.6)
.485(12.3)
.690(17.5)
.610(15.5)
32V, 32-Lead, Plastic Thin Small Outline Package
(VSOP)
Dimensions in Millimeters (Inches)
INDEX
MARK
INDEX
MARK
18.5(.728)
18.3(.720)
0.50(.020)
BSC
PIN
1
7.50(.295)
REF
12.5(.492)
12.3(.484)
20.2(.795)
19.8(.780)
0.50(.020)
BSC
0.25(.010)
0.15(.006)
8.20(.323)
7.80(.307)
7.50(.295)
REF
0.25(.010)
0.15(.006)
8.10(.319)
7.90(.311)
1.20(.047) MAX
14.2(.559)
13.8(.543)
1.20(.047) MAX
0.15(.006)
0.05(.002)
0.15(.006)
0.05(.002)
0
5 REF
0.20(.008)
0.10(.004)
0.70(.028)
0.50(.020)
0
5 REF
0.20(.008)
0.10(.004)
0.70(.028)
0.50(.020)
11
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