PD - 95270 IRL7833PbF IRL7833SPbF IRL7833LPbF Applications l High Frequency Synchronous Buck Converters for Computer Processor Power l High Frequency Isolated DC-DC Converters with Synchronous Rectification for Telecom and Consumer Use l Lead-Free HEXFET® Power MOSFET VDSS RDS(on) max 3.8m: 30V Qg 32nC Benefits l l l Very Low RDS(on) at 4.5V VGS Ultra-Low Gate Impedance Fully Characterized Avalanche Voltage and Current D2Pak IRL7833S TO-220AB IRL7833 TO-262 IRL7833L Absolute Maximum Ratings Parameter Max. Units 30 V VDS Drain-to-Source Voltage VGS Gate-to-Source Voltage Continuous Drain Current, VGS @ 10V ± 20 150 IDM Continuous Drain Current, VGS @ 10V Pulsed Drain Current 600 PD @TC = 25°C Maximum Power Dissipation PD @TC = 100°C Maximum Power Dissipation TJ Linear Derating Factor Operating Junction and TSTG Storage Temperature Range ID @ TC = 25°C ID @ TC = 100°C c f 110f g g A 140 W 72 0.96 -55 to + 175 y Mounting Torque, 6-32 or M3 screw W/°C °C y 10 lbf in (1.1N m) Thermal Resistance Parameter RθJC RθCS Junction-to-Case Case-to-Sink, Flat, Greased Surface RθJA Junction-to-Ambient h RθJA Junction-to-Ambient (PCB Mount) h g Typ. Max. ––– 1.04 0.50 ––– ––– 62 ––– 40 Units °C/W Notes through are on page 12 www.irf.com 1 05/18/04 IRL7833/S/LPbF Static @ TJ = 25°C (unless otherwise specified) Parameter Min. Typ. Max. Units BVDSS Drain-to-Source Breakdown Voltage ∆ΒVDSS/∆TJ Breakdown Voltage Temp. Coefficient RDS(on) Static Drain-to-Source On-Resistance 30 V ––– ––– 18 ––– ––– 3.1 3.8 mV/°C Reference to 25°C, ID = 1mA mΩ VGS = 10V, ID = 38A ––– 3.7 4.5 VGS = 4.5V, ID = 30A VGS(th) Gate Threshold Voltage 1.4 ––– 2.3 V ∆VGS(th)/∆TJ Gate Threshold Voltage Coefficient ––– -11 ––– mV/°C IDSS Drain-to-Source Leakage Current ––– ––– 1.0 µA ––– ––– 150 Gate-to-Source Forward Leakage ––– ––– 100 Gate-to-Source Reverse Leakage ––– ––– -100 Forward Transconductance 150 ––– ––– IGSS gfs Qg Conditions ––– VGS = 0V, ID = 250µA f f VDS = VGS, ID = 250µA VDS = 24V, VGS = 0V VDS = 24V, VGS = 0V, TJ = 125°C nA VGS = 20V VGS = -20V S VDS = 15V, ID = 30A Total Gate Charge ––– 32 47 Qgs1 Pre-Vth Gate-to-Source Charge ––– 8.7 ––– Qgs2 Post-Vth Gate-to-Source Charge ––– 5.1 ––– Qgd Gate-to-Drain Charge ––– 13 ––– ID = 30A Qgodr Gate Charge Overdrive Switch Charge (Qgs2 + Qgd) ––– 5.3 ––– See Fig. 16 Qsw ––– 18 ––– Qoss Output Charge ––– 22 ––– td(on) Turn-On Delay Time ––– 18 ––– tr Rise Time ––– 50 ––– td(off) Turn-Off Delay Time ––– 21 ––– tf Fall Time ––– 6.9 ––– Ciss Input Capacitance ––– 4170 ––– Coss Output Capacitance ––– 950 ––– Crss Reverse Transfer Capacitance ––– 470 ––– VDS = 16V nC nC VGS = 4.5V VDS = 16V, VGS = 0V VDD = 15V, VGS = 4.5V ns f ID = 26A Clamped Inductive Load VGS = 0V pF VDS = 15V ƒ = 1.0MHz Avalanche Characteristics EAS Parameter Single Pulse Avalanche Energy IAR Avalanche Current EAR Repetitive Avalanche Energy c dh c Typ. Max. Units ––– 560 mJ ––– 30 A ––– 14 mJ Diode Characteristics Parameter Min. Typ. Max. Units IS Continuous Source Current ––– ––– ISM (Body Diode) Pulsed Source Current ––– ––– VSD (Body Diode) Diode Forward Voltage ––– trr Reverse Recovery Time ––– Qrr Reverse Recovery Charge ––– 2 ch 150 f Conditions MOSFET symbol A D 600 showing the integral reverse ––– 1.2 V p-n junction diode. TJ = 25°C, IS = 30A, VGS = 0V 42 63 ns 34 51 nC G S f TJ = 25°C, IF = 30A, VDD = 15V di/dt = 100A/µs f www.irf.com IRL7833/S/LPbF 1000 1000 100 BOTTOM 10 VGS 10V 7.0V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V 2.7V TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 100 BOTTOM 2.7V 10 20µs PULSE WIDTH Tj = 175°C 20µs PULSE WIDTH Tj = 25°C 1 1 0.1 1 10 100 1000 0.1 VDS, Drain-to-Source Voltage (V) 1 10 100 1000 VDS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 2.0 RDS(on) , Drain-to-Source On Resistance (Normalized) 1000 ID, Drain-to-Source Current (Α) VGS 10V 7.0V 4.5V 3.7V 3.5V 3.3V 3.0V 2.7V T J = 175°C 100 TJ = 25°C VDS = 15V 20µs PULSE WIDTH ID = 75A VGS = 10V 1.5 1.0 0.5 10 2.0 3.0 4.0 5.0 6.0 7.0 VGS, Gate-to-Source Voltage (V) Fig 3. Typical Transfer Characteristics www.irf.com 8.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 T J , Junction Temperature (°C) Fig 4. Normalized On-Resistance Vs. Temperature 3 IRL7833/S/LPbF 100000 12.0 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd VGS, Gate-to-Source Voltage (V) ID= 30A C, Capacitance(pF) Coss = Cds + Cgd 10000 Ciss Coss 1000 Crss 10.0 VDS= 24V VDS= 15V 8.0 6.0 4.0 2.0 0.0 100 1 10 100 0 VDS, Drain-to-Source Voltage (V) 15 20 25 30 35 40 Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage 1000.00 1000 T J = 175°C ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 10 QG Total Gate Charge (nC) Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage 100.00 OPERATION IN THIS AREA LIMITED BY R DS(on) 100 10.00 T J = 25°C 1.00 100µsec 10 1msec 1 10msec Tc = 25°C Tj = 175°C Single Pulse VGS = 0V 0.10 0.1 0.0 0.5 1.0 1.5 2.0 2.5 VSD, Source-to-Drain Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 4 5 3.0 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 8. Maximum Safe Operating Area www.irf.com IRL7833/S/LPbF 2.5 160 VGS(th) Gate threshold Voltage (V) LIMITED BY PACKAGE ID , Drain Current (A) 120 80 40 2.0 1.5 ID = 250µA 1.0 0.5 0.0 0 25 50 75 100 125 150 175 TC, Case Temperature (°C) -75 -50 -25 0 25 50 75 100 125 150 175 T J , Temperature ( °C ) Fig 9. Maximum Drain Current Vs. Case Temperature Fig 10. Threshold Voltage Vs. Temperature (Z thJC) 10 1 Thermal Response D = 0.50 0.20 P DM 0.10 0.1 t1 0.05 0.02 0.01 t2 SINGLE PULSE (THERMAL RESPONSE) Notes: 1. Duty factor D = 2. Peak T 0.01 0.00001 0.0001 0.001 0.01 t1 / t 2 J = P DM x Z thJC +TC 0.1 1 t 1, Rectangular Pulse Duration (sec) Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case www.irf.com 5 IRL7833/S/LPbF 15V 2000 ID TOP DRIVER D.U.T RG + V - DD IAS 20V VGS 1600 A 0.01Ω tp Fig 12a. Unclamped Inductive Test Circuit V(BR)DSS tp EAS , Single Pulse Avalanche Energy (mJ) L VDS 12A 21A 30A BOTTOM 1200 800 400 0 25 50 75 100 125 150 175 Fig 12c. Maximum Avalanche Energy Vs. Drain Current LD I AS VDS Fig 12b. Unclamped Inductive Waveforms + VDD D.U.T Current Regulator Same Type as D.U.T. VGS Pulse Width < 1µs Duty Factor < 0.1% 50KΩ 12V .2µF .3µF Fig 14a. Switching Time Test Circuit D.U.T. + V - DS VDS 90% VGS 3mA 10% IG ID Current Sampling Resistors Fig 13. Gate Charge Test Circuit VGS td(on) tr td(off) tf Fig 14b. Switching Time Waveforms 6 www.irf.com IRL7833/S/LPbF D.U.T Driver Gate Drive + - - * D.U.T. ISD Waveform Reverse Recovery Current + RG • • • • dv/dt controlled by R G Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test V DD P.W. Period VGS=10V Circuit Layout Considerations • Low Stray Inductance • Ground Plane • Low Leakage Inductance Current Transformer D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Curent ISD Ripple ≤ 5% * VGS = 5V for Logic Level Devices Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET® Power MOSFETs Id Vds Vgs Vgs(th) Qgs1 Qgs2 Qgd Qgodr Fig 16. Gate Charge Waveform www.irf.com 7 IRL7833/S/LPbF Power MOSFET Selection for Non-Isolated DC/DC Converters Control FET Synchronous FET Special attention has been given to the power losses in the switching elements of the circuit - Q1 and Q2. Power losses in the high side switch Q1, also called the Control FET, are impacted by the Rds(on) of the MOSFET, but these conduction losses are only about one half of the total losses. The power loss equation for Q2 is approximated by; * Ploss = Pconduction + Pdrive + Poutput ( 2 Ploss = Irms × Rds(on) ) Power losses in the control switch Q1 are given by; + (Qg × Vg × f ) Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput ⎛Q ⎞ + ⎜ oss × Vin × f + (Qrr × Vin × f ) ⎝ 2 ⎠ This can be expanded and approximated by; *dissipated primarily in Q1. Ploss = (Irms 2 × Rds(on ) ) ⎛ Qgd +⎜I × × Vin × ig ⎝ ⎞ ⎞ ⎛ Qgs 2 f⎟ + ⎜ I × × Vin × f ⎟ ig ⎠ ⎝ ⎠ + (Qg × Vg × f ) + ⎛ Qoss × Vin × f ⎞ ⎝ 2 ⎠ This simplified loss equation includes the terms Qgs2 and Qoss which are new to Power MOSFET data sheets. Qgs2 is a sub element of traditional gate-source charge that is included in all MOSFET data sheets. The importance of splitting this gate-source charge into two sub elements, Qgs1 and Qgs2, can be seen from Fig 16. Qgs2 indicates the charge that must be supplied by the gate driver between the time that the threshold voltage has been reached and the time the drain current rises to Idmax at which time the drain voltage begins to change. Minimizing Q gs2 is a critical factor in reducing switching losses in Q1. Qoss is the charge that must be supplied to the output capacitance of the MOSFET during every switching cycle. Figure A shows how Qoss is formed by the parallel combination of the voltage dependant (nonlinear) capacitances Cds and Cdg when multiplied by the power supply input buss voltage. For the synchronous MOSFET Q2, Rds(on) is an important characteristic; however, once again the importance of gate charge must not be overlooked since it impacts three critical areas. Under light load the MOSFET must still be turned on and off by the control IC so the gate drive losses become much more significant. Secondly, the output charge Qoss and reverse recovery charge Qrr both generate losses that are transfered to Q1 and increase the dissipation in that device. Thirdly, gate charge will impact the MOSFETs’ susceptibility to Cdv/dt turn on. The drain of Q2 is connected to the switching node of the converter and therefore sees transitions between ground and Vin. As Q1 turns on and off there is a rate of change of drain voltage dV/dt which is capacitively coupled to the gate of Q2 and can induce a voltage spike on the gate that is sufficient to turn the MOSFET on, resulting in shoot-through current . The ratio of Qgd/Qgs1 must be minimized to reduce the potential for Cdv/dt turn on. Figure A: Qoss Characteristic 8 www.irf.com IRL7833/S/LPbF TO-220AB Package Outline Dimensions are shown in millimeters (inches) 2.87 (.113) 2.62 (.103) 10.54 (.415) 10.29 (.405) -B- 3.78 (.149) 3.54 (.139) 4.69 (.185) 4.20 (.165) -A- 1.32 (.052) 1.22 (.048) 6.47 (.255) 6.10 (.240) 4 15.24 (.600) 14.84 (.584) 1.15 (.045) MIN 1 2 LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE 4 - DRAIN 3 14.09 (.555) 13.47 (.530) 4.06 (.160) 3.55 (.140) 3X 1.40 (.055) 3X 1.15 (.045) 0.93 (.037) 0.69 (.027) 0.36 (.014) 3X M B A M 0.55 (.022) 0.46 (.018) 2.92 (.115) 2.64 (.104) 2.54 (.100) 2X NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982. 2 CONTROLLING DIMENSION : INCH 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB. 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS. TO-220AB Part Marking Information E XAMPL E : T H IS IS AN IR F 1010 L OT CODE 1789 AS S E MB L E D ON WW 19, 1997 IN T HE AS S E MB L Y L INE "C" Note: "P" in assembly line position indicates "Lead-Free" INT E R NAT IONAL RE CT IF IE R L OGO AS S E MB L Y L OT CODE www.irf.com P AR T NU MB E R DAT E CODE YE AR 7 = 1997 WE E K 19 L INE C 9 IRL7833/S/LPbF D2Pak Package Outline D2Pak Part Marking Information THIS IS AN IRF530S WITH LOT CODE 8024 AS S EMBLED ON WW 02, 2000 IN THE AS SEMBLY LINE "L" INTERNATIONAL RECT IFIER LOGO Note: "P" in assembly line position indicates "Lead-Free" PART NUMBER F530S AS S EMBLY LOT CODE DAT E CODE YEAR 0 = 2000 WEEK 02 LINE L OR INT ERNAT IONAL RECTIF IER LOGO ASSE MBLY LOT CODE 10 PART NUMBER F 530S DAT E CODE P = DESIGNAT E S LEAD-F REE PRODUCT (OPTIONAL) YE AR 0 = 2000 WE EK 02 A = ASSE MBLY SIT E CODE www.irf.com IRL7833/S/LPbF TO-262 Package Outline TO-262 Part Marking Information EXAMPLE: THIS IS AN IRL3103L LOT CODE 1789 AS S EMBLED ON WW 19, 1997 IN T HE AS S EMBLY LINE "C" Note: "P" in assembly line position indicates "Lead-Free" INT ERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE PART NUMBER DATE CODE YEAR 7 = 1997 WEEK 19 LINE C OR INT ERNATIONAL RECTIFIER LOGO AS S EMBLY LOT CODE www.irf.com PART NUMBER DATE CODE P = DES IGNATES LEAD-FREE PRODUCT (OPTIONAL) YEAR 7 = 1997 WEEK 19 A = AS S EMBLY SITE CODE 11 IRL7833/S/LPbF D2Pak Tape & Reel Information Dimensions are shown in millimeters (inches) TRR 1.60 (.063) 1.50 (.059) 4.10 (.161) 3.90 (.153) FEED DIRECTION 1.85 (.073) 1.65 (.065) 1.60 (.063) 1.50 (.059) 11.60 (.457) 11.40 (.449) 0.368 (.0145) 0.342 (.0135) 15.42 (.609) 15.22 (.601) 24.30 (.957) 23.90 (.941) TRL 10.90 (.429) 10.70 (.421) 1.75 (.069) 1.25 (.049) 4.72 (.136) 4.52 (.178) 16.10 (.634) 15.90 (.626) FEED DIRECTION 13.50 (.532) 12.80 (.504) 27.40 (1.079) 23.90 (.941) 4 330.00 (14.173) MAX. NOTES : 1. COMFORMS TO EIA-418. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION MEASURED @ HUB. 4. INCLUDES FLANGE DISTORTION @ OUTER EDGE. 60.00 (2.362) MIN. 26.40 (1.039) 24.40 (.961) 3 30.40 (1.197) MAX. 4 Notes: Repetitive rating; pulse width limited by max. junction temperature. Starting TJ = 25°C, L = 1.3mH, RG = 25Ω, IAS = 30A. Pulse width ≤ 400µs; duty cycle ≤ 2%. Calculated continuous current based on maximum allowable junction temperature. Package limitation current is 75A. When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. This is only applied to TO-220AB package. TO-220AB package isnot recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site. IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.05/04 12 www.irf.com Note: For the most current drawings please refer to the IR website at: http://www.irf.com/package/