DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 DS90C241 and DS90C124 5-MHz to 35-MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Check for Samples: DS90C124, DS90C241 FEATURES DESCRIPTION • The DS90C241 and DS90C124 chipset translates a 24-bit parallel bus into a fully transparent data and control LVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 24-bit bus over PCB traces or over cable by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths, which in turn reduces PCB layers, cable width, and connector size and pins. 1 2 • • • • • • • • • • • • • • • • 5-MHz to 35-MHz clock embedded and DCBalancing 24:1 and 1:24 data transmissions User defined pre-emphasis driving ability through external resistor on LVDS outputs and capable to drive up to 10-meter shielded twisted-pair cable User-selectable clock edge for parallel data on both transmitter and receiver Internal DC balancing encode and decode – Supports AC-coupling interface with no external coding required Individual power-down controls for both transmitter and receiver Embedded clock CDR (clock and data recovery) on receiver and no external source of reference clock needed All codes RDL (random data lock) to support live-pluggable applications LOCK output flag to ensure data integrity at receiver side Balanced TSETUP and THOLD between RCLK and RDATA on receiver side PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects All LVCMOS inputs and control pins have internal pulldown On-chip filters for PLLs on transmitter and receiver Temperature range –40°C to +105°C Greater than 8-kV HBM ESD tolerant Meets AEC-Q100 compliance Power supply range 3.3V ± 10% 48-pin TQFP package The DS90C241 and DS90C124 incorporate LVDS signaling on the high-speed I/O. LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the serializer output edge rate for the operating frequency range, EMI is further reduced. In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding and decoding supports AC-coupled interconnects. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Block Diagram PRE DEN VODSEL PLL RRFB RPWDNB Timing and Control LOCK RCLK bit23 CLK0 bit22 bit21 bit20 bit18 bit19 bit17 bit16 bit14 bit12 bit13 DCB bit11 DCA bit9 bit10 DESERIALIZER ± DS90C124 bit8 bit7 bit6 bit5 bit4 bit3 bit1 bit2 bit0 SERIALIZER ± DS90C241 CLK1 ROUT Clock Recovery bit15 TPWDNB 24 Timing and Control PLL TCLK Output Latch RIN- DOUT- DC Balance Decode Serial to Parallel RIN+ RT = 100: RT = 100: TRFB DOUT+ Parallel to Serial 24 DC Balance Encode DIN Input Latch REN These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4V Supply Voltage (VCC) LVCMOS/LVTTL Input Voltage −0.3V to (VCC +0.3V) LVCMOS/LVTTL Output Voltage −0.3V to (VCC +0.3V) LVDS Receiver Input Voltage −0.3V to 3.9V LVDS Driver Output Voltage −0.3V to 3.9V LVDS Output Short Circuit Duration 10 ms Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Soldering, 4 seconds) +260°C Maximum Package Power Dissipation Capacity Package Derating: 48L TQFP 1/θJA °C/W above +25°C DS90C241 θJA 45.8°C/W (4L JEDEC); 75.4°C/W (2L JEDEC) θJC 21.0°C/W DS90C124 θJA 45.4°C/W (4L JEDEC); 75.0°C/W (2L JEDEC) θJC 21.1°C/W ≥±8 kV ESD Rating (HBM) ESD Rating (ISO10605) RD = 2 kΩ, CS = 330 pF DS90C241 meets ISO 10605 Contact Discharge (DOUT+, DOUT-) ±8 kV Air Discharge (DOUT+, DOUT-) (1) 2 ±25 kV “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Recommended Operating Conditions Min Nom Max Supply Voltage (VCC) 3.0 3.3 3.6 V Operating Free Air −40 +25 +105 °C 35 MHz ±100 mVP-P Temperature (TA) Clock Rate 5 Supply Noise Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Units Submit Documentation Feedback 3 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 2.0 VCC V GND 0.8 V −0.8 −1.5 V LVCMOS/LVTTL DC SPECIFICATIONS VIH High Level Voltage VIL Low Level Input Voltage VCL Input Clamp Voltage IIN Input Current ICL = −18 mA (1) VIN = 0V or 3.6V VOH High Level Output Voltage IOH = −4 mA VOL Low Level Output Voltage IOL = +4 mA (1) Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB, DCAOFF, DCBOFF, VODSEL Rx: RPWDNB, RRFB, REN Tx: DIN[23:0], TCLK, TPWDNB, DEN, TRFB, DCAOFF, DCBOFF, VODSEL −10 ±5 +10 µA Rx: RPWDNB, RRFB, REN −20 ±5 +20 µA Rx: ROUT[23:0], RCLK, LOCK IOS Output Short Circuit Current VOUT = 0V IOZ TRI-STATE Output Current RPWDNB, REN = 0V, VOUT = 0V or 2.4V Rx: ROUT[23:0], RCLK, LOCK VCM = +1.2V Rx: RIN+, RIN− 2.3 3.0 VCC V GND 0.33 0.5 V −40 −70 −110 mA −30 ±0.4 +30 µA +50 mV LVDS DC SPECIFICATIONS VTH Differential Threshold High Voltage VTL Differential Threshold Low Voltage IIN Input Current VOD Output Differential Voltage (DOUT+)–(DOUT−) −50 mV VIN = +2.4V, VCC = 3.6V or 0V VIN = 0V, VCC = 3.6V RL = 100Ω, without Pre-emphasis VODSEL = L (Figure 10) Tx: DOUT+, DOUT− RL = 100Ω, without Pre-emphasis VODSEL = H (Figure 10) ±200 µA ±200 µA 250 400 600 mV 450 750 1200 mV 10 50 mV 1.25 1.50 V 1 50 mV ΔVOD Output Differential Voltage Unbalance RL = 100Ω, without Pre-emphasis VOS Offset Voltage RL = 100Ω, without Pre-emphasis ΔVOS Offset Voltage Unbalance RL = 100Ω, without Pre-emphasis IOS Output Short Circuit Current DOUT = 0V, DIN = H, TPWDNB, DEN = 2.4V, VODSEL = L −2 −8 mA DOUT = 0V, DIN = H, TPWDNB, DEN = 2.4V, VODSEL = H −7 −13 mA TPWDNB, DEN = 0V, DOUT = 0V or 2.4V −15 +15 µA IOZ (1) 4 TRI-STATE Output Current 1.00 ±1 Specification is ensured by characterization and is not tested in production. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Pin/Freq. Min Typ Max Units 40 65 mA 45 70 mA 40 65 mA 45 70 mA 800 µA 85 mA 80 mA 50 µA SER/DES SUPPLY CURRENT (DVDD*, PVDD* and AVDD* pins) *Digital, PLL, and Analog VDDs ICCT Serializer (Tx) Total Supply Current (includes load current) RL = 100Ω RPRE = OFF VODSEL = H/L Checker-board pattern (Figure 1) f = 35 MHz RL = 100Ω RPRE = 6 kΩ VODSEL = H/L Checker-board pattern (Figure 1) f = 35 MHz Serializer (Tx) Total Supply RL = 100Ω Current(includes load current) RPRE = OFF VODSEL = H/L RL = 100Ω RPRE = 6 kΩ VODSEL = H/L Random pattern f = 35 MHz f = 35 MHz ICCTZ Serializer (Tx)Supply Current Power-down ICCR Deserializer (Rx) Total Supply CL = 8 pF LVCMOS Output Current (includes load Checker-board pattern current) (Figure 2) f = 35 MHz Deserializer (Rx) Total Supply CL = 8 pF LVCMOS Output Current (includes load Random pattern current) f = 35 MHz ICCRZ Deserializer (Rx) Supply Current Power-down TPWDNB = 0V (All other LVCMOS Inputs = 0V) RPWDNB = 0V (All other LVCMOS Inputs = 0V, RIN+/ RIN-= 0V) Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 5 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Serializer Timing Requirements for TCLK Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Max Units tTCP Transmit Clock Period 28.6 T 200 ns tTCIH Transmit Clock High Time 0.4T 0.5T 0.6T ns tTCIL Transmit Clock Low Time 0.4T 0.5T 0.6T ns tCLKT TCLK Input Transition Time 3 6 ns 33 ps (RMS) Max Units 0.6 ns 0.6 ns tJIT (1) (Figure 5) Typ (Figure 4) (1) TCLK Input Jitter tJIT (at BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter. Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions Min Typ tLLHT LVDS Low-to-High Transition Time tLHLT LVDS High-to-Low Transition Time tDIS DIN (23:0) Setup to TCLK tDIH DIN (23:0) Hold from TCLK tHZD DOUT ± HIGH to TRI-STATE Delay tLZD DOUT ± LOW to TRI-STATE Delay tZHD DOUT ± TRI-STATE to HIGH Delay tZLD DOUT ± TRI-STATE to LOW Delay 200 ns tPLD Serializer PLL Lock Time RL = 100Ω, (Figure 7) 10 ms tSD Serializer Delay RL = 100Ω, (Figure 8) VODSEL = L, TRFB = H 3.5T + 2.85 3.5T + 10 ns RL = 100Ω, (Figure 8) VODSEL = L, TRFB = L 3.5T + 2.85 3.5T + 10 ns TxOUT_ E_O (1) (2) (3) (4) (5) 6 TxOUT_Eye_Opening (respect to ideal) RL = 100Ω, (Figure 3) CL = 10 pF to GND VODSEL = L RL = 100Ω, CL = 10 pF to GND 5 ns 5 (1) ns RL = 100Ω, CL = 10 pF to GND (Figure 6) (2) 5–35 MHz (Figure 9) (1) 15 ns 15 ns 200 ns 0.75 (3) (4) UI (5) Specification is ensured by characterization and is not tested in production. When the Serializer output is tri-stated, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer. tJIT (at BER of 10e-9) specifies the allowable jitter on TCLK. tJIT not included in TxOUT_E_O parameter. TxOUT_E_O is affected by pre-emphasis value. UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Deserializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter Conditions tRCP Receiver out Clock Period tRDC RCLK Duty Cycle tCLH LVCMOS Low-to-High Transition Time tCHL LVCMOS High-to-Low Transition Time tROS ROUT (7:0) Setup Data to RCLK (Group 1) tROH CL = 8 pF (lumped load) (Figure 11) (1) Pin/Freq. ROUT (15:8) Setup Data to RCLK (Group 2) tROH ROUT (15:8) Hold Data to RCLK (Group 2) tROS ROUT (23:16) Setup Data to RCLK (Group 3) 28.6 RCLK 45 HIGH to TRI-STATE Delay tLZR LOW to TRI-STATE Delay tZHR Typ ROUT [23:0], LOCK, RCLK (Figure 15) ROUT [7:0] (Figure 15) ROUT [15:8], LOCK (Figure 15) ROUT [23:16] ROUT (23:16) Hold Data to RCLK (Group 3) tHZR Min RCLK ROUT (7:0) Hold Data to RCLK (Group 1) tROS tROH tRCP = tTCP (1) (Figure 13) Max Units 200 ns 50 55 % 2.5 3.5 ns 2.5 3.5 ns (0.40)* tRCP (29/56)*tR (0.40)* tRCP (27/56)*tR ns CP ns CP (0.40)* tRCP 0.5*tRCP ns (0.40)* tRCP 0.5*tRCP ns (0.40)* tRCP (27/56)*tR ns (0.40)* tRCP (29/56)*tR ROUT [23:0], RCLK, LOCK CP ns CP 3 10 ns 3 10 ns TRI-STATE to HIGH Delay 3 10 ns tZLR TRI-STATE to LOW Delay 3 10 ns tDD Deserializer Delay (Figure 12) RCLK [4+(3/56)] T +5.9 [4+(3/56)] T +14 ns tDRDL Deserializer PLL Lock Time from Powerdown (Figure 14) 5 MHz 5 50 ms 35 MHz 5 50 ms 0.25 UI 0.25 UI (2) (1) RxIN_TOL Receiver INput TOLerance Left, _L (Figure 16) (3) (1) (4) RxIN_TOL Receiver INput TOLerance Right, _R (Figure 16) (3) (1) (4) (1) (2) (3) (4) 5 MHz–35 MHz 5 MHz–35 MHz Specification is ensured by characterization and is not tested in production. The Deserializer PLL lock time (tDRDL) may vary depending on input data patterns and the number of transitions within the pattern. RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement in reference with the ideal bit position, please see AN-1217 (SNLA053) for detail. UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency. AC TIMING DIAGRAMS AND TEST CIRCUITS Device Pin Name Signal Pattern TCLK ODD DIN EVEN DIN Figure 1. Serializer Input Checkerboard Pattern Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 7 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com Device Pin Name Signal Pattern RCLK ODD ROUT EVEN ROUT Figure 2. Deserializer Output Checkerboard Pattern DOUT+ 10 pF Differential Signal 100: 80% 80% 20% Vdiff = 0V 20% DOUT10 pF tLLHT tLHLT Vdiff = (DOUT+) - (DOUT-) Figure 3. Serializer LVDS Output Load and Transition Times 80% VDD 80% TCLK 20% 20% tCLKT 0V tCLKT Figure 4. Serializer Input Clock Transition Times tTCP TCLK VDD/2 tDIS VDD/2 VDD/2 tDIH VDD DIN [0:23] VDD/2 Setup Hold VDD/2 0V Figure 5. Serializer Setup/Hold Times 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Parasitic package and Trace capcitance DOUT+ 5 pF 100: DOUTDEN tLZD DEN VCC/2 (single-ended) 0V VCC/2 0V CLK1 CLK1 tTCP tTCP DOUT± (differential) 200 mV DCA tZLD 200 mV DCA DCA DCA $OO GDWD ³0´V DCA DCA DCA DCA tHZD DEN VCC/2 (single-ended) 0V VCC/2 0V $OO GDWD ³1´V tZHD DCA 200 mV DCA DCA DCA DCA DCA DCA DCA 200 mV DOUT± (differential) tTCP tTCP CLK0 CLK0 Figure 6. Serializer TRI-STATE Test Circuit and Delay PWDWN 2.0V 0.8V tHZD or tLZD TCLK tPLD DOUT± TRI-STATE tZHD or tZLD Output Active TRI-STATE Figure 7. Serializer PLL Lock Time, and TPWDNB TRI-STATE Delays Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 9 DS90C124, DS90C241 DIN SYMBOL N www.ti.com SYMBOL N+1 SYMBOL N+2 | | SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 SYMBOL N+3 | tSD TCLK 23 0 1 2 23 0 1 2 23 0 1 2 STOP START BIT BIT 23 0 STOP BIT SYMBOL N 1 2 | | 2 STOP START BIT BIT SYMBOL N-1 | | 1 | | 0 | | DOUT0-23 DCA, DCB STOP START BIT BIT SYMBOL N-2 | | STOP START BIT BIT SYMBOL N-3 SYMBOL N-4 23 Figure 8. Serializer Delay Ideal Data Bit End Ideal Data Bit Beginning TxOUT_E_O tBIT(1/2UI) tBIT(1/2UI) Ideal Center Position (tBIT/2) tBIT (1UI) 24 DIN PARALLEL-TO-SERIAL Figure 9. Transmitter Output Eye Opening (TxOUT_E_O) DOUT+ RL DOUT- TCLK VOD = (DOUT+) – (DOUT -) Differential output signal is shown as (DOUT+) – (DOUT -), device in Data Transfer mode. Figure 10. Serializer VOD Diagram Single-ended Signal Deserializer 8 pF lumped 80% 80% 20% 20% tCLH tCHL Figure 11. Deserializer LVCMOS/LVTTL Output Load and Transition Times 10 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 23 0 1 2 23 0 1 2 23 0 1 2 STOP BIT | | 2 STOP START BIT BIT SYMBOL N+3 | | 1 STOP START BIT BIT SYMBOL N+2 | | 0 STOP START BIT BIT SYMBOL N+1 SYMBOL N | | START BIT RIN0-23 DCA, DCB 23 tDD RCLK SYMBOL N-3 ROUT0-23 SYMBOL N-2 SYMBOL N-1 SYMBOL N Figure 12. Deserializer Delay 500: VREF CL = 8pF VREF = VDD/2 for tZLR or tLZR, + - VREF = 0V for tZHR or tHZR REN VOH VDD/2 REN VDD/2 VOL tLZR tZLR VOL + 0.5V VOL + 0.5V VOL tHZR ROUT [23:0] tZHR VOH VOH - 0.5V VOH + 0.5V Note: CL includes instrumentation and fixture capacitance within 6 cm of ROUT[23:0] Figure 13. Deserializer TRI-STATE Test Circuit and Timing 2.0V PWDN 0.8V | | tDRDL RIN± LOCK TRI-STATE }v[š Œ TRI-STATE tHZR or tLZR ROUT [0:23] TRI-STATE TRI-STATE RCLK TRI-STATE TRI-STATE REN Figure 14. Deserializer PLL Lock Times and RPWDNB TRI-STATE Delay Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 11 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com tLOW RCLK tHIGH VDD/2 ROUT [7:0] VDD/2 VDD/2 tROS tROH (group 1) (group 1) Data Valid Before RCLK Data Valid After RCLK VDD/2 1/2 UI ROUT [15:8], LOCK 1/2 UI VDD/2 tROS tROH (group 2) (group 2) Data Valid Before RCLK Data Valid After RCLK VDD/2 1/2 UI ROUT [23:16] 1/2 UI VDD/2 tROS tROH (group 3) (group 3) Data Valid Before RCLK Data Valid After RCLK VDD/2 Figure 15. Deserializer Setup and Hold Times Ideal Data Bit Beginning Sampling Window RxIN_TOL -L Ideal Data Bit End RxIN_TOL -R Ideal Sampling Position tBIT ( ) 2 tBIT (1UI) RxIN_TOL_L is the ideal noise margin on the left of the figure, with respect to ideal. RxIN_TOL_R is the ideal noise margin on the right of the figure, with respect to ideal. Figure 16. Receiver Input Tolerance (RxIN_TOL) and Sampling Window 12 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 PIN ASSIGNMENTS DS90C241 Serializer Pin Descriptions Pin # Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 4-1, DIN[23:0] 48-44, 41-32, 29-25 LVCMOS_I Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float. 10 LVCMOS_I Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin. TCLK CONTROL AND CONFIGURATION PINS 9 TPWDNB LVCMOS_I Transmitter Power Down Bar TPWDNB = H; Transmitter is Enabled and ON TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver DOUT (+/-) Outputs are in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption. 18 DEN LVCMOS_I Transmitter Data Enable DEN = H; LVDS Driver Outputs are Enabled (ON). DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver DOUT (+/-) Outputs are in TRI-STATE, PLL still operational and locked to TCLK. 23 PRE LVCMOS_I Pre-emphasis Level Select PRE = NC (No Connect); Pre-emphasis is Disabled (OFF). Pre-emphasis is active when input is tied to VSS through external resistor RPRE. Resistor value determines pre-emphasis level. Recommended value RPRE ≥ 3 kΩ; Imax = [(1.2/R)*20], Rmin = 3 kΩ 11 TRFB LVCMOS_I Transmitter Clock Edge Select Pin TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge. TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge 12 VODSEL LVCMOS_I VOD Level Select VODSEL = L; LVDS Driver Output is ≈±400 mV (RL = 100Ω) VODSEL = H; LVDS Driver Output is ≈±750 mV (RL = 100Ω) For normal applications, set this pin LOW. For long cable applications where a larger VOD is required, set this pin HIGH. 5 DCAOFF LVCMOS_I Reserved. This pin MUST be tied LOW. 8 DCBOFF LVCMOS_I Reserved. This pin MUST be tied LOW. 13 RESRVD LVCMOS_I Reserved. This pin MUST be tied LOW. LVDS SERIAL INTERFACE PINS 20 DOUT+ LVDS_O Transmitter LVDS True (+) Output. This output is intended to be loaded with a 100Ω load to the DOUT+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor. 19 DOUT− LVDS_O Transmitter LVDS Inverted (-) Output This output is intended to be loaded with a 100Ω load to the DOUT-pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor. POWER / GROUND PINS 22 VDDDR VDD Analog Voltage Supply, LVDS Output Power 21 VSSDR GND Analog Ground, LVDS Output Ground 16 VDDPT0 VDD Analog Voltage supply, VCO Power 17 VSSPT0 GND Analog Ground, VCO Ground 14 VDDPT1 VDD Analog Voltage supply, PLL Power 15 VSSPT1 GND Analog Ground, PLL Ground 30 VDDT VDD Digital Voltage supply, Tx Serializer Power 31 VSST GND Digital Ground, Tx Serializer Ground 7 VDDL VDD Digital Voltage supply, Tx Logic Power 6 VSSL GND Digital Ground, Tx Logic Ground 42 VDDIT VDD Digital Voltage supply, Tx Input Power 43 VSSIT GND Digital Ground, Tx Input Ground 24 VSS GND ESD Ground Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 13 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com DS90C241 Pin Diagram DIN[5] VDDT DIN[4] DIN[3] DIN[2] DIN[1] DIN[0] 30 29 28 27 26 25 DIN[6] 33 VSST DIN[7] 34 31 DIN[8] 35 32 DIN[9] 36 Serializer - DS90C241 DIN[10] 37 24 VSS DIN[11] 38 23 PRE DIN[12] 39 22 VDDDR DIN[13] 40 21 VSSDR DIN[14] 41 20 DOUT+ VDDIT 42 19 DOUT- VSSIT 43 18 DEN DIN[15] 44 17 VSSPT0 DIN[16] 45 16 VDDPT0 DIN[17] 46 15 VSSPT1 DIN[18] 47 14 VDDPT1 DIN[19] 48 13 RESRVD 12 11 TRFB VODSEL 10 9 TPWDNB TCLK 8 6 VSSL 7 5 DCAOFF VDDL 4 DIN[23] DCBOFF 3 2 DIN[21] DIN[22] 1 DIN[20] DS90C241 48 PIN TQFP Figure 17. TOP VIEW DS90C124 Deserializer Pin Descriptions Pin # Pin Name I/O Description LVCMOS PARALLEL INTERFACE PINS 25-28, ROUT[7:0] 31-34 LVCMOS_O Receiver LVCMOS level Outputs – Group 1 13-16, ROUT[15:8] 21-24 LVCMOS_O Receiver LVCMOS level Outputs – Group 2 3-6, 9- ROUT[23:16] 12 LVCMOS_O Receiver LVCMOS level Outputs – Group 3 18 LVCMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin. RCLK CONTROL AND CONFIGURATION PINS 43 RRFB LVCMOS_I Receiver Clock Edge Select Pin RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge. RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge. 48 REN LVCMOS_I Receiver Data Enable REN = H; ROUT[23-0] and RCLK are Enabled (ON). REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs are in TRI-STATE, PLL still operational and locked to TCLK. 1 RPWDNB LVCMOS_I Receiver Power Down Bar RPWDNB = H; Receiver is Enabled and ON RPWDNB = L; Receiver is in power down mode (Sleep), ROUT[23-0], RCLK, and LOCK are in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption. 17 LOCK LVCMOS_O LOCK indicates the status of the receiver PLL LOCK = H; receiver PLL is locked LOCK = L; receiver PLL is unlocked, ROUT[23-0] and RCLK are TRI-STATED 14 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com Pin # 2 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Pin Name RESRVD I/O LVCMOS_I Description Reserved. This pin MUST be tied LOW. LVDS SERIAL INTERFACE PINS 41 RIN+ LVDS_I Receiver LVDS True (+) Input This input is intended to be terminated with a 100Ω load to the RIN+ pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor. 42 RIN− LVDS_I Receiver LVDS Inverted (−) Input This input is intended to be terminated with a 100Ω load to the RIN-pin. The interconnect should be AC Coupled to this pin with a 100 nF capacitor. POWER / GROUND PINS 39 VDDIR VDD Analog LVDS Voltage supply, Power 40 VSSIR GND Analog LVDS Ground 47 VDDPR0 VDD Analog Voltage supply, PLL Power 46 VSSPR0 GND Analog Ground, PLL Ground 45 VDDPR1 VDD Analog Voltage supply, PLL VCO Power 44 VSSPR1 GND Analog Ground, PLL VCO Ground 37 VDDR1 VDD Digital Voltage supply, Logic Power 38 VSSR1 GND Digital Ground, Logic Ground 36 VDDR0 VDD Digital Voltage supply, Logic Power 35 VSSR0 GND Digital Ground, Logic Ground 30 VDDOR1 VDD Digital Voltage supply, LVCMOS Output Power 29 VSSOR1 GND Digital Ground, LVCMOS Output Ground 20 VDDOR2 VDD Digital Voltage supply, LVCMOS Output Power 19 VSSOR2 GND Digital Ground, LVCMOS Output Ground 7 VDDOR3 VDD Digital Voltage supply, LVCMOS Output Power 8 VSSOR3 GND Digital Ground, LVCMOS Output Ground Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 15 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com DS90C124 Pin Diagram VSSOR1 ROUT[4] ROUT[5] ROUT[6] ROUT[7] 29 28 27 26 25 32 ROUT[3] ROUT[2] 33 VDDOR1 ROUT[1] 34 30 ROUT[0] 35 31 VDDR0 VSSR0 36 Deserializer - DS90C124 PTO GROUP 1 37 24 ROUT[8] VSSR1 38 23 ROUT[9] VDDIR 39 22 ROUT[10] VSSIR 40 21 ROUT[11] RIN+ 41 20 VDDOR2 RIN- 42 19 VSSOR2 RRFB 43 18 RCLK VSSPR1 44 17 LOCK VDDPR1 45 16 ROUT[12] VSSPR0 46 15 ROUT[13] VDDPR0 47 14 ROUT[14] REN 48 13 ROUT[15] PTO GROUP 2 VDDR1 DS90C124 48 PIN TQFP 10 11 12 ROUT[18] ROUT[17] ROUT[16] 7 VDDOR3 9 6 ROUT[20] 8 5 ROUT[21] VSSOR3 4 ROUT[19] 3 ROUT[22] 2 RESRVD ROUT[23] 1 RPWDNB PTO GROUP 3 Figure 18. TOP VIEW FUNCTIONAL DESCRIPTION The DS90C241 Serializer and DS90C124 Deserializer chipset is an easy-to-use transmitter and receiver pair that sends 24-bits of parallel LVCMOS data over a single serial LVDS link from 120 Mbps to 840 Mbps throughput. The DS90C241 transforms a 24-bit wide parallel LVCMOS data into a single high speed LVDS serial data stream with embedded clock and scrambles / DC Balances the data to enhance signal quality to support AC coupling. The DS90C124 receives the LVDS serial data stream and converts it back into a 24-bit wide parallel data and recovered clock. The 24-bit Serializer/Deserializer chipset is designed to transmit data up to 10 meters over shielded twisted pair (STP) at clock speeds from 5 MHz to 35 MHz. The Deserializer can attain lock to a data stream without the use of a separate reference clock source; greatly simplifying system complexity and overall cost. The Deserializer synchronizes to the Serializer regardless of data pattern, delivering true automatic “plug and lock” performance. It will lock to the incoming serial stream without the need of special training patterns or sync characters. The Deserializer recovers the clock and data by extracting the embedded clock information and validating data integrity from the incoming data stream and then deserializes the data. The Deserializer monitors the incoming clock information, determines lock status, and asserts the LOCK output high when lock occurs. Each has a power down control to enable efficient operation in various applications. INITIALIZATION AND LOCKING MECHANISM Initialization of the DS90C241 and DS90C124 must be established before each device sends or receives data. Initialization refers to synchronizing the Serializer’s and Deserializer’s PLL’s together. After the Serializers locks to the input clock source, the Deserializer synchronizes to the Serializers as the second and final initialization step. 16 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Step 1: When VCC is applied to both Serializer and/or Deserializer, the respective outputs are held in TRI-STATE and internal circuitry is disabled by on-chip power-on circuitry. When VCC reaches VCC OK (2.2V) the PLL in Serializer begins locking to a clock input. For the Serializer, the local clock is the transmit clock, TCLK. The Serializer outputs are held in TRI-STATE while the PLL locks to the TCLK. After locking to TCLK, the Serializer block is now ready to send data patterns. The Deserializer output will remain in TRI-STATE while its PLL locks to the embedded clock information in serial data stream. Also, the Deserializer LOCK output will remain low until its PLL locks to incoming data and sync-pattern on the RIN± pins. Step 2: The Deserializer PLL acquires lock to a data stream without requiring the Serializer to send special patterns. The Serializer that is generating the stream to the Deserializer will automatically send random (nonrepetitive) data patterns during this step of the Initialization State. The Deserializer will lock onto embedded clock within the specified amount of time. An embedded clock and data recovery (CDR) circuit locks to the incoming bit stream to recover the high-speed receive bit clock and re-time incoming data. The CDR circuit expects a coded input bit stream. In order for the Deserializer to lock to a random data stream from the Serializer, it performs a series of operations to identify the rising clock edge and validates data integrity, then locks to it. Because this locking procedure is independent on the data pattern, total random locking duration may vary. At the point when the Deserializer’s CDR locks to the embedded clock, the LOCK pin goes high and valid RCLK/data appears on the outputs. Note that the LOCK signal is synchronous to valid data appearing on the outputs. The Deserializer’s LOCK pin is a convenient way to ensure data integrity is achieved on receiver side. DATA TRANSFER After Serializer lock is established, the inputs DIN0–DIN23 may be used to input data to the Serializer. Data is clocked into the Serializer by the TCLK input. The edge of TCLK used to strobe the data is selectable via the TRFB pin. TRFB high selects the rising edge for clocking data and low selects the falling edge. The Serializer outputs (DOUT±) are intended to drive point-to-point connections as shown in Figure 20. CLK1, CLK0, DCA, DCB are four overhead bits transmitted along the single LVDS serial data stream. The CLK1 bit is always high and the CLK0 bit is always low. The CLK1 and CLK0 bits function as the embedded clock bits in the serial stream. DCB functions as the DC Balance control bit. It does not require any pre-coding of data on transmit side. The DC Balance bit is used to minimize the short and long-term DC bias on the signal lines. This bit operates by selectively sending the data either unmodified or inverted. The DCA bit is used to validate data integrity in the embedded data stream. Both DCA and DCB coding schemes are integrated and automatically performed within Serializer and Deserializer. Serialized data and clock/control bits (24+4 bits) are transmitted from the serial data output (DOUT±) at 28 times the TCLK frequency. For example, if TCLK is 35 MHz, the serial rate is 35 x 28 = 980 Mega bits per second. Since only 24 bits are from input data, the serial “payload” rate is 24 times the TCLK frequency. For instance, if TCLK = 35 MHz, the payload data rate is 35 x 24 = 840 Mbps. TCLK is provided by the data source and must be in the range of 5 MHz to 35 MHz nominal. The Serializer outputs (DOUT±) can drive a point-to-point connection. The outputs transmit data when the enable pin (DEN) is high, TPWDNB is high. The DEN pin may be used to TRI-STATE the outputs when driven low. When the Deserializer channel attains lock to the input from a Serializer, it drives its LOCK pin high and synchronously delivers valid data and recovered clock on the output. The Deserializer locks onto the embedded clock, uses it to generate multiple internal data strobes, and then drives the recovered clock to the RCLK pin. The recovered clock (RCLK output pin) is synchronous to the data on the ROUT[23:0] pins. While LOCK is high, data on ROUT[23:0] is valid. Otherwise, ROUT[23:0] is invalid. The polarity of the RCLK edge is controlled by the RRFB input. ROUT(0-23), LOCK and RCLK outputs will each drive a maximum of 8 pF load with a 35 MHz clock. REN controls TRI-STATE for ROUTn and the RCLK pin on the Deserializer. RESYNCHRONIZATION If the Deserializer loses lock, it will automatically try to re-establish lock. For example, if the embedded clock edge is not detected one time in succession, the PLL loses lock and the LOCK pin is driven low. The Deserializer then enters the operating mode where it tries to lock to a random data stream. It looks for the embedded clock edge, identifies it and then proceeds through the locking process. The logic state of the LOCK signal indicates whether the data on ROUT is valid; when it is high, the data is valid. The system must monitor the LOCK pin to determine whether data on the ROUT is valid. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 17 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com POWERDOWN The Powerdown state is a low power sleep mode that the Serializer and Deserializer may use to reduce power when no data is being transferred. The TPWDNB and RPWDNB are used to set each device into power down mode, which reduces supply current to the µA range. The Serializer enters powerdown when the TPWDNB pin is driven low. In powerdown, the PLL stops and the outputs go into TRI-STATE, disabling load current and reducing supply. To exit Powerdown, TPWDNB must be driven high. When the Serializer exits Powerdown, its PLL must lock to TCLK before it is ready for the Initialization state. The system must then allow time for Initialization before data transfer can begin. The Deserializer enters powerdown mode when RPWDNB is driven low. In powerdown mode, the PLL stops and the outputs enter TRI-STATE. To bring the Deserializer block out of the powerdown state, the system drives RPWDNB high. Both the Serializer and Deserializer must reinitialize and relock before data can be transferred. The Deserializer will initialize and assert LOCK high when it is locked to the input clock. TRI-STATE For the Serializer, TRI-STATE is entered when the DEN or TPWDNB pin is driven low. This will TRI-STATE both driver output pins (DOUT+ and DOUT−). When DEN is driven high, the serializer will return to the previous state as long as all other control pins remain static (TPWDNB, TRFB). When you drive the REN or RPWDNB pin low, the Deserializer enters TRI-STATE. Consequently, the receiver output pins (ROUT0–ROUT23) and RCLK will enter TRI-STATE. The LOCK output remains active, reflecting the state of the PLL. The Deserializer input pins are high impedance during receiver powerdown (RPWDNB low) and power-off (VCC = 0V). PRE-EMPHASIS The DS90C241 features a Pre-Emphasis function used to compensate for long or lossy transmission media. Cable drive is enhanced with a user selectable Pre-Emphasis feature that provides additional output current during transitions to counteract cable loading effects. The transmission distance will be limited by the loss characteristics and quality of the media. Pre-Emphasis adds extra current during LVDS logic transition to reduce the cable loading effects and increase driving distance. In addition, Pre-Emphasis helps provide faster transitions, increased eye openings, and improved signal integrity. To enable the Pre-Emphasis function, the “PRE” pin requires one external resistor (Rpre) to Vss in order to set the additional current level. Pre-Emphasis strength is set via an external resistor (Rpre) applied from min to max (floating to 3kΩ) at the “PRE” pin. A lower input resistor value on the ”PRE” pin increases the magnitude of dynamic current during data transition. There is an internal current source based on the following formula: PRE = (Rpre ≥ 3kΩ); IMAX = [(1.2/Rpre) X 20]. The ability of the DS90C241 to use the Pre-Emphasis feature will extend the transmission distance up to 10 meters in most cases. The amount of Pre-Emphasis for a given media will depend on the transmission distance of the application. In general, too much Pre-Emphasis can cause over or undershoot at the receiver input pins. This can result in excessive noise, crosstalk and increased power dissipation. For short cables or distances, Pre-Emphasis may not be required. Signal quality measurements are recommended to determine the proper amount of PreEmphasis for each application. AC-COUPLING AND TERMINATION The DS90C241 and DS90C124 supports AC-coupled interconnects through integrated DC balanced encoding/decoding scheme. To use AC coupled connection between the Serializer and Deserializer, insert external AC coupling capacitors in series in the LVDS signal path as illustrated in Figure 20. The Deserializer input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to +1.2V. With AC signal coupling, capacitors provide the ac-coupling path to the signal input. For the high-speed LVDS transmissions, the smallest available package should be used for the AC coupling capacitor. This will help minimize degradation of signal quality due to package parasitics. The most common used capacitor value for the interface is 100 nF (0.1 uF) capacitor. NPO class 1 or X7R class 2 type capacitors are recommended. 50 WVDC should be the minimum used for the best system-level ESD performance. The DS90C124 input stage is designed for AC-coupling by providing a built-in AC bias network which sets the internal VCM to +1.2V. Therefore multiple termination options are possible. 18 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 Receiver Termination Option 1 A single 100 Ohm termination resistor is placed across the RIN± pins (see Figure 20). This provides the signal termination at the Receiver inputs. Other options may be used to increase noise tolerance. Receiver Termination Option 2 For additional EMI tolerance, two 50 Ohm resistors may be used in place of the single 100 Ohm resistor. A small capacitor is tied from the center point of the 50 Ohm resistors to ground (see Figure 23). This provides a highfrequency low impedance path for noise suppression. Value is not critical, 4.7nF maybe used with general applications. Receiver Termination Option 3 For high noise environments an additional voltage divider network may be connected to the center point. This has the advantage of a providing a DC low-impedance path for noise suppression. Use resistor values in the range of 75Ω-2KΩ for the pullup and pulldown. Ratio the resistor values to bias the center point at 1.2V. For example (see Figure 24): VDD=3.3V, Rpullup=1.3KΩ, Rpulldown=750Ω; or Rpullup=130Ω, Rpulldown=75Ω (strongest). The smaller values will consume more bias current, but will provide enhanced noise suppression. PROGRESSIVE TURN–ON (PTO) Deserializer ROUT[23:0] outputs are grouped into three groups of eight, with each group switching about 0.5UI apart in phase to reduce EMI, simultaneous switching noise, and system ground bounce. APPLICATIONS INFORMATION USING THE DS90C241 AND DS90C124 The DS90C241/DS90C124 Serializer/Deserializer (SERDES) pair sends 24 bits of parallel LVCMOS data over a serial LVDS link up to 840 Mbps. Serialization of the input data is accomplished using an on-board PLL at the Serializer which embeds clock with the data. The Deserializer extracts the clock/control information from the incoming data stream and deserializes the data. The Deserializer monitors the incoming clockl information to determine lock status and will indicate lock by asserting the LOCK output high. DISPLAY APPLICATION The DS90C241/DS90C124 chipset is intended for interface between a host (graphics processor) and a Display. It supports an 18-bit color depth (RGB666) and up to 800 X 480 display formats. In a RGB666 configuration 18 color bits (R[5:0], G[5:0], B[5:0]), Pixel Clock (PCLK) and three control bits (VS, HS and DE) along with three spare bits are supported across the serial link with PCLK rates from 5 to 35 MHz. TYPICAL APPLICATION CONNECTION Figure 21 shows a typical application of the DS90C241 Serializer (SER). The LVDS outputs utilize a 100 ohm termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins. A system GPO (General Purpose Output) controls the TPWDNB pin. In this application the TRFB pin is tied High to latch data on the rising edge of the TCLK. The DEN signal is not used and is tied High also. In this application the link is short, therefore the VODSEL pin is tied Low for the standard LVDS swing. The pre-emphasis input utilizes a resistor to ground to set the amount of pre-emphasis desired by the application. Figure 22 shows a typical application of the DS90C124 Deserializer (DES). The LVDS inputs utilize a 100 ohm termination and 100nF coupling capacitors to the line. Bypass capacitors are placed near the power supply pins. A system GPO (General Purpose Output) controls the RPWDNB pin. In this application the RRFB pin is tied High to strobe the data on the rising edge of the RCLK. The REN signal is not used and is tied High also. POWER CONSIDERATIONS An all CMOS design of the Serializer and Deserializer makes them inherently low power devices. Additionally, the constant current source nature of the LVDS outputs minimize the slope of the speed vs. ICC curve of CMOS designs. Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 19 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com NOISE MARGIN The Deserializer noise margin is the amount of input jitter (phase noise) that the Deserializer can tolerate and still reliably recover data. Various environmental and systematic factors include: • Serializer: TCLK jitter, VCC noise (noise bandwidth and out-of-band noise) • Media: ISI, VCM noise • Deserializer: VCC noise For a graphical representation of noise margin, please see Figure 16. TRANSMISSION MEDIA The Serializer and Deserializer can be used in point-to-point configuration, through a PCB trace, or through twisted pair cable. In a point-to-point configuration, the transmission media needs be terminated at both ends of the transmitter and receiver pair. Interconnect for LVDS typically has a differential impedance of 100 Ohms. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. In most applications that involve cables, the transmission distance will be determined on data rates involved, acceptable bit error rate and transmission medium. The resulting signal quality at the receiving end of the transmission media may be assessed by monitoring the differential eye opening of the serial data stream. The Receiver Input Tolerance and Differential Threshold Voltage specifications define the acceptable data eye opening. A differential probe should be used to measure across the termination resistor at the DS90C124 inputs. Figure 19 illustrates the eye opening and relationship to the Receiver Input Tolerance and Differential Threshold Voltage specifications. Ideal Data Bit Beginning RxIN_TOL -L Ideal Data Bit End Minimum Eye Width • VTH - VTL RxIN_TOL -R tBIT (1UI) Figure 19. Receiver Input Eye Opening LIVE LINK INSERTION The Serializer and Deserializer devices support live pluggable applications. The automatic receiver lock to random data “plug & go” hot insertion capability allows the DS90C124 to attain lock to the active data stream during a live insertion event. PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS SERDES devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at high frequencies, and makes the value and placement of external bypass capacitors less critical. External bypass capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the tantalum capacitors should be at least 5X the power supply voltage being used. Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per supply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power entry. This is typically in the 50uF to 100uF range and will smooth low frequency switching noise. It is recommended to connect power and ground pins directly to the power and ground planes with bypass capacitors connected to the plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypass capacitor will increase the inductance of the path. 20 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of these external bypass capacitors, usually in the range of 20-30 MHz range. To provide effective bypassing, multiple capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing the impedance at high frequency. Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not required. Pin Description tables typically provide guidance on which circuit blocks are connected to which power pin pairs. In some cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs. Use at least a four layer board with a power and ground plane. Locate LVCMOS (LVTTL) signals away from the LVDS lines to prevent coupling from the LVCMOS lines to the LVDS lines. Closely-coupled differential lines of 100 Ohms are typically recommended for LVDS interconnect. The closely coupled lines help to ensure that coupled noise will appear as common-mode and thus is rejected by the receivers. The tightly coupled lines will also radiate less. Termination of the LVDS interconnect is required. For point-to-point applications, termination should be located at both ends of the devices. Nominal value is 100 Ohms to match the line’s differential impedance. Place the resistor as close to the transmitter DOUT± outputs and receiver RIN± inputs as possible to minimize the resulting stub between the termination resistor and device. LVDS INTERCONNECT GUIDELINES See AN-1108 (SNLA008) and AN-905 (SNLA035) for full details. • Use 100Ω coupled differential pairs • Use the S/2S/3S rule in spacings – S = space between the pair – 2S = space between pairs – 3S = space to LVCMOS/LVTTL signal • Minimize the number of VIA • Use differential connectors when operating above 500Mbps line speed • Maintain balance of the traces • Minimize skew within the pair • Terminate as close to the TX outputs and RX inputs as possible Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TI web site at:www.ti.com/lvds DOUT+ 100 nF RIN+ 100 nF 100: DOUT- 100: 100 nF RIN- 100 nF Figure 20. AC Coupled Application Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 21 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com DS90C241 (SER) VDDDR DIN0 DIN1 DIN2 DIN3 DIN4 DIN5 DIN6 DIN7 C5 C3 C6 C7 Serial LVDS Interface R1 GPO DOUTTPWDNB DEN TRFB DCAOFF DCBOFF VODSEL PRE RESRVD R2 C2 DOUT+ TCLK TPWDNB = System GPO DEN = High (ON) TRFB = High (Rising edge) VODSEL = Low (400mV) PRE = Rpre RESRVD = Low DCAOFF = Low DCBOFF = Low C4 VDDIT VDDL VDDT DIN16 DIN17 DIN18 DIN19 DIN20 DIN21 DIN22 DIN23 3.3V C1 VDDPT0 VDDPT1 DIN8 DIN9 DIN10 DIN11 DIN12 DIN13 DIN14 DIN15 LVCMOS Parallel Interface 3.3V VSSDR VSSPT0 VSSPT1 VSST VSSL VSSIT VSS C8 C1 to C3 = 0.1 PF C4 to C6 = 0.01 PF C7 = 100 nF; 50WVDC, NPO or X7R C8 = 100 nF; 50WVDC, NPO or X7R R1 = 100: R2 = Open (OFF) or Rpre t 3 k: (ON) (cable specific) Figure 21. DS90C241 Tyical Application Connection 22 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 DS90C124 (DES) 3.3V VDDIR C5 VDDPR0 VDDPR1 C6 VDDOR1 VDDOR2 VDDOR3 C7 C9 RIN+ Serial LVDS Interface R1 RINC10 3.3V GPO RPWDNB REN RRFB RPWDNB = System GPO REN = High (ON) RRFB = High (Rising edge) RESRVD = Low RESRVD C1 C2 C3 C4 VDDR0 VDDR1 C8 C1 to C8 = 0.1 PF to 0.01 PF C9 = 100 nF; 50 WVDC, NPO or X7R C10 = 100 nF; 50 WVDC, NPO or X7R R1 = 100: 3.3V ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 ROUT7 ROUT8 ROUT9 ROUT10 ROUT11 ROUT12 ROUT13 ROUT14 ROUT15 LVCMOS Parallel Interface ROUT16 ROUT17 ROUT18 ROUT19 ROUT20 ROUT21 ROUT22 ROUT23 VSSIR VSSOR1 VSSOR2 VSSOR3 VSSPR0 VSSPR1 VSSR0 VSSR1 RCLK LOCK Figure 22. DS90C124 Tyical Application Connection 0.1 PF 0.1 PF RIN+ 50: DS90C241 DS90C124 100: 4.7 nF 50: RIN0.1 PF 0.1 PF Figure 23. Receiver Termination Option 2 Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 23 DS90C124, DS90C241 SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 www.ti.com VDD 0.1 PF 0.1 PF RIN+ RPU DS90C241 50: DS90C124 100: 4.7 nF RPD 50: RIN- 0.1 PF 0.1 PF Figure 24. Receiver Termination Option 3 Truth Tables Table 1. DS90C241 Serializer Truth Table TPWDNB (Pin 9) DEN (Pin 18) Tx PLL Status (Internal) LVDS Outputs (Pins 19 and 20) L X X Hi Z Hi Z H L X H H Not Locked Hi Z H H Locked Serialized Data with Embedded Clock Table 2. DS90C124 Deserializer Truth Table 24 RPWDNB (Pin 1) REN (Pin 48) Rx PLL Status (Internal) ROUTn and RCLK (See Pin Diagram) LOCK (Pin 17) L X X Hi Z Hi Z H L X Hi Z L = PLL Unocked; H = PLL Locked H H Not Locked Hi Z L H H Locked Data and RCLK Active H Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 DS90C124, DS90C241 www.ti.com SNLS209L – NOVEMBER 2005 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision K (April 2013) to Revision L • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 24 Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90C124 DS90C241 Submit Documentation Feedback 25 PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) DS90C124IVS/NOPB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS90C124 IVS DS90C124IVSX/NOPB ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS90C124 IVS DS90C124QVS/NOPB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS90C124 QVS DS90C124QVSX/NOPB ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS90C124 QVS DS90C241IVS/NOPB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS90C241 IVS DS90C241IVSX/NOPB ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS90C241 IVS DS90C241QVS/NOPB ACTIVE TQFP PFB 48 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS90C241 QVS DS90C241QVSX/NOPB ACTIVE TQFP PFB 48 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 105 DS90C241 QVS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 12-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF DS90C124, DS90C124-Q1, DS90C241, DS90C241-Q1 : • Catalog: DS90C124, DS90C241 • Automotive: DS90C124-Q1, DS90C241-Q1 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90C124IVSX/NOPB TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.0 Q2 DS90C124QVSX/NOPB TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.0 Q2 DS90C241IVSX/NOPB TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.0 Q2 DS90C241QVSX/NOPB TQFP PFB 48 1000 330.0 16.4 9.3 9.3 2.2 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90C124IVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 DS90C124QVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 DS90C241IVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 DS90C241QVSX/NOPB TQFP PFB 48 1000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MTQF019A – JANUARY 1995 – REVISED JANUARY 1998 PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°– 7° 1,05 0,95 Seating Plane 0,75 0,45 0,08 1,20 MAX 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated