L4938E/ED L4938EPD ADVANCED VOLTAGE REGULATOR ENABLE AND SENSE INPUTS (EN, SI) PROTECTED AGAINST NEGATIVE TRANSIENTS DOWN TO -5V RESET THRESHOLD ADJUSTABLE FROM 3.8 TO 4.7V EXTREMELY LOW QUIESCENT CURRENT, 65µA (LESS THAN 90µA) IN STANDBY MODE OPERATING DC SUPPLY VOLTAGE RANGE 5V - 28V OPERATING TRANSIENT SUPPLY VOLTAGE UP TO 40V HIGH PRECISION STANDBY OUTPUT VOLTAGE 5V ± 1% WITH 100mA CURRENT CAPABILITY OUTPUT 2 VOLTAGE 5V ± 2% WITH 400mA CURRENT CAPABILITY (ADJ WIRED TO VOUT2) OUTPUT 2 VOLTAGE ADJUSTABLE BY EXTERNAL VOLTAGE DIVIDER OUTPUT 2 DISABLE FUNCTION FOR STANDBY MODE DIP (12+2+2) SO20 (12+4+4) PowerSO20 ORDERING NUMBERS: L4938E (DIP) L4938ED (SO) L4938EPD (PSO) DESCRIPTION The L4938E/ED/EPD is a monolithic integrated dual voltage regulator with two very low dropout outputs and additional functions as power-on reset and input voltage sense. It is designed for supplying the microcomputer controlled systems especially in automotive applications. PIN CONNECTIONS PR 1 16 SI PR 1 20 SI CT 2 19 VS1 GND 1 20 GND N.C. 2 19 N.C. CT 2 15 VS1 EN 3 18 VS2 3 18 OUT2 EN 3 14 VS2 VS2 GND 4 17 GND VS1 4 17 ADJ GND 4 13 GND GND 5 16 GND SI 5 16 OUT1 GND 5 12 GND GND 6 15 GND PR 6 15 SO RES 6 11 N.C. GND 7 14 GND CT 7 14 RESET SO 7 10 OUT2 RES 8 13 N.C. EN 8 13 N.C. OUT1 8 9 SO 9 12 OUT2 N.C. 9 12 N.C. 11 ADJ GND 10 11 GND D94AT075A ADJ OUT1 10 D94AT076A DIP (12+2+2) February 1999 SO (12+4+4) L4938EPD PowerSO20 1/12 L4938E - L4938ED - L4938EPD ABSOLUTE MAXIMUM RATINGS Symbol VINDC V INTR IO VSI ISI V EN IEN VRES , VSO IRES , ISO PO Tstg Tj TJSD Parameter DC Operating Supply Voltage Transient Operating Supply Voltage (T < 400ms) Output Current Sense Input Voltage (Voltage Forced) (note 2) Sense Input Current (Current Forced) (note 2) Enable Input Voltage (Voltage Forced) (note 2) Sense Input Current (Current Forced) (note 2) Output Voltages Output Currents (Output Low) Power Dissipation at Tamb = 80°C (note 3) Powerdip 12+2+2 Storage Temperature Operating Junction Temperature Thermal shutdown junction temperature Output 2 will shut-down typically at Tj 10K lower than output 1 Value 28 -14 to 40 internally limited -20 to 20 ±1 -20 to 20 ±1 -0.3 to 20 5 875 Unit V V -65 to 150 -40 to 150 165 °C °C °C V mA V mA V mA mW Note 1: The circuit is ESD protected according to MIL-STD-883C Note 2: Current forced means voltage unlimited but current limited to the specified value Voltage forced means voltage limi ted to the specified valueswhile the current is not limited 2 Note 3: Typical value soldered on a PC board with 8cm copper ground plane (35mm thick). BLOCK DIAGRAM OUT1 VS1 1.23V REFERENCE REG1 OUT2 VS2 ADJ EN 1.23V REG2 CT 1.23V RES PR 1.4V RESET SO SI 1.23V GND SENSE D94AT074A 2/12 L4938E - L4938ED - L4938EPD THERMAL DATA Symbol Parameter DIP 12+2+2 SO 12+4+4 PowerSO20 Rth j-amb Thermal Resistance Junction to ambient Rth j-case Thermal Resistance Junction to case Unit 40 50 - °C/W - - <2 °C/W 2 Note 3: Typical value soldered on a PC board with 8cm copper ground plane (35mm thick). PIN FUNCTIONS PIN (DIP 12+2+2) 14 15 16 1 2 3 4, 5, 12, 13 PIN (SO 12+4+4) 18 19 20 1 2 3 4, 5, 6, 7, 14, 15, 16, 17 8 9 10 11 12 13 6 7 8 9 10 11 PIN PowerSO20 3 4 5 6 7 8 1,10,11,20 14 15 16 17 18 2,9,19 Name VS2 VS1 S1 PR CT EN GND RES SO OUT 1 ADJ OUT 2 NC Function Supply Voltage (400mA Regulator) Supply Voltage (100mA Regulator, Reset, Sense) Sense Input Reset Theresold Programming Reset Delay Capacitor Enable (low will activate the 400mA regulator) Ground Reset Output Sense Output 100mA Regulator Output Feedback of 400mA Regulator 400mA Regulator Output Not Connected ELECTRICAL CHARACTERISTICS (VS = 14V; Tj = -40 to 150°C unless otherwise specified.) Symbol Parameter Test Condition Min. Typ. Max. Unit 4.9 5 5.1 V 4.8 5 0.1 0.2 5.2 0.2 0.4 25 V V V mV 100 200 65 400 90 mA µA OUT 1 V O1 Supply Output Voltage VDP1 Dropoutput Voltage 1 VOL01 Load Regulation 1 VLIM1 IQSB Current Limit 1 Quiescent Current in Standby Mode VS = 6 to 28V; IO1 = 400µA to 100mA Tj ≤125°C; IO1 = 50 to 400µA IOUT1 = 10mA IOUT1 = 100mA; VS = 4.8V IOUT1 = 1 to 100mA (after regulation setting) VOUT1 = 0.8 to 4.5V IEN ≥ 2.4V (output 2 disabled) IO1 = 0.1mA; VSI > 1.3V TJ < 85°C; R PR = 0 µA 75 OUT 2 V O2 VDP2 Output Voltage 2 ADJ connected to OUT 2 Dropoutput Voltage 2 VOL02 Load Regulation 2 RADJ ILIM2 IQ Adjust Input Resistance Current Limit 2 Quiescent Current Enable = LOW; VS = 6 to 28V; I02 = 5 to 400mA IOUT2 = 100mA IOUT2 = 400mA; VS = 4.8V IOUT1 = 5 to 400mA (after regulation setting) V02 = 0.8 to 4.5V IOUT1 = 100mA; IOUT2 = 400mA 4.9 60 450 5.1 V 0.2 0.3 0.3 0.6 50 V V mV 100 650 150 1300 20 mA mA mA 20 mV OUT1, OUT 2 VOLi 1,2 Line Regulation VS = 6 to 28V; IO1 = 1mA, IO2 = 5mA, (after regulation setting) 3/12 L4938E - L4938ED - L4938EPD ELECTRICAL CHARACTERISTICS (Continued) Symbol Parameter Test Condition Min. Typ. Max. Unit 1 V ENABLE INPUT VENL Enable Input Low Voltage (Output 2 Active) -20 VENH Enable Input High Voltage 1.4 20 V VENhyst Enable Hysteresis 20 30 60 mV IEN LOW Enable Input Current Low VEN = 0 -20 -8 -3 µA IEN HIGH Enable Input Current High VEN = 1.1 to 7V; TJ < 130°C; -1 0 1 µA VEN = 1.1 to 7V; TJ = 130 to 150°C; -10 0 10 µA RESET CIRCUIT Reset Theresold Voltage (note4) R PR = ∞ 4.5 R PR = 0 3.65 3.8 3.95 V VRTH Reset Theresold Hysteresis R PR = ∞ 30 60 120 mV tRD min Reset Pulse Delay C RES = 47nF; t r ≤ 30µs; (note 5) 40 60 100 ms tRD nom Reset Pulse Delay C RES = 47nF; (note 6) 60 100 140 ms tRR Reset Reaction Time C RES = 47nF 10 50 150 µs ICT Pull Down Capability of the Discharge circuit VOUT1 < VRT 3 6 15 mA ICT -1.3 -1 V RT Charge Current VOUT1 > VRT VRESL Reset Output Low Voltage R RES = 10KΩ to VOUT1 VOUT1 ≥ 1.5V VRESH Reset Output High Leakage current VRES = 5V VO1-0.3 VO1-0.2 V 0.7 µA 0.4 V 1 µA SENSE COMPARATOR VSI Functional Range VSIT Sense Threshold Voltage 20 V Falling Edge; TJ <130°C 1.08 -20 1.16 1.24 V Falling Edge; TJ <130 to 150°C 1.05 1.16 1.29 V 10 30 VSITH Sense Threshold Hysteresis VSOL Sense Output Low Voltage V SI ≤ 1.05V; RSO =10KΩ connected to 5V; V S ≥ 5V ISOH Sense Output Leakage VSO = 5V; VSI ≥ 1.5V Sense Input Current High VSI = 1.1 to 7V; TJ <130°C -1 0 VSI = 1.1 to 7V; TJ <130 to 150°C -10 0 10 µA VSI = 0V -20 -8 -3 µA ISI HIGH ISI LOW Sense Input Current Low 60 mV 0.4 V 1 µA 1 µA Note : 4) The reset threshold can be programmed continuously from typ 3.8V to 4.7V by changing a value of an external resistor from pin PR to GN 5) This is a minimum reset time according to the hysteresis of the comparator. Delay time starts with VOUT1 exceeding VRT 6) This is the nominal reset time depending on the discharging limit of C T (saturation voltage) and theupper threshold of the timer comparator. Delay time starts with VOUT1 exceeding VRT 7) The leakage of CT must be less than 0.5mA (2V). If an external resistor between C T and VOUT1 is applied, the leakage current may be increased. The external resistor should have more than 30KΩ. for stability: Cs ≥ 1µF, C01 ≥ 10µF, C02 ≥ 10µF, ESR ≤ 5Ω (designed target) For details see application note. 8) For transients exceeding 20V or -20V external protection is required at the Pins SI and EN as shown at Pin EN. The protection proposed will provide proper function for transients in the range of ±200V. If the zener diode is omitted the external resistor should be raised to 200KΩ to limit the current to 1mA. Without the zener diode, the function 20V or -20V can not be guaran teed. 4/12 L4938E - L4938ED - L4938EPD Figure 1. Application Diagram. VS1 OUT1 CS CO1 1.23V REFERENCE REG1 (Note 8) OUT2 VS2 100K 15V CO2 ADJ EN 1.23V REG2 for example BZX97C15 CT (Note 7) CT 1.23V RES VOUT1 PR 1.4V RESET RSO SO SI 1.23V GND SENSE D94AT079A FUNCTIONAL DESCRIPTION The L4938E/ED/EPD is a monolithic integrated dual voltage regulator, based on the STM modulator voltage regulator approach. Several outstanding features and auxiliary functions are implemented to meet the requirements of supplying microprocessor systems in automotive applications. Nevertheless, it is suitable also in other applications where two stabilized voltages are required. The modular approach of this device allows to get easly also other features and functions when required. Standby Regulator The standby regulator uses an Isolated collector Vertical PNP transistor as a regulating element. With this structure very low dropout volotage at currents up to 100mA is obtained. The dropout operation of the standby regulator is maintained down to 3V input supply voltage. The output voltage is regulated up to the transient input supply voltage of 40V. With this feature no functional interruption due to overvoltage pulses is generated. In the standby mode when the output 2 is disabled, the current consumption of the device (quiescent current) is less than 90µA (14V supply voltage). To reduce the quiescent current peak in the undervoltage region and to improve the transient response in this region, the dropout voltage is controlled. A second regulation path will keep the output voltage without load below 5.5V even at high temperatures. Output 2 Voltage The output 2 regulator uses the same output structure as the standby regulator but rated for the output current of 400mA. The output voltage is internally fixed to 5V if ADJ is connected to VOUT2. The output 2 regulator can be switches OFF via the enable input. Figure 2. OUT2 ADJ R2E R1i + 1.23V R1E RADJ R2i total 100K typical D94AT080 5/12 L4938E - L4938ED - L4938EPD Connecting a resistor divider R1E, R2E to the ADJ, OUT2 pin the output voltage 2 can be programmed to the value of R1E(R2E + RADJ) VOUT2 = VOUT1 1 + R2E ⋅ RADJ with RADJ = 60K to 150K and VOUT1 = 4.95 to 5.05V. For an exact calculation the temperature coefficient (Tc -2000pprm) of the internal resistor (RADJ) must be taken into account. Pin ADJ in this mode should not have a capacitive burden because this would reduce the phase margin of the regulator loop. Reset circuit The reset circuit supervises the standby output voltage. The reset output (RES) is defined from VOUT ≥ 1V. Even if VS is lacking, the reset generator is supplied by the output voltage V OUT1. The reset threshold of 4.7V is defined with the internal reference voltage (note 9) and standby output divider, when pin PR is left open. The reset threshold voltage can be programmed in the range from 3.8V to 4.7V by connecting an external resistor from pin PR to GND. The value of the programming resistor RPR can be calculated with: RPR = 22K − 92.9K,3.8V ≤ VRT ≤ 4.7V 4.7K −1 VRT The reset pulse delay time t RD, is defined with the charge time of an external capacitor CT: CT ⋅ 0.6V (note 5) tRDmin = 1µA tRDnom = CT ⋅ 1.4V (note 6) 1µA The reaction time of the reset circuit originates from the noise immunity. Standby output voltage drops below the reset threshold only a bit longer than the reaction time results in a shorter reset delay time. The nominal reset delay time will be generated for standby output voltage drops longer 6/12 than approximately 50µs. The minimum rset time is generated if reset condition only occures for a short time triggering a reset pulse but not completely discharging CT. The reset can be related to output2 on request. If higher charge currents for the reset capacitor are required a resistors from Pin CT to OUT1, may be used to increase the current. We recommended the use of 10KΩ to 5V as an output pull up. Sense Comparator The sense comparator compares an input signal with an internal voltage reference of typical 1.23V. The use of an external voltage divider makes this comparator very flexible in the application. It can be used to supervise the input voltage either before or after the protection diode and to give additional information to the microprocessor like low voltage warnings. We recommended the use of 10KΩ to 5V as an output pull up. Note 9: The reference is alternatively supplied from VS or VOUT1. If one supply is present, the reference is operating. Thermal Protection Both outputs are provided with an overtemperature shut down regulation power dissipation down to uncritical values. Output 2 will shut down approximately 10K before output 1. Under normal conditions shut down of output 2 will allow the chip to cool down again. Thus output 1 will be unaffected. The thermal shut down reduces the output voltages until power dissipation and the flow of thermal energy out of the chip balance. Transient Sensitivity In proper operation (VOUT > 4.5V) the reference is supplied by V OUT1 thus reducing sensitivity to input transients. Precise Data will be issued as soon as samples are available. L4938E - L4938ED - L4938EPD Figure 3. Reset Generator OUT1 REF 1.23V 10...100K 1µA 17K RES 74K - PR + VOUT1 Low threshold VBE at 1µA=0.5V at 25°C REG High threshold =1.4 CT CT D94AT081 Figure 4: 7/12 L4938E - L4938ED - L4938EPD INPUT PROTECTION The Inputs Enable (EN) and sense in(SI) are proFigure 5. Input Characteristics of SI, EN: 8/12 tected against negative transients. Figure 5 is showing the simplified schematic L4938E - L4938ED - L4938EPD mm DIM. MIN. a1 0.51 B 0.85 b b1 TYP. inch MAX. MIN. TYP. MAX. 0.020 1.40 0.033 0.50 0.38 0.055 0.020 0.50 D 0.015 0.020 20.0 0.787 E 8.80 0.346 e 2.54 0.100 e3 17.78 0.700 F 7.10 0.280 I 5.10 0.201 L Z OUTLINE AND MECHANICAL DATA 3.30 0.130 1.27 Powerdip 16 0.050 9/12 L4938E - L4938ED - L4938EPD mm DIM. MIN. TYP. inch MAX. MIN. TYP. MAX. A 2.35 2.65 0.093 0.104 A1 0.1 0.3 0.004 0.012 B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.6 13 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 OUTLINE AND MECHANICAL DATA 0.050 H 10 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 SO20 K 0° (min.)8° (max.) L h x 45° A B e A1 K H D 20 11 E 1 0 1 SO20MEC 10/12 C L4938E - L4938ED - L4938EPD DIM. A a1 a2 a3 b c D (1) D1 E e e3 E1 (1) E2 E3 G H h L N S T MIN. mm TYP. 0.1 0 0.4 0.23 15.8 9.4 13.9 MAX. 3.6 0.3 3.3 0.1 0.53 0.32 16 9.8 14.5 MIN. 0.004 0.000 0.016 0.009 0.622 0.370 0.547 1.27 11.43 10.9 inch TYP. 0.050 0.450 11.1 0.429 2.9 6.2 0.228 0.1 0.000 15.9 0.610 1.1 1.1 0.031 10° (max.) 8° (max.) 5.8 0 15.5 0.8 OUTLINE AND MECHANICAL DATA MAX. 0.142 0.012 0.130 0.004 0.021 0.013 0.630 0.386 0.570 10 0.437 0.114 0.244 0.004 0.626 0.043 0.043 JEDEC MO-166 0.394 PowerSO20 (1) ”D and F” do not include mold flash or protrusions. - Mold flash or protrusions shall not exceed 0.15 mm (0.006”). - Critical dimensions: ”E”, ”G” and ”a3” N R N a2 b A e DETAIL A c a1 DETAIL B E e3 H DETAIL A lead D slug a3 DETAIL B 20 11 0.35 Gage Plane -C- S SEATING PLANE L G E2 E1 BOTTOM VIEW C (COPLANARITY) T E3 1 h x 45 10 PSO20MEC D1 11/12 L4938E - L4938ED - L4938EPD Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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