ICST ICS853054AG 4:1, differential-to-3.3v or 2.5v lvpecl/ecl clock multiplexer Datasheet

PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
GENERAL DESCRIPTION
FEATURES
The ICS853054 is an 4:1 Differential-to-3.3V or
2.5V LVPECL/ECL Clock Multiplexer which
HiPerClockS™
can operate up to 2.5GHz and is a member of
the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853054 has 4
selectable differential clock inputs. The PCLKx, nPCLKx input pairs can accept LVPECL, LVDS, CML or SSTL levels.
The fully differential architecture and low propagation
delay make it ideal for use in clock distribution circuits. The
select pins have internal pulldown resistors. The SEL1 pin is
the most significant bit and the binary number applied to the
select pins will select the same numbered data input (i.e., 00
selects PCLK0, nPCLK0).
• High speed 4:1 differential multiplexer
ICS
• One differential 3.3V or 2.5V LVPECL output
• Four selectable differential PCLK, nPCLK inputs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 3.2GHz
• Translates any single ended input signal to
LVPECL levels with resistor bias on nPCLKx input
• Part-to-part skew: TBD
• Propagation delay: 465ps (typical)
• Additive phase jitter, RMS: 0.238ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
PCLK0
nPCLK0
00
PCLK1
nPCLK1
01
PCLK2
nPCLK2
10
PCLK3
nPCLK3
PCLK0
nPCLK0
PCLK1
nPCLK1
VCC
SEL0
SEL1
VEE
Q
nQ
16
15
14
13
12
11
10
9
VCC
Q
nQ
VEE
nPCLK3
PCLK3
nPCLK2
PCLK2
ICS853054
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm package body
G Package
Top View
11
SEL1
1
2
3
4
5
6
7
8
SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
853054AG
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REV. A JANUARY 5, 2006
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
PCLK0
Type
Input
2
nPCLK0
Input
3
PCLK1
Input
4
nPCLK1
Input
5, 16
VCC
Power
6, 7
SEL0, SEL1
Input
8, 13
VEE
Power
9
PCLK2
10
11
Description
Pulldown
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
Pullup/Pulldown
VCC/2 default when left floating.
Pulldown
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
Pullup/Pulldown
VCC/2 default when left floating.
Positive supply pins.
Pulldown
Clock select input pins. LVCMOS/LVTTL interface levels.
Input
Pulldown
Non-inver ting differential LVPECL clock input.
nPCLK2
Input
Pullup/Pulldown
PCLK3
Input
Pulldown
12
nPCLK3
Input
14, 15
nQ, Q
Output
Negative supply pin.
Inver ting differential LVPECL clock input.
VCC/2 default when left floating.
Non-inver ting differential LVPECL clock input.
Inver ting differential LVPECL clock input.
Pullup/Pulldown
VCC/2 default when left floating.
Differential output pair. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
RPULLDOWN
Input Pulldown Resistor
Test Conditions
Minimum Typical
75
Maximum
Units
kΩ
RVDD/2
Pullup/Pulldown Resistosr
50
kΩ
TABLE 3. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
SEL1
SEL0
Q/nQ
0
0
PCLK0/nPCLK0
0
1
PCLK1/nPCLK1
1
0
PCLK2/nPCLK2
1
1
PCLK3/nPCLK3
853054AG
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REV. A JANUARY 5, 2006
PRELIMINARY
Integrated
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ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
Inputs, VI (LVPECL mode)
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage
-4.6V (ECL mode, VCC = 0)
to the device. These ratings are stress specifi-0.5V to V + 0.5V
Inputs, VI (ECL mode)
0.5V to VEE - 0.5V
Supply Voltage, VCC
Negative Supply Voltage, VEE
CC
Outputs, IO
Continuous Current
Surge Current
cations only. Functional operation of product at
these conditions or any conditions beyond those
50mA
100mA
listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maxi-
Operating Temperature Range, TA -40°C to +85°C
Storage Temperature, TSTG
-65°C to 150°C
Package Thermal Impedance, θJA
89°C/W (0 lfpm)
mum rating conditions for extended periods may
affect product reliability.
(Junction-to-Ambient)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol
Parameter
VCC
Positive Supply Voltage
Test Conditions
ICC
Power Supply Current
Minimum
Typical
Maximum
Units
2.375
3.3
3.465
V
61
mA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
Test Conditions
IIH
Input High Current
SEL0, SEL1
IIL
Input Low Current
SEL0, SEL1
Minimum
Typical
Maximum
Units
VCC = 3.3V
2
VCC + 0.3
V
VCC = 2.5V
1.7
VCC + 0.3
V
VCC = 3.3V
-0.3
0.8
V
VCC = 2.5V
-0.3
0.7
V
150
µA
VCC = VIN = 3.465V,
VCC = VIN = 2.625V
VCC = 3.465V, VIN = 0V,
VCC = 2.625V, VIN = 0V
-150
µA
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = 2.375 TO 3.465V; VEE = 0V
Symbol Parameter
Test Conditions
Typical
Units
150
µA
-10
µA
nPCLK0:nPCLK3
VCC = 3.465V, VIN = 0V
-150
µA
0.15
V
Input High Current
IIL
Input Low Current
VPP
VOH
Peak-to-Peak Input Voltage
Common Mode Input Voltage;
NOTE 1, 2
Output High Voltage Voltage; NOTE 3
VOL
Output Low Voltage; NOTE 3
VCC = VIN = 3.465V
1.2
3.3
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3
V
VCC - 1.005
V
VCC - 1.78
V
VSWING
Peak-to-Peak Output Voltage Swing
0.8
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
853054AG
Maximum
VCC = 3.465V, VIN = 0V
IIH
VCMR
Minimum
PCLK0:PCLK3
nPCLK0:nPCLK3
PCLK0:PCLK3
V
REV. A JANUARY 5, 2006
PRELIMINARY
Integrated
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Systems, Inc.
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TABLE 4D. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VOH
Output High Voltage; NOTE 1
-1.005
V
VOL
Output Low Voltage; NOTE 1
-1.78
V
VIH
Input High Voltage
-1.225
-0.94
V
VIL
Input Low Voltage
-1.87
-1.535
V
VPP
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 2, 3
Input
PCLK0:PCLK3
High Current nPCLK0:nPCLK3
PCLK0:PCLK3
Input Low
Current
nPCLK0:nPCLK3
VCMR
IIH
IIL
800
VEE + 1.2
mV
0
V
150
µA
-10
µA
-150
µA
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
NOTE 2: Common mode voltage is defined as VIH.
NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, nPCLKx is VCC + 0.3V.
TABLE 5. AC CHARACTERISTICS, VCC = 0V; VEE = -3.465V TO -2.375V OR VCC = 2.375 TO 3.465V; VEE = 0V
Symbol
Parameter
fMAX
tPD
Output Frequency
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
Propagation Delay; NOTE 1
tsk(pp)
Par t-to-Par t Skew; NOTE 2, 3
tR / tF
Output Rise/Fall Time
t jit
Test Conditions
155.52MHz,
12kHz - 20MHz
Minimum
Typical
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4
Units
3.2
GHz
0.238
ps
465
ps
TBD
ps
20% to 80%
200
VIN 1.6V to 2.4V,
MUXISOLATION MUX Isolation
-55
155.52MHz
All parameters measured up to 1.3GHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
853054AG
Maximum
ps
dB
REV. A JANUARY 5, 2006
PRELIMINARY
Integrated
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ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
Additive Phase Jitter, RMS
-20
@ 155.52MHz = <0.238ps typical
-30
-40
-50
SSB PHASE NOISE dBc/HZ
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
853054AG
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
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REV. A JANUARY 5, 2006
PRELIMINARY
Integrated
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ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
PARAMETER MEASUREMENT INFORMATION
2V
VCC
Qx
V CC
SCOPE
nPCLK0:3
LVPECL
V
Cross Points
PP
V
CMR
PCLK0:3
nQx
VEE
VEE
-1.465V to -0.375V
OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nPCLK0:3
nQx
PART 1
Qx
PCLK0:3
nQ
nQy
PART 2
Qy
Q
tPD
tsk(pp)
PROPAGATION DELAY
PART-TO-PART SKEW
80%
80%
VOD
Clock
Outputs
20%
20%
tR
tF
OUTPUT RISE/FALL TIME
853054AG
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REV. A JANUARY 5, 2006
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ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VCC/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VCC= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
SELECT PINS:
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resister can be used.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resister can be tied
from PCLK to ground.
853054AG
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REV. A JANUARY 5, 2006
PRELIMINARY
Integrated
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ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
LVPECL CLOCK INPUT INTERFACE
gested here are examples only. If the driver is from another
vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the
driver termination requirements.
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLK/nPCLK input driven
by the most common driver types. The input interfaces sug-
2.5V
3.3V
3.3V
3.3V
2.5V
3.3V
R1
50
CML
R3
120
R2
50
SSTL
Zo = 50 Ohm
R4
120
Zo = 60 Ohm
PCLK
PCLK
Zo = 60 Ohm
Zo = 50 Ohm
nPCLK
nPCLK
HiPerClockS
PCLK/nPCLK
R1
120
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A CML DRIVER
HiPerClockS
PCLK/nPCLK
R2
120
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL IN DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
Zo = 50 Ohm
Zo = 50 Ohm
C1
LVDS
R3
1K
R4
1K
PCLK
PCLK
R5
100
Zo = 50 Ohm
nPCLK
LVPECL
R1
84
C2
nPCLK
Zo = 50 Ohm
HiPerClockS
Input
R1
1K
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
HiPerClockS
PCL K/n PC LK
R2
1K
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
3.3V
3.3V
3.3V
3.3V LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
84
R4
84
PCLK
nPCLK
R5
100 - 200
R6
100 - 200
R1
125
HiPerClockS
PCLK/nPCLK
R2
125
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
853054AG
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TERMINATION
FOR
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
3.3V LVPECL OUTPUTS
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different
layouts which are recommended only as guidelines. Other
suitable clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compatibility
across all printed circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
FOUT
50Ω
1
RTT =
Z
((VOH + VOL) / (VCC – 2)) – 2 o
FIN
50Ω
Zo = 50Ω
VCC - 2V
RTT
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
853054AG
125Ω
84Ω
FIGURE 3B. LVPECL OUTPUT TERMINATION
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TERMINATION
FOR
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for
2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
close to ground level. The R3 in Figure 4B can be eliminated
and the termination is shown in Figure 4C.
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
R1
250
Zo = 50 Ohm
R3
250
+
Zo = 50 Ohm
+
Zo = 50 Ohm
-
Zo = 50 Ohm
2,5V LVPECL
Driv er
-
R1
50
2,5V LVPECL
Driv er
R2
62.5
R2
50
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
853054AG
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ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS853054.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS853054 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V ± 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 61mA = 211.37mW
Power (outputs)MAX = 27.83mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 211.37mW + 27.83mW = 239.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 meters per second and a multi-layer board, the appropriate value is 81.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.239W * 81.8°C/W = 104.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA
FOR
16-PIN TSSOP FORCED CONVECTION
θJA by Velocity (Meters per Second)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
853054AG
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4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
For logic high, VOUT = V
OH_MAX
(V
CC_MAX
•
-V
OH_MAX
OL_MAX
CC_MAX
-V
OL_MAX
CC_MAX
– 1.005V
) = 1.005
For logic low, VOUT = V
(V
=V
=V
CC_MAX
– 1.78V
) = 1.78V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R ] * (V
CC_MAX
L
-V
OH_MAX
) = [(2V - (V
CC_MAX
-V
OH_MAX
))/R ] * (V
CC_MAX
L
-V
OH_MAX
)=
[(2V - 1.005V)/50Ω] * 1.005V = 20mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R ] * (V
L
CC_MAX
-V
OL_MAX
) = [(2V - (V
CC_MAX
-V
OL_MAX
))/R ] * (V
L
CC_MAX
-V
OL_MAX
)=
[(2V - 1.78V)/50Ω] * 1.78V = 7.83mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 27.83mW
853054AG
www.icst.com/products/hiperclocks.html
12
REV. A JANUARY 5, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
RELIABILITY INFORMATION
TABLE 7.
θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
137.1°C/W
89.0°C/W
118.2°C/W
81.8°C/W
106.8°C/W
78.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS853054 is: 326
853054AG
www.icst.com/products/hiperclocks.html
13
REV. A JANUARY 5, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
FOR
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
N
Maximum
16
A
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
4.90
E
E1
5.10
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
α
0°
8°
aaa
--
0.10
0.75
Reference Document: JEDEC Publication 95, MO-153
853054AG
www.icst.com/products/hiperclocks.html
14
REV. A JANUARY 5, 2006
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS853054
4:1, DIFFERENTIAL-TO-3.3V OR 2.5V
LVPECL/ECL CLOCK MULTIPLEXER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging Temperature
ICS853054AG
853054AG
16 Lead TSSOP
tube
-40°C to 85°C
ICS853054AGT
853054AG
16 Lead TSSOP
2500 tape & reel
-40°C to 85°C
ICS853054AGLF
853054AL
16 Lead "Lead-Free" TSSOP
tube
-40°C to 85°C
ICS853054AGLFT
853054AL
16 Lead "Lead-Free" TSSOP
2500 tape & reel
-40°C to 85°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
853054AG
www.icst.com/products/hiperclocks.html
15
REV. A JANUARY 5, 2006
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