DA9178.001 10 Dec, 2003 MAS9178 AM Receiver IC • • • • • • • High Sensitivity Very Low Power Consumption Wide Supply Voltage Range Power Down Control Control for AGC On High Selectivity by Crystal Filter Fast Startup Feature DESCRIPTION The MAS9178 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiver. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. Unlike MAS1016A and MAS1016B, MAS9178 does not require AGC control procedure in WWVB and JJY systems. FEATURES APPLICATIONS • • • • • • • • • MAS9178A1 has differential input and internal 0.875 pF compensation capacitor for crystal shunt capacitance compensation. MAS9178A5 requires external compensation capacitor for crystal shunt capacitance compensation. It can be used with crystals that do not match with fixed 0.875 pF compensation capacitance of MAS9178A1. Highly Sensitive AM Receiver, 0.4 µVRMS typ. Wide Supply Voltage Range from 1.1 V to 3.6 V Very Low Power Consumption Power Down Control Fast Startup Only a Few External Components Necessary Control for AGC On Wide Frequency Range from 40 kHz to 100 kHz High Selectivity by Quartz Crystal Filter • • Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany) and MSF (UK) Receiver for ASK Modulated Data Signals BLOCK DIAGRAM QOP QI AON QOM RFP AGC Amplifier RFM Demodulator & Comparator OUT Power Supply/Biasing VDD VSS PDN AGC DEC 1 (8) DA9178.001 10 Dec, 2003 PAD LAYOUT 1906 µm VSS RFM RFP PDN AON DEC 9178 A1 1778 µm VDD QOP QI QOM AGC OUT DIE size = 1.91 x 1.78 mm; PAD size = 100 x 100 µm except for VSS PAD size 104 x 112 µm Note: Because the substrate of the die is internally connected to VDD, the die has to be connected to VDD or left floating. Please make sure that VDD is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in the center of VDD pad Pad Identification Name X-coordinate Y-coordinate Power Supply Voltage Quartz Filter Output for Crystal Quartz Filter Input for Crystal and External Compensation Capacitor Quartz Filter Output for External Compensation Capacitor AGC Capacitor Receiver Output Demodulator Capacitor AGC On Control Power Down Input Positive Receiver Input Negative Receiver Input Power Supply Ground VDD QOP QI 0 µm 306 µm 549 µm 0 µm 19 µm 19 µm QOM 866 µm 19 µm AGC OUT DEC AON PDN RFP RFM VSS 1146 µm 1389 µm 1389 µm 1146 µm 829 µm 586 µm 269 µm 16 µm 19 µm 19 µm 1428 µm 1428 µm 1428 µm 1428 µm 1428 µm 1407 µm Note 1 2 3 Notes: 1) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 2) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 3) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 2 (8) DA9178.001 10 Dec, 2003 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature VDD-VSS VIN PMAX TOP TST Conditions Min Max Unit -0.3 VSS-0.3 5.0 VDD+0.3 100 70 120 V V mW o C o C -20 -40 ELECTRICAL CHARACTERISTICS Operating Conditions: VDD = 1.4V, Temperature = 25°C Parameter Operating Voltage Current Consumption Stand-By Current Input Frequency Range Minimum Input Voltage Maximum Input Voltage Input Levels |lIN|<0.5 µA Output Current VOL<0.2 VDD;VOH >0.8 VDD Output Pulse Symbol VDD IDD Conditions VDD=3.6 V, Vin=0 µV VDD=1.4 V, Vin=0 µV IDDoff fIN VIN min VIN max VIL VIH |IOUT| T100ms T200ms T500ms T800ms Startup Time TStart Output Delay Time TDelay Min 1.10 56 Typ 76 66 40 0.4 Max Unit 3.60 95 µA 0.1 100 1 20 0.2 VDD 0.8 VDD 5 1 µVrms ≤ VIN ≤ 20 mVrms 1 µVrms ≤ VIN ≤ 20 mVrms 1 µVrms ≤ VIN ≤ 20 mVrms 1 µVrms ≤ VIN ≤ 20 mVrms Fast Start-up Without Fast Start-up V µA kHz µVrms mVrms V µA 50 140 ms 150 230 ms 400 500 600 ms 700 800 900 ms 100 s min ms 12 3 50 3 (8) DA9178.001 10 Dec, 2003 TYPICAL APPLICATION Note 4 Optional Control for AGC on/hold Note 1 QOP QI RFP Ferrite Antenna AON QOM Demodulator & Comparator AGC Amplifier RFM OUT Receiver Output Power Supply/Biasing VDD VSS AGC PDN CAGC + 10 µF 1.4 V Figure 1 CDEC 47 nF Note 2 Note 3 Power Down / Fast Startup Control Application circuit of internal compensation capacitance version MAS9178A1. Note 1 QOP CC_EXT=C0 QI Note 4 Optional Control for AGC on/hold AON QOM RFP Ferrite Antenna DEC AGC Amplifier RFM Demodulator & Comparator OUT Receiver Output Power Supply/Biasing VDD 1.4 V Figure 2 VSS PDN AGC CAGC + 10 µF DEC CDEC 47 nF Note 3 Note 2 Power Down / Fast Startup Control Application circuit of external compensation capacitance version MAS9178A5. 4 (8) DA9178.001 10 Dec, 2003 TYPICAL APPLICATION (Continued) Note 1 QOP Note 4 Optional Control for AGC on/hold QI AON QOM RFP Ferrite Antenna AGC Amplifier RFM Antenna Frequency Selection OUT Receiver Output Power Supply/Biasing VDD VSS PDN AGC CAGC + 10 µF 1.4 V Figure 3 Demodulator & Comparator DEC CDEC 47 nF Note 3 Note 2 Power Down / Fast Startup Control Dual band application circuit of external compensation capacitance version MAS9178A5. Note 1: Crystal The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). The crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance compensation capacitor CC=0.875 pF of MAS9178A1. External compensation pad QOM is unconnected in MAS9178A1. MAS9178A5 does not have internal compensation capacitance CC and it requires use of external compensation capacitor CC_EXT. It must be connected between pins QOM and QI (see figure 2). CC_EXT should have equal value with crystal’s effective shunt capacitance C0. External compensation version MAS9178A5 should be used when fixed 0.875 pF compensation capacitance of MAS9178A1 does not match well with used crystal’s shunt capacitance. It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of floating crystal shunt capacitance. PCB traces of crystal and external compensation capacitance should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance mismatching. In dual band receiver configuration the crystals can be connected in parallel thus external compensation capacitor value CC_EXT must be sum of two crystals’ shunt capacitances. Instead of parallel crystal connection it is also possible to connect other crystal from QOP pin and the other crystal from QOM pin to common QI pin (figure 3). In this circuit configuration no external compensation capacitor is required since the crystals compensate each other. The sensitivity of dual band receiver configuration will be lower than that of single band receiver configuration since the noise band width of crystal filter with two parallel crystals is double. Time-Signal System DCF77 MSF WWVB JJY Table 1 Location Antenna Frequency Germany 77.5 kHz United Kingdom 60 kHz USA 60 kHz Japan 40 kHz and 60 kHz Time-Signal System Frequencies Recommended Crystal Frequency 77.503 kHz 60.003 kHz 60.003 kHz 40.003 kHz and 60.003 kHz 5 (8) DA9178.001 10 Dec, 2003 TYPICAL APPLICATION (Continued) Note 2: AGC Capacitor The AGC and DEC capacitors must have low leakage currents due to very small 40 nA signal currents through the capacitors. The insulation resistance of these capacitors should be higher than 70 MΩ. Also probes with at least 100 MΩ impedance should be used for voltage probing of AGC and DEC pins. Electrolyte capacitors cannot be used due to their large leakage current. Instead low leakage tantalum capacitor can be used as AGC capacitor. DEC capacitor can be low leakage chip capacitor. Note 3: Power Down / Fast Startup Control Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if PDN = VDD and in power up (turned on) if PDN = VSS. Fast startup is triggered by the falling edge of PDN signal, i.e., controlling device from power down to power up. The startup time without using the fast startup control can be several minutes but with fast startup it is shortened typically to 12 s. Note 4: Optional Control for AGC On/Hold AON control pin has internal pull up which turns AGC circuit on all the time if AON pin is left unconnected. Optionally AON control can be used to hold and release AGC circuit. Stepper motor drive etc. can produce disturbing amount of noise which can shift the input amplifier gain to unoptimal level. This can be avoided by controlling AGC hold (AON=VSS) during stepper motor drive periods and releasing AGC (AON=VDD) when motors are not driven. 6 (8) DA9178.001 10 Dec, 2003 SAMPLES IN SBDIL 20 PACKAGE VDD 1 20 VSS NC 2 19 NC 18 RFM QOP 3 NC 6 QOM 7 NC 8 17 RFP 9178Ax YYWW XXXXX.X NC 4 QI 5 16 NC 15 PDN 14 AON 13 DEC AGC 9 12 NC 11 OUT NC 10 Top Marking Definitions: YYWW = Year Week XXXXX.X = Lot Number x =1, 5 Sample Version Number PIN DESCRIPTION Pin Name Pin Type VDD NC QOP NC QI 1 2 3 4 5 P NC QOM 6 7 NC AGC NC OUT NC DEC AON PDN NC RFP RFM NC VSS 8 9 10 11 12 13 14 15 16 17 18 19 20 Function Note Positive Power Supply AO Quartz Filter Output for Crystal AI Quartz Filter Input for Crystal and External Compensation Capacitor AO Quartz Filter Output for External Compensation Capacitor AO AGC Capacitor DO Receiver Output 2 AO DI AI Demodulator Capacitor AGC On Control Power Down Input 3 4 AI AI Positive Receiver Input Negative Receiver Input 1 1 G Power Supply Ground Notes: 1) Pins 4 and 6 around quartz crystal filter input pins must be connected to VSS to eliminate DIL package leadframe parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) pins are also recommended to be connected to VSS to minimize noise coupling. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 µA - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 µA which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 7 (8) DA9178.001 10 Dec, 2003 SAMPLE INFORMATION Product Code Product Description Capacitance Option MAS9178A1TB00.01 AM-Receiver IC with Differential Input AM-Receiver IC with Differential Input EWS-tested wafer, Thickness 480 µm. EWS-tested wafer, Thickness 480 µm. CC = 0.875 pF AM-Receiver IC with Differential Input AM-Receiver IC with Differential Input EWS-tested wafer, Thickness 400 µm. EWS-tested wafer, Thickness 400 µm. MAS9178A5TB00.01 MAS9178A1TC00.01 MAS9178A5TC00.01 External Compensation Capacitor CC = 0.875 pF External Compensation Capacitor LOCAL DISTRIBUTOR MICRO ANALOG SYSTEMS OY CONTACTS Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 8 (8)