ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER GENERAL DESCRIPTION FEATURES The ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high HiPerClockS™ performance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to both of two outputs. This device may be useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit and 1000Mbit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. Another mode allows loop back testing and allows the output of a PHY transmit pair to be routed to the PHY input pair. For examples, please refer to the Application Information section of the data sheet. • Dual 2:1/1:2 MUX The ICS85454-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards. • 2.5V operating supply ICS • Three LVDS outputs • Three differential inputs • Differential inputs can accept the following differential levels: LVPECL, LVDS, CML • Loopback test mode available • Maximum output frequency: 2.5GHz • Part-to-part skew: 250ps (maximum) • Additive phase jitter, RMS: 0.05ps (typical) • Propagation delay: 550ps (maximum) • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages BLOCK DIAGRAM PIN ASSIGNMENT INA0 nQA0 0 1 VDD SELA 11 nINA0 QA1 3 10 INA1 nQA1 4 9 5 6 7 INA0 nINA1 8 GND QA0 nQA0 2 nINB 0 16 15 14 13 12 SELB LOOP0 INB nINB QA0 1 INB nINA0 nQB QB SELB QB nQB 1 INA1 ICS85454-01 nINA1 16-Lead VFQFN 3mm x 3mm x 0.95 package body K Package Top View LOOP1 QA1 nQA1 SELA 85454AK-01 www.icst.com/products/hiperclocks.html 1 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 QA0, nQA0 Output Differential output pair. LVDS interface levels. 3, 4 QA1, nQA1 Output Differential output pair. LVDS interface levels. 5 INB Input 6 nINB Input 7 SEL B Input 8 GND Power 9 nINA1 Input 10 INA1 Input 11 nINA0 Input 12 INA0 Input 13 VDD Power Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Select pin for QAx outputs. When HIGH, selects same inputs used for Pulldown QB output. When LOW, selects INB input. LVCMOS/LVTTL interface levels. Power supply ground. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. VDD/2 default when left floating. Pulldown Pulldown Non-inver ting differential clock input. Positive supply pin. Select pin for QB outputs. When HIGH, selects INA1 input. 14 SELA Input Pulldown When LOW, selects INA0 input. LVCMOS/LVTTL interface levels. 15, 16 nQB, QB Output Differential output pair. LVDS interface levels. NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLDOWN Input Pulldown Resistor Test Conditions Minimum Typical 37.5 Maximum Units kΩ RPULLUP Input Pullup Resistor 37.5 kΩ TABLE 3. INPUT CONTROL FUNCTION TABLE Control Inputs SELA SELB 0 0 Mode LOOP0 selected 1 0 LOOP1 selected 0 1 Loopback mode: LOOP0 1 1 Loopback mode: LOOP1 85454AK-01 www.icst.com/products/hiperclocks.html 2 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER ABSOLUTE MAXIMUM RATINGS NOTE: Stresses beyond those listed under Absolute Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current Maximum Ratings may cause permanent damage t o the device. These ratings are stress specifi- 10mA 15mA cations only. Functional operation of product at these conditions or any conditions beyond those Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 51.5°C/W (0 lfpm) listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 5% Symbol Parameter VDD Positive Supply Voltage Test Conditions IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 90 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 2.5V ± 5% Symbol Parameter Maximum Units VIH Input High Voltage Test Conditions Minimum 1.7 VDD + 0.3 V VIL Input Low Voltage 0 0.7 V IIH Input High Current SELA, SELB VDD = VIN = 2.625V IIL Input Low Current SELA, SELB VDD = 2.625V, VIN = 0V Typical 150 -150 µA µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V ± 5% Symbol Parameter Min -40°C Typ Max Min 25°C Typ Max Min 85°C Typ Max INAx, INB 150 150 150 nINAx, nINB INAx, INB IIL Input Low Current -150 -150 -150 nINAx, nINB VPP Peak-to-Peak Input Voltage 0.15 1.2 0.15 1.2 0.15 1.2 Commond Mode Input Voltage; VCMR 1.2 VDD 1.2 VDD 1.2 VDD NOTE 1, 2 NOTE 1: Common mode input voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for INAx, nINAx and INB, nINB is VDD + 0.3V. IIH 85454AK-01 Input High Current www.icst.com/products/hiperclocks.html 3 Units µA µA V V REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V ± 5% Symbol Parameter VOD Differential Output Voltage ∆ VOD VOD Magnitude Change VOS Offset Voltage ∆ VOS VOS Magnitude Change -40°C 25°C 85°C Units Min Typ Max Min Typ Max Min Typ Max 25 0 350 450 250 350 450 250 350 450 mV 30 mV 30 0.93 1.18 1.43 30 0.97 1.22 10 1.47 1.02 1.27 10 1.52 V 10 mV NOTE 1: Refer to Parameter Measurement Information, "2.5V Output Load Test Circuit" diagram. TABLE 5. AC CHARACTERISTICS, VDD = 2.375V TO 2.625V Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(pp) M U X ISOLATION Par t-to-Par t Skew; NOTE 2, 3 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section MUX Isolation tR/tF Output Rise/Fall Time tjit Conditions Minimum INAx to QB or INB to QAx 250 INAx to QAx 300 ƒ = 622.08MHz, 12kHz - 20MHz @ 500MHz output 20% to 80% Typical Maximum Units 2.5 GHz 550 ps 650 ps 250 ps 0.05 ps 55 50 dB 250 ps All parameters are measured ≤ 1.7GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 85454AK-01 www.icst.com/products/hiperclocks.html 4 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER ADDITIVE PHASE JITTER ratio of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a 0 -10 Additive Phase Jitter at 622.08MHz (12kHz - 20MHz) = 0.05ps (typical) -20 -30 -40 SSB PHASE NOISE dBc/HZ -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1M 10M 100M OFFSET FROM CARRIER FREQUENCY (HZ) above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated 85454AK-01 www.icst.com/products/hiperclocks.html 5 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER PARAMETER MEASUREMENT INFORMATION VDD Qx nINA0, nINA1 nINB SCOPE V 2.5V±5% POWER SUPPLY V Cross Points PP LVDS + Float GND - CMR INA0, INA1 INB nQx GND OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nINA0, nINA1 nINB nQx PART 1 Qx INA0, INA1 INB nQA0, nQA1, nQB QA0, QA1, QB nQy PART 2 Qy t sk(pp) tPD PROPAGATION DELAY PART-TO-PART SKEW VDD ➤ 80% LVDS 100 VOD/∆ VOD 20% 20% tR out tF OUTPUT RISE/FALL TIME ➤ DC Input VSW I N G Clock Outputs ➤ out 80% DIFFERENTIAL OUTPUT VOLTAGE VDD out LVDS ➤ DC Input ➤ out VOS/∆ VOS ➤ OFFSET VOLTAGE SETUP 85454AK-01 www.icst.com/products/hiperclocks.html 6 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. VDD R1 1K Single Ended Clock Input IN V_REF nIN C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: IN/nIN INPUT: For applications not requiring the use of the differential input, both IN and nIN can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from IN to ground. LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, we recommend that there is no trace attached. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 85454AK-01 www.icst.com/products/hiperclocks.html 7 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER DIFFERENTIAL CLOCK INPUT INTERFACE are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. The IN/nIN accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2D show interface examples for the HiPerClockS IN/nIN input driven by the most common driver types. The input interfaces suggested here 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm IN IN R1 100 Zo = 50 Ohm nIN FIGURE 2B. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V Zo = 50 Ohm Zo = 50 Ohm IN IN R1 100 Zo = 50 Ohm LVDS R1 100 nIN Zo = 50 Ohm nIN HiPerClockS LVDS HiPerClockS FIGURE 2C. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A 3.3V LVPECL DRIVER 85454AK-01 HiPerClockS CML Built-In Pull-Up FIGURE 2A. HIPERCLOCKS IN/nIN INPUT DRIVEN BY AN OPEN COLLECTOR CML DRIVER 3.3V nIN Zo = 50 Ohm HiPerClockS FIGURE 2D. HIPERCLOCKS IN/nIN INPUT DRIVEN BY A 3.3V LVDS DRIVER www.icst.com/products/hiperclocks.html 8 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER TYPICAL APPLICATION DIAGRAM FOR HOST BUS ADAPTER BOARDS FOR ROUTING BETWEEN INTERNAL AND EXTERNAL CONNECTORS Internal Connector Host Adapter Board SELB INA0 INB 0 nINB Protocol Controller SerDes QA0 nQA0 0 QB nQB 1 INA1 1 External Connector nINA0 nINA1 QA1 nQA1 SELA PCI Bus 85454AK-01 www.icst.com/products/hiperclocks.html 9 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER TYPICAL APPLICATION DIAGRAM FOR HOT-SWAPPABLE LINKS TO REDUNDANT SWITCH FABRIC CARDS LOOP 0 SELB INA0 nINA0 TX SerDes INB nINB 0 QB 0 QA0 1 nQA0 nQB Switch Fabric INA1 1 nINA1 RX QA1 nQA1 #0 SELA LOOP 1 #1 Redundant Switch Card Linecard Backplane 2.5V LVDS DRIVER TERMINATION transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs. Figure 3 shows a typical termination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Line ΩDifferential 100Ω Differential Transmission Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION 85454AK-01 www.icst.com/products/hiperclocks.html 10 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85454-01. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85454-01 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. · Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 90mA = 236.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow of and a multi-layer board, the appropriate value is 51.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.236W * 51.5°C/W = 97.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θ JA FOR 16-PIN VFQFN, FORCED CONVECTION θJA vs. 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 85454AK-01 51.5°C/W www.icst.com/products/hiperclocks.html 11 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD VFQFN θJA vs. 0 Air Flow (Linear Feet per Minute) 0 Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W TRANSISTOR COUNT The transistor count for ICS85454-01 is: 171 85454AK-01 www.icst.com/products/hiperclocks.html 12 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - K SUFFIX FOR DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER 16 LEAD VFQFN TABLE 8. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM MAXIMUM 16 N A 0.80 1.0 A1 0 0.05 0.25 Reference A3 b 0.18 0.30 e 0.50 BASIC ND 4 NE 4 3.0 D D2 1.0 1.8 3.0 E E2 1.0 1.8 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 85454AK-01 www.icst.com/products/hiperclocks.html 13 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS85454AK-01 5A01 16 Lead VFQFN Tube -40°C to 85°C ICS85454AK-01T 5A01 16 Lead VFQFN 2500 Tape & Reel -40°C to 85°C ICS85454AK-01LF A01L 16 Lead "Lead-Free" VFQFN Tube -40°C to 85°C ICS85454AK-01LFT A01L 16 Lead "Lead-Free" VFQFN 2500 Tape & Reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85454AK-01 www.icst.com/products/hiperclocks.html 14 REV. B JUNE 16, 2006 ICS85454-01 Integrated Circuit Systems, Inc. DUAL 2:1/1:2 DIFFERENTIAL-TO-LVDS MULTIPLEXER REVISION HISTORY SHEET Rev Table T4D Page 4 T9 14 T8 13 B B 85454AK-01 Description of Change LVDS DC Characteristics - changed VOD parameters. Changed ∆ VOD/VOS parameters from typical to maximum. Ordering Information - corrected Shipping Packaging from Tray to Tube. Package Dimension Table - corrected D2/E2 from 0.25min/1.25max. to 1.0min./1.8max. www.icst.com/products/hiperclocks.html 15 Date 3/14/06 6/16/06 REV. B JUNE 16, 2006