QFET TM FQD7N10L / FQU7N10L 100V LOGIC N-Channel MOSFET General Description Features These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar stripe, DMOS technology. This advanced technology is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation modes. These devices are well suited for low voltage applications such as high efficiency switching DC/DC converters, and DC motor control. • • • • • • • 5.8A, 100V, RDS(on) = 0.35Ω @VGS = 10 V Low gate charge ( typical 4.6 nC) Low Crss ( typical 12 pF) Fast switching 100% avalanche tested Improved dv/dt capability Low level gate drive requirments allowing direct operation from logic drives D ! D " ! " " " G! G S I-PAK D-PAK FQD Series G D S FQU Series ! S Absolute Maximum Ratings Symbol VDSS ID TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current FQD7N10L / FQU7N10L 100 Units V 5.8 A - Continuous (TC = 100°C) IDM Drain Current - Pulsed (Note 1) 3.67 A 23.2 A VGSS Gate-Source Voltage ± 20 V EAS Single Pulsed Avalanche Energy (Note 2) 50 mJ IAR Avalanche Current (Note 1) 5.8 A EAR Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) * (Note 1) 2.5 6.0 2.5 mJ V/ns W 25 0.2 -55 to +150 W W/°C °C 300 °C dv/dt PD (Note 3) Power Dissipation (TC = 25°C) TJ, TSTG TL - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8” from case for 5 seconds Thermal Characteristics Symbol RθJC Parameter Thermal Resistance, Junction-to-Case Typ -- Max 5.0 Units °C/W RθJA Thermal Resistance, Junction-to-Ambient * -- 50 °C/W RθJA Thermal Resistance, Junction-to-Ambient -- 110 °C/W * When mounted on the minimum pad size recommended (PCB Mount) ©2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD7N10L / FQU7N10L December 2000 Symbol TC = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units 100 -- -- V -- 0.1 -- V/°C Off Characteristics BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS / ∆TJ Breakdown Voltage Temperature Coefficient ID = 250 µA, Referenced to 25°C VDS = 100 V, VGS = 0 V -- -- 1 µA VDS = 80 V, TC = 125°C -- -- 10 µA Gate-Body Leakage Current, Forward VGS = 20 V, VDS = 0 V -- -- 100 nA Gate-Body Leakage Current, Reverse VGS = -20 V, VDS = 0 V -- -- -100 nA Gate Threshold Voltage VDS = VGS, ID = 250 µA 1.0 -- 2.0 V RDS(on) Static Drain-Source On-Resistance VGS = 10 V, ID = 2.9 A VGS = 5 V, ID = 2.9 A -- 0.275 0.300 0.35 0.38 Ω gFS Forward Transconductance VDS = 30 V, ID = 2.9 A -- 4.6 -- S -- 220 290 pF IDSS IGSSF IGSSR Zero Gate Voltage Drain Current On Characteristics VGS(th) (Note 4) Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance VDS = 25 V, VGS = 0 V, f = 1.0 MHz -- 55 72 pF -- 12 15 pF Switching Characteristics td(on) Turn-On Delay Time tr Turn-On Rise Time td(off) Turn-Off Delay Time tf Turn-Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = 50 V, ID = 7.3 A, RG = 25 Ω (Note 4, 5) VDS = 80 V, ID = 7.3 A, VGS = 5 V (Note 4, 5) -- 9 30 ns -- 100 210 ns -- 17 45 ns -- 50 110 ns -- 4.6 6.0 nC -- 1.0 -- nC -- 2.6 -- nC Drain-Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain-Source Diode Forward Current -- -- 5.8 A ISM -- -- 23.2 A VSD Maximum Pulsed Drain-Source Diode Forward Current VGS = 0 V, IS = 5.8 A Drain-Source Diode Forward Voltage -- -- 1.5 V trr Reverse Recovery Time -- 70 -- ns Qrr Reverse Recovery Charge VGS = 0 V, IS = 7.3 A, dIF / dt = 100 A/µs -- 140 -- nC (Note 4) Notes: 1. Repetitive Rating : Pulse width limited by maximum junction temperature 2. L = 2.23mH, IAS = 5.8A, VDD = 25V, RG = 25 Ω, Starting TJ = 25°C 3. ISD ≤ 7.3A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C 4. Pulse Test : Pulse width ≤ 300µs, Duty cycle ≤ 2% 5. Essentially independent of operating temperature ©2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD7N10L / FQU7N10L Electrical Characteristics FQD7N10L / FQU7N10L Typical Characteristics VGS 10.0 V 8.0 V 6.0 V 5.0 V 4.5 V 4.0 V 3.5 V Bottom : 3.0 V Top : ID, Drain Current [A] 1 10 ID , Drain Current [A] 1 10 0 10 150℃ 0 10 25℃ -55℃ ※ Notes : 1. VDS = 30V 2. 250μs Pulse Test ※ Notes : 1. 250μs Pulse Test 2. TC = 25℃ -1 -1 10 -1 0 10 10 1 10 0 10 2 4 6 8 10 VGS , Gate-Source Voltage [V] VDS, Drain-Source Voltage [V] Figure 1. On-Region Characteristics Figure 2. Transfer Characteristics 1.5 IDR , Reverse Drain Current [A] 1 1.2 RDS(ON) [Ω ], Drain-Source On-Resistance VGS = 5V 0.9 VGS = 10V 0.6 0.3 10 0 10 150℃ ※ Notes : 1. VGS = 0V 2. 250μs Pulse Test ※ Note : TJ = 25℃ -1 0.0 0 5 10 15 20 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VSD , Source-Drain Voltage [V] ID, Drain Current [A] Figure 3. On-Resistance Variation vs. Drain Current and Gate Voltage Figure 4. Body Diode Forward Voltage Variation vs. Source Current and Temperature 12 600 Ciss = Cgs + Cgd (Cds = shorted) Coss = Cds + Cgd Crss = Cgd 400 ※ Notes : 1. VGS = 0 V 2. f = 1 MHz Ciss 300 Coss 200 Crss 100 10 VGS, Gate-Source Voltage [V] 500 Capacitance [pF] 25℃ VDS = 50V 8 VDS = 80V 6 4 2 ※ Note : ID = 7.3 A 0 -1 10 0 0 10 1 10 VDS, Drain-Source Voltage [V] Figure 5. Capacitance Characteristics ©2000 Fairchild Semiconductor International 0 1 2 3 4 5 6 7 8 QG, Total Gate Charge [nC] Figure 6. Gate Charge Characteristics Rev. A2, December 2000 FQD7N10L / FQU7N10L Typical Characteristics (Continued) 3.0 1.2 RDS(ON) , (Normalized) Drain-Source On-Resistance BV DSS , (Normalized) Drain-Source Breakdown Voltage 2.5 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 μA 0.9 0.8 -100 -50 0 50 100 150 2.0 1.5 1.0 ※ Notes : 1. VGS = 5 V 2. ID = 2.9 A 0.5 0.0 -100 200 -50 o 50 100 150 200 o TJ, Junction Temperature [ C] Figure 7. Breakdown Voltage Variation vs. Temperature Figure 8. On-Resistance Variation vs. Temperature 2 6 10 Operation in This Area is Limited by R DS(on) 5 100 µs 1 10 ID, Drain Current [A] ID, Drain Current [A] 0 TJ, Junction Temperature [ C] 1 ms 10 ms DC 0 10 ※ Notes : o 1. TC = 25 C 4 3 2 1 o 2. TJ = 150 C 3. Single Pulse -1 10 0 1 10 0 25 2 10 10 50 θ JC ( t) , T h e r m a l R e s p o n s e Figure 9. Maximum Safe Operating Area Z 75 100 125 150 TC, Case Temperature [℃] VDS, Drain-Source Voltage [V] Figure 10. Maximum Drain Current vs. Case Temperature D = 0 .5 10 ※ N o te s : 1 . Z θ J C ( t ) = 5 . 0 ℃ /W M a x . 2 . D u ty F a c t o r , D = t 1 /t 2 3 . T J M - T C = P D M * Z θ J C( t ) 0 .2 0 0 .1 0 .0 5 PDM 0 .0 2 t1 0 .0 1 10 s in g le p u ls e -1 10 -5 10 -4 10 t2 -3 10 -2 10 -1 10 0 10 1 t 1 , S q u a r e W a v e P u ls e D u r a t io n [ s e c ] Figure 11. Transient Thermal Response Curve ©2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD7N10L / FQU7N10L Gate Charge Test Circuit & Waveform VGS Same Type as DUT 50KΩ Qg 200nF 12V 5V 300nF VDS VGS Qgs Qgd DUT 3mA Charge Resistive Switching Test Circuit & Waveforms VDS RL VDS 90% VDD VGS RG VGS DUT 5V 10% td(on) tr td(off) t on tf t off Unclamped Inductive Switching Test Circuit & Waveforms BVDSS 1 EAS = ---- L IAS2 -------------------2 BVDSS - VDD L VDS BVDSS IAS ID RG VDD DUT 10V tp ©2000 Fairchild Semiconductor International ID (t) VDS (t) VDD tp Time Rev. A2, December 2000 FQD7N10L / FQU7N10L Peak Diode Recovery dv/dt Test Circuit & Waveforms DUT + VDS _ I SD L Driver RG VGS VGS ( Driver ) Same Type as DUT VDD • dv/dt controlled by RG • ISD controlled by pulse period Gate Pulse Width D = -------------------------Gate Pulse Period 10V IFM , Body Diode Forward Current I SD ( DUT ) di/dt IRM Body Diode Reverse Current VDS ( DUT ) Body Diode Recovery dv/dt VSD VDD Body Diode Forward Voltage Drop ©2000 Fairchild Semiconductor International Rev. A2, December 2000 DPAK MIN0.55 0.91 ±0.10 9.50 ±0.30 0.50 ±0.10 0.76 ±0.10 0.50 ±0.10 1.02 ±0.20 2.30TYP [2.30±0.20] (1.00) (3.05) (2XR0.25) (0.10) 2.70 ±0.20 6.10 ±0.20 9.50 ±0.30 6.60 ±0.20 (5.34) (5.04) (1.50) (0.90) 2.30 ±0.20 (0.70) 2.30TYP [2.30±0.20] (0.50) 2.30 ±0.10 0.89 ±0.10 MAX0.96 (4.34) 2.70 ±0.20 0.80 ±0.20 0.60 ±0.20 (0.50) 6.10 ±0.20 5.34 ±0.30 0.70 ±0.20 6.60 ±0.20 0.76 ±0.10 ©2000 Fairchild Semiconductor International Rev. A2, December 2000 FQD7N10L / FQU7N10L Package Dimensions (Continued) IPAK 2.30 ±0.20 6.60 ±0.20 5.34 ±0.20 0.76 ±0.10 2.30TYP [2.30±0.20] ©2000 Fairchild Semiconductor International 0.50 ±0.10 16.10 ±0.30 6.10 ±0.20 0.70 ±0.20 (0.50) 9.30 ±0.30 MAX0.96 (4.34) 1.80 ±0.20 0.80 ±0.10 0.60 ±0.20 (0.50) 2.30TYP [2.30±0.20] 0.50 ±0.10 Rev. A2, December 2000 FQD7N10L / FQU7N10L Package Dimensions TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ E2CMOS™ FACT™ FACT Quiet Series™ FAST® FASTr™ GTO™ HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench® QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR INTERNATIONAL. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. ©2000 Fairchild Semiconductor International Rev. A, January 2000