Micrel DSC400-2112Q0001KI1T Configurable four output, low jitter crystal-lessâ ¢ clock generator Datasheet

DSC400
Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
General Description
The DSC400 is a four output crystal-less™
clock generator. It utilizes Micrel’s proven
PureSilicon™ MEMS technology to provide
excellent
jitter
and
stability
while
incorporating additional device functionality.
The frequencies of the outputs can be
identical or independently derived from
common PLLs.
Each
output
may
be
configured
independently to support a single ended
LVCMOS interface or a differential interface.
Differential options include LVPECL, LVDS, or
HCSL.
The DSC400 provides two independent select
lines for choosing between two sets of preconfigured frequencies per bank. It also has
two OE pins to allow for enabling and
disabling outputs.
The DSC400 is packaged in a 20-pin QFN
(5mm x 3.2mm) and is available in extended
commercial and
industrial
temperature
grades.
Features
 Low RMS Phase Jitter: <1 ps (typ)
 High Stability: ±25ppm, ±50ppm
 Wide Temperature Range
o Ext. commercial: -20°C to 70°C
o Industrial: -40°C to 85°C
 High Supply Noise Rejection: -50 dBc
 Four format configurable outputs:
o LVPECL, LVDS, HCSL, LVCMOS
 Available Pin-Selectable frequency table
o 1 pin per bank for 2 frequency sets
 Wide Freq. Range:
o 2.3 MHz – 460 MHz
 20 QFN Footprint (5mm x 3.2mm)
 Excellent Shock & Vibration Immunity
o Qualified to MIL-STD-883
 High Reliability
o 20x better MTF than quartz based devices
 Wide Supply Range of 2.25 to 3.6 V
 Lead Free & RoHS Compliant
 AEC-Q100 Automotive Qualified
Block Diagram
Applications
 Communications and Networks
 Ethernet
o 1G, 10GBASE-T/KR/LR/SR, and FCoE
 Storage Area Networks
o SATA, SAS, Fibre Channel
 Passive Optical Networks
o EPON, 10G-EPON, GPON, 10G-PON
 HD/SD/SDI Video & Surveillance
 Automotive
 Media and Video
 Embedded and Industrial

_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 1
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Pin Description
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
17
18
19
20
Pin
Name
OE1
NC
VSS
VSS
CLK0CLK0+
CLK1CLK1+
VDD2
FSB2
OE2
NC
VSS
VSS
CLK2CLK2+
CLK3CLK3+
VDD1
FSB1
Pin
Type
I
NA
Power
Power
O
O
O
O
Power
I
I
NA
Power
Power
O
O
O
O
Power
I
Description
Output Enable for Bank1 (CLK0 and CLK3); active high – See Table 1
Leave unconnected or connect to ground
Ground
Ground
Complement output of differential pair 0 (off when in LVCMOS format)
True output of differential pair 0 or LVCMOS output 0
Complement output of differential pair 1 (off when in LVCMOS format)
True output of differential pair 1 or LVCMOS output 1
Power Supply for Bank2 (CLK1 and CLK2)
Input for selecting pre-configured frequencies on Bank2 (CLK1 and CLK2)
Output Enable for Bank2 (CLK1 and CLK2); active high – See Table 1
Leave unconnected or connect to ground
Ground
Ground
Complement output of differential pair 2 (off when in LVCMOS format)
True output of differential pair 2 or LVCMOS output 2
Complement output of differential pair 3 (off when in LVCMOS format)
True output of differential pair 3 or LVCMOS output 3
Power Supply for Bank1 (CLK0 and CLK3)
Input for selecting pre-configured frequencies on Bank1 (CLK0 and CLK3)
Pin Diagram
20 QFN 5.0 × 3.2mm
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 2
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Operational Description
The DSC400 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it
does not require an external crystal to operate; it relies on the integrated MEMS resonator that
interfaces with internal PLLs. This technology enhances performance and reliability by allowing
tighter frequency stability over a far wider temperature range. In addition, the higher resistance to
shock and vibration decreases the aging rate to allow for much improved product life in the system.
Inputs
There are 4 input signals in the device. Each has an internal (40kΩ) pull up to default the selection
to a high (1). Inputs can be controlled through hardware strapping method with a resistor to
ground to assert the input low (0). Inputs may also be controlled by other components’ GPIOs
In case more than one frequency set is desired, FSB1 and FSB2 are used for independently
selecting one of two sets per bank. FSB1 selects the pre-configured set on Bank1 (CLK0 and CLK3)
and FSB2 selects the pre-configured set on Bank2 (CLK1 and CLK2), as shown in table 2.
If there is a requirement to disable outputs, the inputs OE1 and OE2 are used in conjunction to
disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.
Table 1: Output Enable (OE) Selection Table
OE1
OE2
Bank1 (CLK0 & CLK3)
Bank2 (CLK1 & CLK2)
0
0
Hi-Z
Hi-Z
0
1
Hi-Z
Running
1
0
Running
Hi-Z
1
1
Running
Running
Outputs
The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to
allow for optimized noise isolation between the two banks. Each bank provides two synchronous
outputs generated by a common PLL:


Bank1 is composed of outputs CLK0 and CLK3
Bank2 is composed of outputs CLK1 and CLK2
Each output maybe pre-configured independently to be one of the following formats: LVCMOS,
LVDS, LVPECL or HCSL. In case the output is configured to be the single ended LVCMOS, the
frequency is generated on the true output (CLKx+) and the complement output (CLKx-) is shut off
in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential outputs and from
2.3MHz to 170MHz on LVCMOS outputs.
Power
VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different
supply voltage from the other as long as it is within the 2.25V to 3.6V range. Each VDD pin should
have a 0.1µF capacitor to filter high frequency noise. VSS is common to the entire device.
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 3
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Ordering Information
(Example shown in red font)
DSC400- 4 3 2 1 Q x x x x K E 1 T
4
T
T
CLK3 Output Format
0: off
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Packing
T: Tape & Reel
Stability
1: ±50ppm
2: ±25ppm
CLK2 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Temp Range
E: -20ºC to 70ºC
I: -40ºC to 85º
Package
K: 20 QFN
CLK1 Output Format
0: off
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Frequency Code
Qxxxx is assigned
by factory; see
Table2
CLK0 Output Format
1: LVCMOS
2: LVPECL
3: LVDS
4: HCSL
Factory configuration code assignment of Qxxxx
The DSC400 is meant for customers to define their own frequency requirements at the four
available outputs. The Qxxxx number identifies these specific customer requirements and is
assigned by the factory.
Table 2: Example of how FSB1 and FSB2 are applied and the Qxxxx code assignment
Bank1
FSB1
Qxxxx number
Outputs
1 (default)
0
CLK0
125 MHz
150 MHz
CLK3
50 MHz
25 MHz
Bank2
Q0001
FSB2
Outputs
1 (default)
0
CLK1
156.25 MHz
100 MHz
CLK2
156.25 MHz
100 MHz
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 4
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Absolute Maximum Ratings
Item
Min
Max
Unit
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
-0.3
+4.0
V
-0.3
-55
-
VDD+0.3
+150
+150
+260
V
°C
°C
°C
ESD
HBM
MM
CDM
-
Condition
40sec max.
V
4000
400
1500
Note: 1000+ years of data retention on internal memory
Specifications
(Unless specified otherwise: Ta =25° C, VDD = 3.3V)
Parameter
Supply Voltage
Symbol
1
VDD
Supply Current – Core2
Frequency Stability
Aging – first year
Aging – after first year
Startup Time3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time4
Output Enable Time
Pull-Up Resistor
Condition
4
Min.
Typ.
2.25
Max.
Unit
3.6
V
44
mA
IDDcore
OE(1:2) = 0
All outputs are disabled
Δf
All temp and VDD ranges
±25
±50
ppm
ΔfY1
ΔfY2+
tSU
1 year @25°C
Year 2 and beyond @25°C
T=25°C
±5
<±1/yr
5
ppm
ppm
ms
0.25xVDD
V
OE(1:2) transition from 1 to 0
5
ns
tEN
OE(1:2) transition from 0 to 1
20
ns
RPU
All input pins have an internal pullup
VIH
VIL
tDA
40
0.75xVDD
-
40
kΩ
Notes:
1. VDD pins should be filtered with a 0.1µF capacitor connected between VDD and VSS.
2. The addition of IDDcore and IDDio provides total current consumption of the device
3. tsu is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled.
4. Output Waveform figures below the parameters. See Output Waveform section
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 5
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVPECL Outputs6
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
RL=50Ω
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
4
Frequency
tR
tF
VDD-1.08
-
VDD-1.55
V
Single-Ended
800
mV
20% to 80%
RL=50Ω
250
ps
f0
Single Frequency
2.3
460
MHz
SYM
Differential
48
52
%
IDDio
Per output at 125MHz
35
38
mA
Period Jitter
JPER
Integrated Phase Noise
JPH
CLK(0:3) = 156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
2.5
0.25
0.38
1.7
Output Duty Cycle
2
Supply Current – IO
5
Notes:
5.
6.
psRMS
2
psRMS
Period Jitter includes crosstalk from adjacent output
LVPECL applicable to ext. commercial temperature only
LVPECL: Typical Termination Scheme
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 6
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVDS Outputs
Output offset Voltage
VOS
Delta Offset Voltage
∆VOS
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
VPP
3
Frequency
tR
tF
R=100Ω Differential
1.125
1.4
V
50
mV
Single-Ended
350
mV
20% to 80%
RL=50Ω, CL= 2pF
200
ps
f0
Single Frequency
2.3
460
MHz
SYM
Differential
48
52
%
Supply Current – IO
IDDio
Per output at 125MHz
Period Jitter
JPER
Integrated Phase Noise
JPH
Output Duty Cycle
2
9
12
2.5
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.28
0.4
1.7
mA
psRMS
2
psRMS
LVDS: Typical Termination Scheme
If the 100Ω clamping resistor does not exist inside the receiving device, it should be added externally on the
PCB and placed as close as possible to the receiver.
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 7
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
HCSL Outputs
Output Logic Levels
Output logic high
Output logic low
VOH
VOL
Pk to Pk Output Swing
Output Transition time
Rise Time
Fall Time
RL=50Ω
0.725
-
Single-Ended
3
0.1
750
V
mV
20% to 80%
RL=50Ω, CL= 2pF
200
400
ps
f0
Single Frequency
2.3
460
MHz
SYM
Differential
48
52
%
Supply Current – IO
IDDio
Per output at 125MHz
22
mA
Period Jitter
JPER
Integrated Phase Noise
JPH
Frequency
Output Duty Cycle
2
tR
tF
20
2.5
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
0.25
0.37
1.7
psRMS
2
psRMS
HCSL: Typical Termination Scheme
RS is a series resistor implemented to match the trace impedance. Depending on the board
layout, the value may range from 0 to 30Ω
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 8
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
LVCMOS Outputs
Output Logic Levels
Output logic high
Output logic low
Output Transition time3
Rise Time
Fall Time
Frequency
VOH
VOL
tR
tF
f0
Output Duty Cycle
SYM
Supply Current – IO2
Period Jitter
IDDio
JPER
Integrated Phase Noise
JPH
I=±6mA
0.9xVDD
-
20% to 80%
CL=15pF
All temp range except Auto
Auto temp range
1.1
1.3
2.3
45
Per output at 125MHz, CL=15pF
CLK(0:3) =125MHz
200kHz to 20MHz @ 125MHz
100kHz to 20MHz @ 125MHz
12kHz to 20MHz @ 125MHz
11
3
0.3
0.38
1.7
0.1xVDD
V
2
2
170
100
ns
MHz
55
%
14
mA
psRMS
2
psRMS
LVCMOS: Typical Termination Scheme
RS is a series resistor implemented to match the trace impedance to that of the clock
output. Depending on the board layout, the value may range from 0 to 27Ω
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 9
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Connection Diagram:
The connection Diagram below includes recommended capacitors to be placed on each VDD
for noise filtering.
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 10
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Output Waveform

Differential Output (LVDS, LVPECL, HCSL)

LVCMOS Output
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 11
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Solder Reflow Profile
MSL 1 @ 260°C refer to JSTD-020C
Ramp-up rate (200°C to peak temp)
3°C/sec max.
Preheat time 150°C to 200°C
60-180 sec
Time maintained above 217°C
60-150 sec
Peak temperature
255-260°C
Time within 5°C of actual peak
20-40 sec
Ramp-down rate
6°C/sec max.
Time 25°C to peak temperature
8 min max.
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 12
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Package Dimensions
20 QFN, 5.0mm x 3.2 mm
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 13
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Recommended Solder Pad Layout
units: mm[inches]
Connect the center pad to ground plane for best thermal performance
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 14
DSC400 Configurable Four Output, Low Jitter Crystal-less™ Clock Generator
Disclaimer:
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a
warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license,
whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of
sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including
liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to
result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose
failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or
systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.
MICREL, Inc.
Phone: +1 (408) 944-0800
●
●
2180 Fortune Drive,
Fax: +1 (408) 474-1000
San Jose, California
95131
● Email: [email protected]
●
●
USA
www.micrel.com
_____________________________________________________________________________________________________________________________ _________________
DSC400
Page 15
Similar pages