TI LM5069MMX-1 Lm5069 positive high voltage hot swap / inrush current controller with power limiting Datasheet

LM5069
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SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013
LM5069 Positive High Voltage Hot Swap / Inrush Current Controller with Power Limiting
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FEATURES
APPLICATIONS
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1
2
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Wide Operating Range: +9V to +80V
In-rush Current Limit for Safe Board Insertion
into Live Power Sources
Programmable Maximum Power Dissipation in
the External Pass Device
Adjustable Current Limit
Circuit Breaker Function for Severe OverCurrent Events
Internal High Side Charge Pump and Gate
Driver for External N-channel MOSFET
Adjustable Under-Voltage Lockout (UVLO) and
Hysteresis
Adjustable Over-Voltage Lockout (OVLO) and
Hysteresis
Initial Insertion Timer Allows Ringing and
Transients to Subside after System
Connection
Programmable Fault Timer Avoids Nuisance
Trips
Active High Open Drain POWER GOOD Output
Available in Latched Fault and Automatic
Restart Versions
Server Backplane Systems
Base Station Power Distribution Systems
Solid State Circuit Breaker
24V/48V Industrial Systems
PACKAGE
•
VSSOP-10
DESCRIPTION
The LM5069 positive hot swap controller provides
intelligent control of the power supply connections
during insertion and removal of circuit cards from a
live system backplane or other "hot" power sources.
The LM5069 provides in-rush current control to limit
system voltage droop and transients. The current limit
and power dissipation in the external series pass NChannel MOSFET are programmable, ensuring
operation within the Safe Operating Area (SOA). The
POWER GOOD output indicates when the output
voltage is within 1.25V of the input voltage. The input
under-voltage and over-voltage lockout levels and
hysteresis are programmable, as well as the initial
insertion delay time and fault detection time. The
LM5069-1 latches off after a fault detection, while the
LM5069-2 automatically restarts at a fixed duty cycle.
The LM5069 is available in a 10 pin VSSOP package.
TYPICAL APPLICATION
V SYS
V OUT
VIN
SENSE GATE
UVLO
OUT
LM5069
Power
Good
PGD
OVLO
TIMER
GND
PWR
Figure 1. Positive Power Supply Control
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM5069
SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013
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CONNECTION DIAGRAM
SENSE
1
10
GATE
VIN
OUT
2
9
UVLO
3
8
PGD
OVLO
4
7
PWR
GND
5
6
TIMER
Figure 2. Top View
10-Lead VSSOP
PIN DESCRIPTIONS
Pin #
Name
Description
Applications Information
1
SENSE
Current sense input
The voltage across the current sense resistor (RS) is measured from VIN to this pin. If
the voltage across RS reaches 55mV the load current is limited and the fault timer
activates.
2
VIN
Positive supply input
A small ceramic bypass capacitor close to this pin is recommended to suppress
transients which occur when the load current is switched off.
3
UVLO
Under-voltage lockout
An external resistor divider from the system input voltage sets the under-voltage turnon threshold. An internal 21 µA current source provides hysteresis. The enable
threshold at the pin is 2.5V. This pin can also be used for remote shutdown control.
4
OVLO
Over-voltage lockout
An external resistor divider from the system input voltage sets the over-voltage turn-off
threshold. An internal 21 µA current source provides hysteresis. The disable threshold
at the pin is 2.5V.
5
GND
Circuit ground
6
TIMER
Timing capacitor
7
PWR
Power limit set
An external resistor connected to this pin, in conjunction with the current sense resistor
(RS), sets the maximum power dissipation allowed in the external series pass
MOSFET.
8
PGD
Power Good indicator
An open drain output. When the external MOSFET VDS decreases below 1.25V, the
PGD indicator is active (high). When the external MOSFET VDS increases above 2.5V
the PGD indicator switches low.
9
OUT
Output feedback
Connect to the output rail (external MOSFET source). Internally used to determine the
MOSFET VDS voltage for power limiting, and to control the PGD indicator.
10
GATE
Gate drive output
Connect to the external MOSFET’s gate. This pin's voltage is typically 12V above the
OUT pin when enabled.
An external capacitor connected to this pin sets the insertion time delay and the Fault
Timeout Period. The capacitor also sets the restart timing of the LM5069-2.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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ABSOLUTE MAXIMUM RATINGS
(1) (2)
(3)
VIN to GND
-0.3V to 100V
SENSE, OUT, PGD to GND
GATE to GND
-0.3V to 100V
(3)
-0.3V to 100V
UVLO to GND
-0.3V to 100V
OVLO to GND
-0.3V to 7V
VIN to SENSE
-0.3V to +0.3V
ESD Rating
(4)
Human Body Model
2kV
Storage Temperature
-65°C to +150°C
Junction Temperature
+150°C
(1)
(2)
(3)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but do not ensure specific performance limits. For ensured specifications and conditions
see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The GATE pin voltage is typically 12V above VIN when the LM5069 is enabled. Therefore the Absolute Maximum Ratings for VIN
(100V) applies only when the LM5069 is disabled, or for a momentary surge to that voltage since the Absolute Maximum Rating for the
GATE pin is also 100V.
The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
OPERATING RATINGS (1)
VIN Supply Voltage
+9.0V to 80V
PGD Off Voltage
0V to 80V
Junction Temp. Range
−40°C to +125°C
(1)
For detailed information on soldering plastic VSSOP packages refer to the SNOA549 available from Texas Instruments.
ELECTRICAL CHARACTERISTICS
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 48V.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Input (VIN pin)
IIN-EN
Input Current, enabled
UVLO > 2.5V and OVLO < 2.5V
1.3
1.6
mA
UVLO <2.5V or OVLO >2.5V
IIN-DIS
Input Current, disabled
480
650
µA
PORIT
Power On Reset threshold at VIN to trigger VIN Increasing
insertion timer
7.6
8.0
V
POREN
Power On Reset threshold at VIN to
enable all functions
VIN increasing
8.4
9.0
V
POREN hysteresis
VIN decreasing
90
mV
OUT = VIN, Normal operation
11
µA
Disabled, OUT = 0V, SENSE = VIN
50
POREN-HYS
OUT pin
IOUT-EN
OUT bias current, enabled
IOUT-DIS
OUT bias current, disabled
(1)
UVLO, OVLO pins
(1)
UVLOTH
UVLO threshold
UVLOHYS
UVLO hysteresis current
UVLO = 1V
UVLODEL
UVLO delay
Delay to GATE high
55
Delay to GATE low
11
UVLOBIAS
UVLO bias current
OVLOTH
OVLO threshold
OVLOHYS
OVLO hysteresis current
2.45
2.5
2.55
V
12
21
30
µA
UVLO = 48V
OVLO = 2.6V
µs
1
µA
2.40
2.5
2.60
V
12
21
30
µA
OUT bias current (disabled) due to leakage current through an internal 1.0 MΩ resistance from SENSE to VOUT.
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ELECTRICAL CHARACTERISTICS (continued)
Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C
to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent
the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated the
following conditions apply: VIN = 48V.
Symbol
OVLODEL
OVLOBIAS
Parameter
Conditions
OVLO delay
OVLO bias current
Min.
Typ.
Delay to GATE high
55
Delay to GATE low
11
OVLO = 2.4V
Max.
Units
µs
1
µA
31
mV
Power Limit (PWR pin)
PWRLIM-1
Power limit sense voltage (VIN-SENSE)
PWRLIM-2
IPWR
PWR pin current
SENSE-OUT = 48V, RPWR = 150 kΩ
19
25
SENSE-OUT = 24V, RPWR = 75 kΩ
25
mV
VPWR = 2.5V
20
µA
Gate Control (GATE pin)
IGATE
Source current
Normal Operation, GATE-OUT = 5V
Sink current
UVLO < 2.5V
VIN - SENSE = 150 mV or VIN <
PORIT, VGATE = 5V
VGATE
10
16
22
µA
1.75
2
2.6
mA
45
110
175
mA
Gate output voltage in normal operation
GATE-OUT voltage
11.4
12
12.6
V
VCL
Threshold voltage
VIN-SENSE voltage
48.5
55
61.5
mV
tCL
Response time
VIN-SENSE stepped from 0 mV to
80 mV
45
µs
SENSE input current
Enabled, SENSE = OUT
23
µA
Disabled, OUT = 0V
60
Current Limit
ISENSE
Circuit Breaker
VCB
Threshold voltage
VIN - SENSE
tCB
Response time
VIN - SENSE stepped from 0 mV to
150 mV, time to GATE low, no load
80
105
130
mV
0.44
1.2
µs
Timer (TIMER pin)
VTMRH
Upper threshold
VTMRL
Lower threshold
Restart cycles (LM5069-2)
3.76
4
4.16
V
1.187
1.25
1.313
V
End of 8th cycle (LM5069-2)
0.3
Re-enable Threshold (LM5069-1)
ITIMER
Insertion time current
Sink current, end of insertion time
TIMER pin = 2V
Fault detection current
Fault sink current
V
0.3
V
3
5.5
8
µA
1.0
1.5
2.0
mA
51
85
120
µA
1.25
2.5
3.75
µA
DCFAULT
Fault Restart Duty Cycle
LM5069-2 only
0.5
%
tFAULT
Fault to GATE low delay
TIMER pin reaches 4.0V
12
µs
Power Good (PGD pin)
PGDTH
4
Threshold measured at SENSE-OUT
Decreasing
0.67
1.25
1.85
Increasing, relative to decreasing
threshold
0.95
1.25
1.55
60
150
mV
5
µA
PGDVOL
Output low voltage
ISINK = 2 mA
PGDIOH
Off leakage current
VPGD = 80V
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V
VIN Pin Input Current
vs.
VIN
SENSE PIN INPUT CURRENT (PA)
VIN PIN INPUT CURRENT (mA)
1.5
Enabled, UVLO = VIN
1.0
0.5
Disabled, UVLO = 0V
0
SENSE Pin Input Current
100
2.0
Disabled, UVLO = 0V
75
50
25
Enabled, UVLO = VIN
0
0
20
40
60
0
80
20
VIN VOLTAGE (V)
Figure 4.
OUT Pin Current
GATE Pin Voltage
vs.
VIN
14
Load at OUT Pin = 600:
Current flow is out of the pin
GATE-OUT VOLTAGE
OUT PIN CURRENT (PA)
Disabled, UVLO = 0V
40
20
Enabled, UVLO = VIN
0
10
8
6
4
Enabled, UVLO = VIN
Normal Operation
2
POREN
0
-20
20
40
80
12
60
0
60
Figure 3.
100
80
40
SENSE PIN VOLTAGE (V)
60
0
80
5
10
15
20
70
80
VIN VOLTAGE (V)
VIN VOLTAGE (V)
18
Figure 5.
Figure 6.
GATE Pin Source Current
vs.
VIN
PGD Pin Low Voltage
vs.
Sink Current
0.8
0.7
16
0.6
PGD VOLTAGE (V)
GATE PIN CURRENT (PA)
17
15
14
13
12
Enabled, UVLO = VIN
Normal Operation
11
0.3
0.1
POREN
9
5
0.4
0.2
10
0
0.5
10
15
20
70
80
VIN VOLTAGE (V)
0
0
5
10
15
20
PGD SINK CURRENT (mA)
Figure 7.
Figure 8.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V
MOSFET Power Dissipation Limit
vs.
RPWR and RS
250
RS = 0.005:
PFET (W)
160
RS = 0.1:
RS = 0.01:
120
80
RS = 0.02:
40
RS = 0.05:
0
30
0
60
90
120
200
150
100
50
TJ = 25°C
|
200
GATE PULLDOWN CURRENT,
CIRCUIT BREAKER (mA)
|
240
GATE Pull-Down Current, Circuit Breaker
vs
GATE Voltage
0
150
0
10
R PWR (k:)
UVLO Hysteresis Current
vs.
Temperature
OVLO Hysteresis Current
vs.
Temperature
OVLO HYSTERESIS CURRENT (PA)
UVLO HYSTERESIS CURRENT (PA)
23
21
20
22
21
20
19
0
20
40
60
80
100 125
-40 -20
JUNCTION TEMPERATURE (oC)
0
20
40
60
80
Figure 11.
Figure 12.
UVLO, OVLO Threshold
vs.
Temperature
Input Current, Enabled
vs.
Temperature
1.320
2.55
2.53
2.51
UVLO
OVLO
OVLO
UVLO
2.47
2.45
-40 -20
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (°C)
INPUT CURRENT, ENABLED (mA)
UVLO, OVLO THRESHOLD VOLTAGE (V)
92
Figure 10.
19
-40 -20
100 125
1.310
1.300
1.290
VIN = 48V
1.280
-40 -20
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
Figure 13.
6
82
GATE PIN VOLTAGE (V)
22
2.49
30
Figure 9.
23
2.50
20
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V
Current Limit Threshold
vs.
Temperature
Circuit Breaker Threshold
vs.
Temperature
115
CIRCUIT BREAKER THRESHOLD
(VOLTAGE ACROSS RS) (mV)
CURRENT LIMIT THRESHOLD
(VOLTAGE ACROSS RS) (mV)
57
56
55
54
53
-40 -20
0
20
40
60
80
110
105
100
95
90
85
-40 -20
100 125
40
60
80
Figure 16.
Power Limit Threshold
vs.
Temperature
GATE Output Voltage
vs.
Temperature
13.0
GATE OUTPUT VOLTAGE ABOVE
OUT PIN (V)
POWER LIMIT THRESHOLD
(VOLTAGE ACROSS RS) (mV)
20
Figure 15.
27
26
25
24
RPWR = 150 k:
VDS = 48V
23
-40 -20
0
20
40
60
80
100 125
12.5
12.0
11.5
GATE-OUT Voltage,
Normal Operation
11.0
-40 -20
100 125
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
Figure 17.
Figure 18.
GATE Source Current
vs.
Temperature
GATE Pull-Down Current, Circuit Breaker
vs.
Temperature
150
GATE PULLDOWN CURRENT,
CIRCUIT BREAKER (mA)
16.4
GATE SOURCE CURRENT (PA)
0
JUNCTION TEMPERATURE (oC)
JUNCTION TEMPERATURE (oC)
16.2
16.0
15.8
GATE-OUT = 5V
15.6
-40 -20
0
20
40
60
80
100 125
130
110
100
90
70
GATE PIN = 5V
50
-40 -20
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Figure 19.
Figure 20.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V
PGD Low Voltage
vs.
Temperature
PGD OUTPUT LOW VOLTAGE (mV)
160
120
80
.
40
PGD Sink Current = 2 mA
0
-40 -20
0
20
40
60
80
100 125
JUNCTION TEMPERATURE (oC)
Figure 21.
8
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BLOCK DIAGRAM
LM5069
Charge
Pump
55 mV
ID
VIN
Current Limit
Threshold
SENSE
16 PA
Gate
Control
GATE
2 mA
230
mA
1 M:
OUT
Current Limit/
Power Limit
Control
Power Limit
Threshold
VDS
12V
OUT
PGD
1.25V/
2.5V
5.5 PA
Insertion
Timer
20 PA
PWR
85 PA
Fault
Timer
21 PA
TIMER AND GATE
LOGIC CONTROL
TIMER
OVLO
2.5V
2.5V
1.5 mA
End
Insertion
Time
2.5 PA
Fault
Discharge
4.0V
UVLO
1.25V
21 PA
GND
8.4/8.3V
0.3V
Enable POR
Insertion Timer POR
VIN
7.6V
VIN
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FUNCTIONAL DESCRIPTION
Q1
VSYS
VOUT
RS
CIN
CL
R1
SENSE GATE
UVLO
OUT
RPG
LM5069
R2
OVLO
TIMER
R3
Power
Good
PGD
GND
PWR
RPWR
CT
Figure 22. Basic Application Circuit
The LM5069 is designed to control the in-rush current to the load upon insertion of a circuit card into a live
backplane or other "hot" power source, thereby limiting the voltage sag on the backplane’s supply voltage, and
the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing
possible unintended resets. A controlled shutdown when the circuit card is removed can also be implemented
using the LM5069. In addition to a programmable current limit, the LM5069 monitors and limits the maximum
power dissipation in the series pass device to maintain operation within the device Safe Operating Area (SOA).
Either current limiting or power limiting for an extended period of time results in the shutdown of the series pass
device. In this event, the LM5069-1 latches off until the circuit is re-enabled by external control, while the
LM5069-2 automatically restarts with defined timing. The circuit breaker function quickly switches off the series
pass device upon detection of a severe over-current condition. The Power Good (PGD) output pin indicates
when the output voltage is within 1.25V of the system input voltage (VSYS). Programmable under-voltage lock-out
(UVLO) and over-voltage lock-out (OVLO) circuits shut down the LM5069 when the system input voltage is
outside the desired operating range. The typical configuration of a circuit card with LM5069 hot swap protection
is shown in Figure 23.
+48V
RS
VSYS
VOUT
Q1
LIVE
BACKPLANE
OUT
VIN
LM5069
PGD
CL
LOAD
GND
GND
PLUG- IN BOARD
Figure 23. LM5069 Application
Power Up Sequence
The VIN operating range of the LM5069 is +9V to +80V, with a transient capability to +100V. Referring to the
Block Diagram and Figure 22 and Figure 24, as the voltage at VIN initially increases, the external N-channel
MOSFET (Q1) is held off by an internal 230 mA pull-down current at the GATE pin. The strong pull-down current
at the GATE pin prevents an inadvertent turn-on as the MOSFET’s gate-to-drain (Miller) capacitance is charged.
Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the PORIT threshold (7.6V)
the insertion time begins. During the insertion time, the capacitor at the TIMER pin (CT) is charged by a 5.5 µA
current source, and Q1 is held off by a 2 mA pull-down current at the GATE pin regardless of the VIN voltage.
The insertion time delay allows ringing and transients at VIN to settle before Q1 can be enabled. The insertion
time ends when the TIMER pin voltage reaches 4.0V. CT is then quickly discharged by an internal 1.5 mA pulldown current. After the insertion time, the LM5069 control circuitry is enabled when VIN reaches the POREN
threshold (8.4V). The GATE pin then switches on Q1 when VSYS exceeds the UVLO threshold (UVLO pin >2.5V).
If VSYS is above the UVLO threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin
charge pump sources 16 µA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is
limited by an internal 12V zener diode.
10
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As the voltage at the OUT pin increases, the LM5069 monitors the drain current and power dissipation of
MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the
load. During the in-rush limiting interval (t2 in Figure 24) an internal 85 µA fault timer current source charges CT.
If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the
TIMER pin reaches 4.0V the 85 µA current source is switched off, and CT is discharged by the internal 2.5 µA
current sink (t3 in Figure 24). The in-rush limiting interval is complete when the voltage at the OUT pin increases
to within 1.25V of the input voltage (VSYS), and the PGD pin switches high.
If the TIMER pin voltage reaches 4.0V before in-rush current limiting or power limiting ceases (during t2), a fault
is declared and Q1 is turned off. See the Fault Timer & Restart section for a complete description of the fault
mode.
VSYS
UVLO
V IN
POR IT
4V
5.5 PA
TIMER
Pin
GATE
Pin
85 PA
2.5 PA
1.5 mA
230 mA
pull-down
2 mA pull-down
16 PA source
I LIMIT
Load
Current
Output
Voltage
(OUT Pin)
1.25V
PGD
t1
Insertion Time
t2
In- rush
Limiting
t3
Normal Operation
Figure 24. Power Up Sequence (Current Limit only)
Gate Control
A charge pump provides internal bias voltage above the output voltage (OUT pin) to enhance the N-Channel
MOSFET’s gate. The gate-to-source voltage is limited by an internal 12V zener diode. During normal operating
conditions (t3 in Figure 24) the gate of Q1 is held charged by an internal 16 µA current source to approximately
12V above OUT. If the maximum VGS rating of Q1 is less than 12V, a lower voltage external zener diode must be
added between the GATE and OUT pins. The external zener diode must have a forward current rating of at least
250 mA.
When the system voltage is initially applied, the GATE pin is held low by a 230 mA pull-down current. This helps
prevent an inadvertent turn-on of the MOSFET through its drain-gate capacitance as the applied system voltage
increases.
During the insertion time (t1 in Figure 24) the GATE pin is held low by a 2 mA pull-down current. This maintains
Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO.
Following the insertion time, during t2 in Figure 24, the gate voltage of Q1 is modulated to keep the current or
power dissipation level from exceeding the programmed levels. While in the current or power limiting mode the
TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 4V the
TIMER pin capacitor then discharges, and the circuit enters normal operation.
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If the in-rush limiting condition persists such that the TIMER pin reached 4V during t2, the GATE pin is then
pulled low by the 2 mA pull-down current. The GATE pin is then held low until either a power up sequence is
initiated (LM5069-1), or until the end of the restart sequence (LM5069-2). See the Fault Timer & Restart section.
If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is
pulled low by the 2 mA pull-down current to switch off Q1.
Q1
VSYS
VOUT
RS
VIN
CL
SENSE
GATE
OUT
Charge
Pump
16 PA
Current Limit /
Power Limit
Control
2 mA
12V
Fault /
UVLO /
OVLO /
Insertion
time
Gate
Control
230 mA
Circuit Breaker /
Initial Hold - down
Figure 25. Gate Control
Current Limit
The current limit threshold is reached when the voltage across the sense resistor RS (VIN to SENSE) reaches 55
mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the
current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section. If the load
current falls below the current limit threshold before the end of the Fault Timeout Period, the LM5069 resumes
normal operation. For proper operation, the RS resistor value should be no larger than 100 mΩ.
Circuit Breaker
If the load current increases rapidly (e.g., the load is short-circuited) the current in the sense resistor (RS) may
exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds
twice the current limit threshold (105 mV/RS), Q1 is quickly switched off by the 230 mA pull-down current at the
GATE pin, and a Fault Timeout Period begins. When the voltage across RS falls below 105 mV the 230 mA pulldown current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit
or the power limit functions. If the TIMER pin reaches 4.0V before the current limiting or power limiting condition
ceases, Q1 is switched off by the 2 mA pull-down current at the GATE pin as described in the Fault Timer &
Restart section.
Power Limit
An important feature of the LM5069 is the MOSFET power limiting. The Power Limit function can be used to
maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5069 determines
the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current
through the sense resistor (VIN to SENSE). The product of the current and voltage is compared to the power
limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold,
the GATE voltage is modulated to reduce the current in Q1. While the power limiting circuit is active, the fault
timer is active as described in the Fault Timer & Restart section.
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Fault Timer & Restart
When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the
gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation. When either
limiting function is activated, an 85 µA fault timer current source charges the external capacitor (CT) at the
TIMER pin as shown in Figure 27 (Fault Timeout Period). If the fault condition subsides during the Fault Timeout
Period before the TIMER pin reaches 4.0V, the LM5069 returns to the normal operating mode and CT is
discharged by the 2.5 µA current sink. If the TIMER pin reaches 4.0V during the Fault Timeout Period, Q1 is
switched off by a 2 mA pull-down current at the GATE pin. The subsequent restart procedure then depends on
which version of the LM5069 is in use.
The LM5069-1 latches the GATE pin low at the end of the Fault Timeout Period. CT is then discharged to ground
by the 2.5 µA fault current sink. The GATE pin is held low by the 2 mA pull-down current until a power up
sequence is externally initiated by cycling the input voltage (VSYS), or momentarily pulling the UVLO pin below
2.5V with an open-collector or open-drain device as shown in Figure 26. The voltage at the TIMER pin must be
<0.3V for the restart procedure to be effective.
VSYS
R1
VIN
UVLO
Restart
Control
LM5069-1
R2
OVLO
R3
GND
Figure 26. Latched Fault Restart Control
The LM5069-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 4.0V
and 1.25V seven times after the Fault Timeout Period, as shown in Figure 27. The period of each cycle is
determined by the 85 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor CT.
When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 16 µA current source at the GATE pin
turns on Q1. If the fault condition is still present, the Fault Timeout Period and the restart cycle repeat.
Fault
Detection
I LIMIT
Load
Current
2. 5 P A
4V
85 PA
TIMER
Pin
16 PA
Gate Charge
2 mA
pulldown
GATE
Pin
1.25V
1
Fault Timeout
Period
2
3
7
8
0.3V
t RESTART
Figure 27. Restart Sequence (LM5069-2)
Under-Voltage Lock-Out (UVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lock-out (OVLO) levels. Typically
the UVLO level at VSYS is set with a resistor divider (R1-R3) as shown in Figure 22. When VSYS is below the
UVLO level, the internal 21 µA current source at UVLO is enabled, the current source at OVLO is off, and Q1 is
held off by the 2 mA pull-down current at the GATE pin. As VSYS is increased, raising the voltage at UVLO above
2.5V, the 21 µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for
this threshold. With the UVLO pin above 2.5V, Q1 is switched on by the 16 µA current source at the GATE pin if
the insertion time delay has expired (Figure 24). See the Applications Section for a procedure to calculate the
values of the threshold setting resistors (R1-R3). The minimum possible UVLO level at VSYS can be set by
connecting the UVLO pin to VIN. In this case Q1 is enabled when the VIN voltage reaches the POREN threshold.
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Over-Voltage Lock-Out (OVLO)
The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range
defined by the programmable under-voltage lockout (UVLO) and over-voltage lock-out (OVLO) levels. If VSYS
raises the OVLO pin voltage above 2.5V Q1 is switched off by the 2 mA pull-down current at the GATE pin,
denying power to the load. When the OVLO pin is above 2.5V, the internal 21 µA current source at OVLO is
switched on, raising the voltage at OVLO to provide threshold hysteresis. When VSYS is reduced below the OVLO
level Q1 is enabled. See the Applications Section for a procedure to calculate the threshold setting resistor
values.
Shutdown Control
The load current can be remotely switched off by taking the UVLO pin below its 2.5V threshold with an open
collector or open drain device, as shown in Figure 28. Upon releasing the UVLO pin the LM5069 switches on the
load current with in-rush current and power limiting.
VSYS
R1
VIN
UVLO
Shutdown
Control
LM5069
R2
OVLO
R3
GND
Figure 28. Shutdown Control
Power Good Pin
The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of
sustaining 80V in the off-state, and transients up to 100V. An external pull-up resistor is required at PGD to an
appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be
higher or lower than the voltages at VIN and OUT. PGD is switched high when the voltage from SENSE to OUT
(the external MOSFET’s VDS) decreases below 1.25V. PGD switches low when the MOSFET’s VDS is increased
past 2.5V. If the UVLO pin is taken below 2.5V, or the OVLO pin taken above 2.5V, to disable the LM5069, PGD
switches low within 10 µs without waiting for the voltage at OUT to fall 2.5V below the voltage at SENSE. The
PGD output pin is high when the voltage at VIN is less than 5V.
APPLICATION INFORMATION
(REFER TO Figure 22)
CURRENT LIMIT, RS
The LM5069 monitors the current in the external MOSFET (Q1) by measuring the voltage across the sense
resistor (RS), connected from VIN to SENSE. The required resistor value is calculated from:
55 mV
RS =
ILIM
(1)
where ILIM is the desired current limit threshold. If the voltage across RS reaches 55 mV, the current limit circuit
modulates the gate of Q1 to regulate the current at ILIM. While the current limiting circuit is active, the fault timer
is active as described in the Fault Timer & Restart section. For proper operation, RS must be no larger than 100
mΩ.
While the maximum load current in normal operation can be used to determine the required power rating for
resistor RS, basing it on the current limit value provides a more reliable design since the circuit can operate near
the current limit threshold continuously. The resistor’s surge capability must also be considered since the circuit
breaker threshold is twice the current limit threshold. Connections from RS to the LM5069 should be made using
Kelvin techniques. In the suggested layout of Figure 29 the small pads at the lower corners of the sense resistor
connect only to the sense resistor terminals, and not to the traces carrying the high current. With this technique,
only the voltage across the sense resistor is applied to VIN and SENSE, eliminating the voltage drop across the
high current solder connections.
14
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HIGH CURRENT PATH
FROM
SYSTEM
INPUT
VOLTAGE
TO MOSFET'S
DRAIN
SENSE
RESISTOR
RS
SENSE
VIN
3
10
9
8
4
LM5069 7
5
6
Figure 29. Sense Resistor Connections
POWER LIMIT THRESHOLD
The LM5069 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the
current in RS), and the VDS of Q1 (SENSE to OUT pins). The resistor at the PWR pin (RPWR) sets the maximum
power dissipation for Q1, and is calculated from the following equation:
RPWR = 1.25 x 105 x RS x PFET(LIM)
(2)
where PFET(LIM) is the desired power limit threshold for Q1, and RS is the current sense resistor described in the
Current Limit section. For example, if RS is 10 mΩ , and the desired power limit threshold is 60W, RPWR
calculates to 75 kΩ. If Q1’s power dissipation reaches the threshold Q1’s gate is modulated to reduce the load
current, keeping Q1’s power from exceeding the threshold. For proper operation of the power limiting feature,
RPWR must be ≤150 kΩ. While the power limiting circuit is active, the fault timer is active as described in the Fault
Timer & Restart section. Typically, power limit is reached during startup, or if the output voltage falls due to a
severe overload or short circuit.
The programmed maximum power dissipation should have a reasonable margin from the maximum power
defined by the FET's SOA chart if the LM5069-2 is used since the FET will be repeatedly stressed during fault
restart cycles. The FET manufacturer should be consulted for guidelines.
If the application does not require use of the power limit function the PWR pin can be left open.
TURN-ON TIME
The output turn-on time depends on whether the LM5069 operates in current limit, or in both power limit and
current limit, during turn-on.
A) Turn-on with current limit only: The current limit threshold (ILIM) is determined by the current sense resistor
(RS). If the current limit threshold is less than the current defined by the power limit threshold at maximum VDS
the circuit operates at the current limit threshold only during turn-on. Referring to Figure 32a, as the load current
reaches ILIM, the gate-to-source voltage is controlled at VGSL to maintain the current at ILIM. As the output voltage
reaches its final value (VDS ≊ 0V) the drain current reduces to its normal operating value, and the gate is charged
to approximately 12V (VGATE). The time for the OUT pin voltage to transition from zero volts to VSYS is equal to:
VSYS x CL
tON =
ILIM
where CL is the load capacitance. For example, if VSYS = 48V, CL = 1000 µF, and ILIM = 1A, tON calculates to 48
ms. The maximum instantaneous power dissipated in the MOSFET is 48W. This calculation assumes the time
from t1 to t2 in Figure 32a is small compared to tON, and the load does not draw any current until after the output
voltage has reached its final value, and PGD switches high (Figure 30). If the load draws current during the turnon sequence (Figure 31), the turn-on time is longer than the above calculation, and is approximately equal to:
tON = -(RL x CL) x In
(ILIM x RL) - VSYS
(ILIM x RL)
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where RL is the load resistance. The Fault Timeout Period must be set longer than tON to prevent a fault
shutdown before the turn-on sequence is complete.
RS
Q1
VSYS
OUT
PGD
VIN
LM5069
CL
RL
GND
GND
Figure 30. No Load Current During Turn-On
RS
Q1
VSYS
CL
OUT
VIN
PGD
RL
LM5069
GND
GND
Figure 31. Load Draws Current During Turn-On
B) Turn-on with power limit and current limit: The maximum allowed power dissipation in Q1 (PFET(LIM)) is
defined by the resistor at the PWR pin, and the current sense resistor RS. See the Power Limit Threshold
section. If the current limit threshold (ILIM) is higher than the current defined by the power limit threshold at
maximum VDS (PFET(LIM)/VSYS) the circuit operates initially at the power limit mode when the VDS of Q1 is high,
and then transitions to current limit mode as the current increases to ILIM and VDS decreases. See Figure 32ab.
Assuming the load (RL) is not connected during turn-on, the time for the output voltage to reach its final value is
approximately equal to:
CL x VSYS2 CL x PFET(LIM)
tON =
+
2 x PFET(LIM)
2 x ILIM2
For example, if VSYS = 48V, CL = 1000 µF, ILIM = 1A, and PFET(LIM) = 20W, tON calculates to ≊68 ms, and the initial
current level (IP) is approximately 0.42A. The Fault Timeout Period must be set longer than tON.
VSYS
VSYS
VDS
VDS
Drain Current
ILIM
Drain Current
ILIM
IP
0
0
VGATE
VGATE
Gate- to - Source Voltage
VGSL
VGSL
VTH
VTH
t ON
0
0
t3
t1 t2
a) Current Limit Only
t ON
0
0
b) Power Limit and Current Limit
Figure 32. MOSFET Power Up Waveforms
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MOSFET SELECTION
It is recommended that the external MOSFET (Q1) selection be based on the following criteria:
- The BVDSS rating should be greater than the maximum system voltage (VSYS), plus ringing and transients
which can occur at VSYS when the circuit card, or adjacent cards, are inserted or removed.
- The maximum continuous current rating should be based on the current limit threshold (55 mV/RS), not the
maximum load current, since the circuit can operate near the current limit threshold continuously.
The Pulsed Drain Current spec (IDM) must be greater than the current threshold for the circuit breaker
function (105 mV/RS).
- The SOA (Safe Operating Area) chart of the device, and the thermal properties, should be used to determine
the maximum power dissipation threshold set by the RPWR resistor. The programmed maximum power dissipation
should have a reasonable margin from the maximum power defined by the FET's SOA chart if the LM5069-2 is
used since the FET will be repeatedly stressed during fault restart cycles. The FET manufacturer should be
consulted for guidelines.
- RDS(on) should be sufficiently low that the power dissipation at maximum load current (IL(max)2 x RDS(on)) does
not raise its junction temperature above the manufacturer’s recommendation.
If the device chosen for Q1 has a maximum VGS rating less than 12V, an external zener diode must be added
from its gate to source, with the zener voltage less than the maximum VGS rating. The zener diode’s forward
current rating must be at least 250 mA to conduct the GATE pull-down current during startup and in the circuit
breaker mode.
TIMER CAPACITOR, CT
The TIMER pin capacitor (CT) sets the timing for the insertion time delay, fault timeout period, and restart timing
of the LM5069-2.
A) Insertion Delay - Upon applying the system voltage (VSYS) to the circuit, the external MOSFET (Q1) is held
off during the insertion time (t1 in Figure 24) to allow ringing and transients at VSYS to settle. Since each
backplane’s response to a circuit card plug-in is unique, the worst case settling time must be determined for each
application. The insertion time starts when VIN reaches the PORIT threshold, at which time the internal 5.5 µA
current source charges CT from 0V to 4.0V. The required capacitor value is calculated from:
t1 x 5.5 PA
CT =
= t1 x 1.38 x 10-6
4V
For example, if the desired insertion delay is 250 ms, CT calculates to 0.345 µF. At the end of the insertion delay,
CT is quickly discharged by a 1.5 mA current sink.
B) Fault Timeout Period - During in-rush current limiting or upon detection of a fault condition where the current
limit and/or power limit circuits regulate the current through Q1, the fault timer current source (85 µA) is switched
on to charge CT. The Fault Timeout Period is the time required for the TIMER pin voltage to reach 4.0V, at which
time Q1 is switched off. The required capacitor value for the desired Fault Timeout Period tFAULT is calculated
from:
tFAULT x 85 PA
= tFAULT x 2.13 x 10-5
CT =
(3)
4V
For example, if the desired Fault Timeout Period is 16 ms, CT calculates to 0.34 µF. After the Fault Timeout
Period, the LM5069-1 latches the GATE pin low until a power up sequence is initiated by external circuitry. CT is
discharged by the 2.5 µA current sink at the end of the Fault Timeout Period. See the Fault Timer & Restart
section and Figure 26. When the Fault Timeout Period of the LM5069-2 expires, a restart sequence starts as
described below (Restart Timing). Since the LM5069 normally operates in power limit and/or current limit during
a power up sequence, the Fault Timeout Period must be longer than the time required for the output voltage to
reach its final value. See the Turn-on Time section.
C) Restart Timing For the LM5069-2, after the Fault Timeout Period described above, CT is discharged by the
2.5 µA current sink to 1.25V. The TIMER pin then cycles through seven additional charge/discharge cycles
between 1.25V and 4.0V as shown in Figure 27. The restart time ends when the TIMER pin voltage reaches
0.3V during the final high-to-low ramp. The restart time, after the Fault Timeout Period, is equal to:
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tRESTART = CT x
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7 x 2.75V 7 x 2.75V 3.7V
+
+
2.5 PA
85 PA
2.5 PA
= CT x 9.4 x 106
For example, if CT = 0.33 µF, tRESTART = 3.1 seconds. At the end of the restart time, Q1 is switched on. If the fault
is still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q1 is approximately
0.5% in this mode.
UVLO, OVLO
By programming the UVLO and OVLO thresholds the LM5069 enables the series pass device (Q1) when the
input supply voltage (VSYS) is within the desired operational range. If VSYS is below the UVLO threshold, or above
the OVLO threshold, Q1 is switched off, denying power to the load. Hysteresis is provided for each threshold.
Option A: The configuration shown in Figure 33 requires three resistors (R1-R3) to set the thresholds.
VSYS
VIN
R1
LM5069
UVLO
2.50V
R2
2.50V
R3
21 PA
TIMER AND GATE
LOGIC CONTROL
OVLO
21 PA
GND
Figure 33. UVLO and OVLO Thresholds Set By R1-R3
The procedure to calculate the resistor values is as follows:
- Choose the upper UVLO threshold (VUVH), and the lower UVLO threshold (VUVL).
- Choose the upper OVLO threshold (VOVH).
- The lower OVLO threshold (VOVL) cannot be chosen in advance in this case, but is determined after the
values for R1-R3 are determined. If VOVL must be accurately defined in addition to the other three thresholds, see
Option B below.
The resistors are calculated as follows:
VUVH - VUVL VUV(HYS)
R1 =
=
21 PA
21 PA
R3 =
2.5V x R1 x VUVL
VOVH x (VUVL - 2.5V)
R2 =
2.5V x R1
- R3
VUVL - 2.5V
The lower OVLO threshold is calculated from:
VOVL = [(R1 + R2) x ((2.5V) - 21 PA)] + 2.5V
R3
As an example, assume the application requires the following thresholds: VUVH = 36V, VUVL = 32V, VOVH = 60V.
36V ± 32V
4V
R1 =
= 190.5 k:
=
21 PA
21 PA
R3 =
18
2.5V x 190.5 k: x 32V
= 8.61 k:
60V x (32V - 2.5V)
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R2 =
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2.5V x 190.5 k:
- 8.61 k: = 7.53 k:
(32V - 2.5V)
The lower OVLO threshold calculates to 55.8V, and the OVLO hysteresis is 4.2V. Note that the OVLO hysteresis
is always slightly greater than the UVLO hysteresis in this configuration. When the R1-R3 resistor values are
known, the threshold voltages and hysteresis are calculated from the following:
2.5V
VUVH = 2.5V + [R1 x (21 PA +
)]
(R2 + R3)
VUVL =
2.5V x (R1 + R2 + R3)
R2 + R3
VUV(HYS) = R1 x 21 µA
VOVH =
2.5V x (R1 + R2 + R3)
R3
VOVL = [(R1 + R2) x (2.5V) - 21 PA)] + 2.5V
R3
VOV(HYS) = (R1 + R2) x 21 µA
Option B: If all four thresholds must be accurately defined, the configuration in Figure 34 can be used.
VSYS
VIN
21 PA
LM5069
R1
UVLO
2.5V
R3
R2
2.5V
TIMER AND GATE
LOGIC CONTROL
OVLO
R4
21 PA
GND
Figure 34. Programming the Four Thresholds
The four resistor values are calculated as follows:
- Choose the upper and lower UVLO thresholds (VUVH) and (VUVL).
VUVH - VUVL VUV(HYS)
R1 =
=
21 PA
21 PA
R2 =
2.5V x R1
(VUVL - 2.5V)
-Choose the upper and lower OVLO threshold (VOVH) and (VOVL).
VOVH - VOVL VOV(HYS)
R3 =
=
21 PA
21 PA
R4 =
2.5V x R3
(VOVH - 2.5V)
As an example, assume the application requires the following thresholds: VUVH = 22V, VUVL = 17V, VOVH = 60V,
and VOVL = 58V. Therefore VUV(HYS) = 5V, and VOV(HYS) = 2V. The resistor values are:
R1 = 238 kΩ, R2 = 41 kΩ
R3 = 95.2 kΩ, R4 = 4.14 kΩ
Where the R1-R4 resistor values are known, the threshold voltages and hysteresis are calculated from the
following:
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VUVH = 2.5V + [R1 x (2.5V + 21 PA)]
R2
2.5V x (R1 + R2)
VUVL =
R2
VUV(HYS) = R1 x 21 µA
2.5V x (R3 + R4)
R4
VOVL = 2.5V + [R3 x (2.5V - 21 PA)]
R4
VOVH =
VOV(HYS) = R3 x 21 µA
Option C: The minimum UVLO level is obtained by connecting the UVLO pin to VIN as shown in Figure 35. Q1
is switched on when the VIN voltage reaches the POREN threshold (≊8.4V). An external transistor can be
connected to UVLO to provide remote shutdown control, and to restart the LM5069-1 after a fault detection. The
OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B.
VSYS
VIN
21 PA
100k
LM5069
UVLO
2.5V
Shutdown/
Restart
Control
TIMER AND GATE
LOGIC CONTROL
R3
2.5V
R4
OVLO
21 PA
GND
Figure 35. UVLO = POREN with Shutdown/Restart Control
Option D: The OVLO function can be disabled by grounding the OVLO pin. The UVLO thresholds are set as
described in Option B or Option C.
POWER GOOD PIN
During turn-on, the Power Good pin (PGD) is high until the voltage at VIN increases above ≊ 5V. PGD then
switches low, remaining low as the VIN voltage increases. When the voltage at OUT increases to within 1.25V of
the SENSE pin (VDS <1.25V), PGD switches high. PGD switches low if the VDS of Q1 increases above 2.5V. A
pull-up resistor is required at PGD as shown in Figure 36. The pull-up voltage (VPGD) can be as high as 80V, with
transient capability to 100V, and can be higher or lower than the voltages at VIN and OUT.
VPGD
R PG
LM5069
Power
Good
PGD
GND
Figure 36. Power Good Output
If a delay is required at PGD, suggested circuits are shown in Figure 37. In Figure 37a, capacitor CPG adds delay
to the rising edge, but not to the falling edge. In Figure 37b, the rising edge is delayed by RPG1 + RPG2 and CPG,
while the falling edge is delayed a lesser amount by RPG2 and CPG. Adding a diode across RPG2 (Figure 37c)
allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.
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VPGD
VPGD
VPGD
R PG1
LM5069
PGD
Power
Good
CPG
R PG1
R PG1
LM5069
R PG2
PGD
LM5069
Power
Good
CPG
GND
GND
a) Delay Rising Edge Only
b) Long delay at rising edge,
short delay at falling edge
PGD R PG2
Power
Good
C PG
GND
c) Short Delay at Rising Edge and
Long Delay at Falling Edge or
Equal Delays
Figure 37. Adding Delay to the Power Good Output Pin
Design-in Procedure
The recommended design-in procedure is as follows:
• Determine the current limit threshold (ILIM). This threshold must be higher than the normal maximum load
current, allowing for tolerances in the current sense resistor value and the LM5069 Current Limit threshold
voltage. Use Equation 1 to determine the value for RS.
• Determine the maximum allowable power dissipation for the series pass FET (Q1), using the device’s SOA
information. Use Equation 2 to determine the value for RPWR.
• Determine the value for the timing capacitor at the TIMER pin (CT) using Equation 3. The fault timeout period
(tFAULT) must be longer than the circuit’s turn-on-time. The turn-on time can be estimated using the equations
in the Turn-on Time section of this data sheet, but should be verified experimentally. Review the resulting
insertion time, and restart timing if the LM5069-2 is used.
• Choose option A, B, C, or D from the UVLO, OVLO section of the Application Information for setting the
UVLO and OVLO thresholds and hysteresis. Use the procedure for the appropriate option to determine the
resistor values at the UVLO and OVLO pins.
• Choose the appropriate voltage, and pull-up resistor, for the Power Good output.
PC Board Guidelines
The following guidelines should be followed when designing the PC board for the LM5069:
• Place the LM5069 close to the board’s input connector to minimize trace inductance from the connector to the
FET.
• Place a small capacitor (1000 pF) directly adjacent to the VIN and GND pins of the LM5069 to help minimize
transients which may occur on the input supply line. Transients of several volts can easily occur when the
load current is shut off.
• The sense resistor (RS) should be close to the LM5069, and connected to it using the Kelvin techniques
shown in Figure 29.
• The high current path from the board’s input to the load (via Q1), and the return path, should be parallel and
close to each other to minimize loop inductance.
• The ground connection for the various components around the LM5069 should be connected directly to each
other, and to the LM5069’s GND pin, and then connected to the system ground at one point. Do not connect
the various component grounds to each other through the high current ground line.
• Provide adequate heat sinking for the series pass device (Q1) to help reduce stresses during turn-on and
turn-off.
• The board’s edge connector can be designed to shut off the LM5069 as the board is removed, before the
supply voltage is disconnected from the LM5069. In Figure 38 the voltage at the UVLO pin goes to ground
before VSYS is removed from the LM5069 due to the shorter edge connector pin. When the board is inserted
into the edge connector, the system voltage is applied to the LM5069’s VIN pin before the UVLO voltage is
taken high.
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5069
21
LM5069
SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013
www.ti.com
GND
VSYS
To
Load
RS
Q1
SENSE GATE
OUT
VIN
UVLO PGD
OVLO PWR
GND TIMER
R1
R2
R3
LM5069
PLUG-IN CARD
CARD EDGE
CONNECTOR
Figure 38. Recommended Board Connector Design
System Considerations
A) Continued proper operation of the LM5069 hot swap circuit requires capacitance be present on the supply
side of the connector into which the hot swap circuit is plugged in, as depicted in Figure 23. The capacitor in the
“Live Backplane” section is necessary to absorb the transient generated whenever the hot swap circuit shuts off
the load current. If the capacitance is not present, inductance in the supply lines will generate a voltage transient
at shut-off which can exceed the absolute maximum rating of the LM5069, resulting in its destruction.
B) If the load powered via the LM5069 hot swap circuit has inductive characteristics, a diode is required across
the LM5069’s output. The diode provides a recirculating path for the load’s current when the LM5069 shuts off
that current. Adding the diode prevents possible damage to the LM5069 as the OUT pin will be taken below
ground by the inductive load at shutoff. See Figure 39.
RS
VSYS
Q1
VOUT
+48V
LIVE
BACKPLANE
OUT
VIN
LM5069
CL
Inductive
Load
GND
GND
PLUG-IN BOARD
Figure 39. Output Diode Required for Inductive Loads
22
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LM5069
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LM5069MM-1/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SNAB
LM5069MM-2
ACTIVE
VSSOP
DGS
10
1000
TBD
Call TI
Call TI
-40 to 125
SNBB
LM5069MM-2/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SNBB
LM5069MMX-1
ACTIVE
VSSOP
DGS
10
3500
TBD
Call TI
Call TI
-40 to 125
SNAB
LM5069MMX-1/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SNAB
LM5069MMX-2
ACTIVE
VSSOP
DGS
10
3500
TBD
Call TI
Call TI
-40 to 125
SNBB
LM5069MMX-2/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
SNBB
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
23-May-2013
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LM5069MM-1/NOPB
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5069MM-2
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5069MM-2/NOPB
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5069MMX-1
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5069MMX-1/NOPB
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5069MMX-2
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM5069MMX-2/NOPB
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-May-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM5069MM-1/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM5069MM-2
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM5069MM-2/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
LM5069MMX-1
VSSOP
DGS
10
3500
367.0
367.0
35.0
LM5069MMX-1/NOPB
VSSOP
DGS
10
3500
367.0
367.0
35.0
LM5069MMX-2
VSSOP
DGS
10
3500
367.0
367.0
35.0
LM5069MMX-2/NOPB
VSSOP
DGS
10
3500
367.0
367.0
35.0
Pack Materials-Page 2
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