ALSC ASM5I9774AG-52-ER 2.5v or 3.3v, 200-mhz, 12-output zero delay buffer Datasheet

ASM5I9774A
June 2005
rev 0.3
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Features
The ASM5I9774A features two reference clock inputs and
ƒ
Output frequency range: 8.3MHz to 125MHz
provides 14 outputs partitioned in 3 banks of 5, 5, and 4
ƒ
Input frequency range: 4.2MHz to 62.5MHz
outputs. Bank A and Bank B divide the VCO output by 4 or
ƒ
2.5V or 3.3V operation
8 while Bank C divides by 8 or 12 per SEL(A:C) settings,
ƒ
Split 2.5V/3.3V outputs
see Functional Table. These dividers allow output to input
ƒ
14 Clock outputs: Drive up to 28 clock lines
ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each
ƒ
1 Feedback clock output
LVCMOS compatible output can drive 50Ω series or
ƒ
2 LVCMOS reference clock inputs
parallel
ƒ
150 pS max output-output skew
terminated transmission lines, each output can drive one or
ƒ
PLL bypass mode
two traces giving the device an effective fanout of 1:28.
ƒ
‘SpreadTrak’
The PLL is ensured stable given that the VCO is configured
ƒ
Output enable/disable
to run between 200 MHz to 500 MHz. This allows a wide
ƒ
Pin compatible with MPC9774 and CY29774AI.
range of output frequencies from 8.3 MHz to 125 MHz. For
ƒ
Industrial temperature range: –40°C to +85°C
normal operation, the external feedback input, FB_IN, is
ƒ
ƒ
52Pin 1.0mm TQFP package
connected to the feedback output, FB_OUT. The internal
RoHS Compliance
VCO is running at multiples of the input reference clock set
terminated
transmission
lines.
For
series
by the feedback divider, see Frequency Table.
Functional Description
When PLL_EN is LOW, PLL is bypassed and the reference
The ASM5I9774A is a low-voltage high-performance
clock directly feeds the output dividers. This mode is fully
125MHz PLL-based zero delay buffer designed for high-
static and the minimum input clock frequency specification
speed clock distribution applications.
does not apply.
Block Diagram
VCO_SEL
PLL_EN
TCLK_SEL
TCLK0
TCLK1
FB_IN
+2
PLL
200500MHZ
+2/+4
+4
CLK
STOP
QA0
QA1
QA2
QA3
QA4
SELA
+2/+4
CLK
STOP
+4/+6
CLK
STOP
SELB
QB0
QB1
QB2
QB3
QB4
QC0
QC1
SELC
QC2
QC3
CLK_STP#
+4/+6/+8/+12
FB_OUT
FB_SEL(1.0)
MR#/OE
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
ASM5I9774A
June 2005
rev 0.3
VSS
1
QB0
VDDQB
VSS
NC
QC3
VDDQC
QC2
VSS
QC1
VDDQC
QC0
VSS
VCO_SEL
Pin Configuration
52 51 50 49 48 47 46 45 44 43 42 41 40
39
VSS
MR#/OE
2
38
QB1
CLK_STP#
3
37
VDDQB
SELB
4
36
QB2
SELC
5
35
VSS
PLL_EN
6
34
QB3
ASM5I9774A
SELA
7
33
VDDQB
TCLK_SEL
8
32
QB4
TCLK0
9
31
FB_IN
TCLK1
10
30
VSS
NC
11
29
FB_OUT
VDD
12
28
VDDFB
AVDD
13
27
NC
VDDQA
QA0
VSS
QA1
VDDQA
QA2
FB_SEL1
QA3
VSS
VDDQA
QA4
AVSS
FB_SEL0
14 15 16 17 18 19 20 21 22 23 24 25 26
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
2 of 12
ASM5I9774A
June 2005
rev 0.3
Pin Description1
Pin
Name
I/O
Type
Description
9
TCLK0
I, PD
LVCMOS
LVCMOS/LVTTL reference clock input
10
TCLK1
I, PU
LVCMOS
LVCMOS/LVTTL reference clock input
16, 18,
21, 23, 25
QA(4:0)
O
LVCMOS
Clock output bank A
32, 34,
36, 38, 40
QB(4:0)
O
LVCMOS
Clock output bank B
44, 46,
48, 50
QC(3:0)
O
LVCMOS
Clock output bank C
29
FB_OUT
O
LVCMOS
Feedback clock output. Connect to FB_IN for normal operation.
31
FB_IN
I, PU
LVCMOS
Feedback clock input. Connect to FB_OUT for normal operation.
This input should be at the same voltage rail as input reference
clock. See Table 1.
2
MR#/OE
I, PU
LVCMOS
Output enable/disable input. See Table 2.
3
CLK_STP#
I, PU
LVCMOS
Clock stop enable/disable input. See Table 2.
6
PLL_EN
I, PU
LVCMOS
PLL enable/disable input. See Table 2.
8
TCLK_SEL
I, PD
LVCMOS
Reference select input. See Table 2.
52
VCO_SEL
I, PD
LVCMOS
VCO divider select input. See Table 2.
7, 4, 5
SEL(A:C)
I, PD
LVCMOS
Frequency select input, Bank (A:C). See Table 3.
20, 14
FB_SEL(1,0)
I, PD
LVCMOS
Feedback dividers select input. See Table 4.
17, 22, 26
VDDQA
Supply
VDD
2.5V or 3.3V Power supply for bank A output clocks2,3
33, 37, 41
VDDQB
Supply
VDD
2.5V or 3.3V Power supply for bank B output clocks2,3
45, 49
VDDQC
Supply
VDD
2.5V or 3.3V Power supply for bank C output clocks2,3
28
VDDFB
Supply
VDD
2.5V or 3.3V Power supply for feedback output clock2,3
13
AVDD
Supply
VDD
2.5V or 3.3V Power supply for PLL2,3
12
VDD
Supply
VDD
2.5V or 3.3V Power supply for core and inputs2,3
15
AVSS
Supply
Ground
Analog Ground
1, 19, 24,
30, 35,
39, 43,
47, 51
VSS
Supply
Ground
Common Ground
11, 27, 42
NC
No Connection
Note: 1.PU = Internal pull up, PD = Internal pull down.
2.A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the
pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
3.AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB
power supply pins
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
3 of 12
ASM5I9774A
June 2005
rev 0.3
‘SpreadTrak’
When a zero delay buffer is not designed to pass the
Many systems being designed now utilize a technology
called Spread Spectrum Frequency Timing Generation.
Spread Spectrum feature through, the result is a
ASM59774A is designed so as not to filter off the Spread
significant amount of tracking skew which may cause
Spectrum feature of the Reference Input, assuming it
problems in the systems requiring synchronization.
exists.
Table 1. Frequency Table
Feedback Output
Divider
VCO
Input Frequency Range
(AVDD = 3.3V)
Input Frequency Range
(AVDD = 2.5V)
÷8
Input Clock * 8
25 MHz to 62.5 MHz
25 MHz to 50 MHz
÷12
Input Clock * 12
16.6 MHz to 41.6 MHz
16.6 MHz to 33.3 MHz
÷16
Input Clock * 16
12.5 MHz to 31.25 MHz
12.5 MHz to 25 MHz
÷24
Input Clock * 24
8.3 MHz to 20.8 MHz
8.3 MHz to 16.6 MHz
÷32
Input Clock * 32
6.25 MHz to 15.625 MHz
6.25 MHz to 12.5 MHz
÷48
Input Clock * 48
4.2 MHz to 10.4 MHz
4.2 MHz to 8.3 MHz
Table 2. Function Table (configuration controls)
Control
Default
0
1
TCLK_SEL
0
TCLK0
TCLK1
VCO_SEL
0
VCO÷2 (high input frequency range)
VCO÷4 (low input frequency range)
PLL_EN
1
PLL enabled. The VCO output
connects to the output dividers
MR#/OE
1
CLK_STP#
1
Bypass mode, PLL disabled. The input clock
connects to the output dividers
Outputs disabled (three-state) and reset of the
device. During reset/output disable the PLL
feedback loop is open and the VCO running at its
minimum frequency. The device is reset by the
internal power-on reset (POR) circuitry during
power-up.
QA, QB, and QC outputs disabled in LOW state.
FB_OUT is not affected by CLK_STP#.
Outputs enabled
Outputs enabled
Table 3. Function Table (Bank A, B and C)
VCO_SEL
SELA
QA(4:0)
SELB
QB(4:0)
SELC
QC(3:0)
0
0
÷4
0
÷4
0
÷8
0
1
÷8
1
÷8
1
÷12
1
0
÷8
0
÷8
0
÷16
1
1
÷16
1
÷16
1
÷24
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
4 of 12
ASM5I9774A
June 2005
rev 0.3
Table 4. Function Table (FB_OUT)
VCO_SEL
FB_SEL1
FB_SEL0
FB_OUT
0
0
0
÷8
0
0
1
÷16
0
1
0
÷12
0
1
1
÷24
1
0
0
÷16
1
0
1
÷32
1
1
0
÷24
1
1
1
÷48
Absolute Maximum Conditions
Parameter
Description
VDD
DC Supply Voltage
VDD
DC Operating Voltage
Condition
Min
Max
Unit
–0.3
5.5
V
Functional
2.375
3.465
V
VIN
DC Input Voltage
Relative to VSS
–0.3
VDD+ 0.3
V
VOUT
DC Output Voltage
Relative to VSS
–0.3
VDD+ 0.3
V
VTT
Output termination Voltage
-
VDD ÷2
V
LU
Latch Up Immunity
Functional
200
-
mA
RPS
Power Supply Ripple
Ripple Frequency < 100 kHz
-
150
mVp-p
TS
Temperature, Storage
Non Functional
–65
+150
°C
TA
Temperature, Operating Ambient
Functional
–40
+85
°C
TJ
Temperature, Junction
Functional
-
150
°C
ØJC
Dissipation, Junction to Case
Functional
-
23
°C/W
ØJA
Dissipation, Junction to Ambient
Functional
-
55
°C/W
-
Volts
ESDH
FIT
ESD Protection (Human Body Model)
Failure in Time
2000
Manufacturing test
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
10
ppm
5 of 12
ASM5I9774A
June 2005
rev 0.3
DC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)
Parameter
Description
Condition
Min
Typ
Max
Unit
-
-
0.7
V
1.7
1.8
-
-
VDD+0.3
0.6
–100
V
V
V
µA
VIL= VDD
-
-
100
µA
PLL Supply Current
AVDD only
-
5
10
mA
Quiescent Supply Current
All VDD pins except AVDD
-
-
8
mA
IDD
Dynamic Supply Current
Outputs loaded @ 100 MHz
-
135
-
mA
CIN
Input Pin Capacitance
ZOUT
Output Impedance
VIL
Input Voltage, Low
LVCMOS
VIH
VOL
VOH
IIL
Input Voltage, High
Output Voltage, Low1
Output Voltage, High1
Input Current, Low2
LVCMOS
IOL= 15mA
IOH= –15mA
VIL= VSS
IIH
Input Current, High2
IDDA
IDDQ
-
4
-
pF
14
18
22
Ω
Note: 1. Driving one 50Ωparallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output
terminated transmission lines
2. Inputs have pull-up or pull-down resistors that affect the input current.
drives up to two 50 Ωseries-
DC Electrical Specifications (VDD= 3.3V ± 5%, TA= –40°C to +85°C)
Parameter
Description
Condition
Min
Typ
Max
Unit
VIL
Input Voltage, Low
LVCMOS
-
-
0.8
V
VIH
Input Voltage, High
LVCMOS
2.0
-
VDD + 0.3
V
VOL
Output Voltage, Low1
IOL= 24 mA
-
-
0.55
VOH
IIL
Output Voltage, High1
Input Current, Low2
IOL= 12 mA
IOH= –24 mA
VIL= VSS
2.4
-
-
0.30
–100
V
µA
IIH
Input Current, High2
VIL= VDD
-
-
100
µA
IDDA
PLL Supply Current
AVDD only
-
5
10
mA
IDDQ
Quiescent Supply Current
All VDD pins except AVDD
-
-
8
mA
IDD
Dynamic Supply Current
Outputs loaded @ 100 MHz
-
225
-
mA
CIN
Input Pin Capacitance
ZOUT
Output Impedance
V
-
4
-
pF
12
15
18
Ω
Note: 1. Driving one 50Ωparallel-terminated transmission line to a termination voltage of VTT. Alternatively, each output
terminated transmission lines
2. Inputs have pull-up or pull-down resistors that affect the input current.
drives up to two 50 Ωseries-
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
6 of 12
ASM5I9774A
June 2005
rev 0.3
AC Electrical Specifications (VDD = 2.5V ± 5%, TA = –40°C to +85°C)1
Parameter
fVCO
fin
Description
Min
Typ
Max
Unit
200
-
400
MHz
÷8 Feedback
25
-
50
÷12 Feedback
16.6
-
33.3
÷16 Feedback
12.5
-
25
÷24 Feedback
8.3
-
16.6
÷32 Feedback
6.3
-
12.5
÷48 Feedback
4.2
-
8.3
Bypass mode
(PLL_EN = 0)
0
-
200
25
-
75
%
0.7V to 1.7V
–
-
1.0
nS
÷4 Output
50
-
100
÷8 Output
25
-
50
÷12 Output
16.6
-
33.3
÷16 Output
12.5
-
25
÷24 Output
8.3
-
16.6
45
-
55
%
0.1
-
0.75
nS
–100
-
100
pS
-
-
150
pS
-
-
150
-
-
200
VCO Frequency
Input Frequency
frefDC
Input Duty Cycle
t r, t f
TCLK Input Rise/FallTime
fMAX
Condition
Maximum Output Frequency
DC
Output Duty Cycle
t r, t f
Output Rise/Fall times
0.7V to 1.8V
t(φ)
Propagation Delay
(static phase offset)
TCLK to FB_IN, does
not include jitter
tsk(O)
Output-to-Output Skew
Skew within Bank
Bank-to-Bank Skew
Banks at same
frequency
Banks at different
frequency
tsk(B)
MHz
MHz
pS
tPLZ, HZ
Output Disable Time
-
-
10
nS
tPZL, ZH
Output Enable Time
-
-
10
nS
BW
PLL Closed Loop Bandwidth
(–3 dB)
-
0.5 -1.0
-
MHz
tJIT(CC)
Cycle-to-Cycle Jitter
Same frequency
-
-
100
Multiple frequencies
-
-
250
tJIT(PER)
Period Jitter
-
-
100
pS
tJIT(φ)
I/O Phase Jitter
-
-
125
pS
tLOCK
Maximum PLL Lock Time
-
-
1
mS
pS
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
7 of 12
ASM5I9774A
June 2005
rev 0.3
AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)1
Parameter
Description
fVCO
VCO Frequency
fin
Input Frequency
Condition
Min
Typ
Max
Unit
200
-
500
MHz
÷8 Feedback
25
-
62.5
÷12 Feedback
16.6
-
41.6
÷16 Feedback
12.5
-
31.25
÷24 Feedback
8.3
-
20.8
÷32 Feedback
6.25
-
15.625
÷48 Feedback
4.2
-
10.4
Bypass mode
(PLL_EN = 0)
0
-
200
25
-
75
%
-
1.0
nS
MHz
frefDC
Input Duty Cycle
t r, t f
TCLK Input Rise/FallTime
0.8V to 2.0V
fMAX
Maximum Output Frequency
÷4 Output
50
-
125
÷8 Output
25
-
62.5
÷12 Output
16.6
-
41.6
÷16 Output
12.5
-
31.25
÷24 Output
8.3
-
20.8
45
-
55
%
1.0
nS
DC
Output Duty Cycle
tr, tf
Output Rise/Fall times
0.8V to 2.4V
t(φ)
Propagation Delay (static phase
offset)
TCLK to FB_IN, same
VDD, does not include jitter
tsk(O)
Output-to-Output Skew
tsk(B)
Bank-to-Bank Skew
0.1
MHz
–100
-
100
pS
Skew within Bank
-
-
150
pS
Banks at same voltage,
same frequency
-
-
150
Banks at same voltage,
different frequency
-
-
225
Banks at different voltage
-
-
250
pS
tPLZ, HZ
Output Disable Time
-
-
10
nS
tPZL, ZH
Output Enable Time
-
-
10
nS
BW
PLL Closed Loop Bandwidth
(–3dB)
Cycle-to-Cycle Jitter
-
0.5 - 1.0
-
MHz
Same frequency
-
-
150
Multiple frequencies
-
-
300
-
-
100
pS
-
-
150
pS
-
-
1
mS
tJIT(CC)
tJIT(PER)
Period Jitter
tJIT(φ)
I/O Phase Jitter
tLOCK
Maximum PLL Lock Time
I/O at same VDD
pS
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Outputs are at same supply voltage unless otherwise stated. Parameters are
guaranteed by characterization and are not 100% tested.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
8 of 12
ASM5I9774A
June 2005
rev 0.3
Zo = 50 ohm
Pulse
Generator
Z = 50 ohm
RT = 50 ohm
VTT
VTT
Figure 1. LVCMOS_CLK AC Test Reference for VDD = 3.3V/2.5V
VDD
LVCMOS_CLK
VDD/2
GND
VDD
VDD/2
t(φ)
GND
Figure 2. LVCMOS Propagation Delay t(φ), Static Phase Offset
VDD
VDD/2
GND
tP
T0
DC = tP / T0 x 100%
Figure 3. Output Duty Cycle (DC)
VDD
VDD/2
GND
VDD
VDD/2
tSK(0)
GND
Figure 4. Output-to-Output Skew, tsk(O)
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
9 of 12
ASM5I9774A
June 2005
rev 0.3
Package Information
52-lead TQFP Package
SECTION A-A
Dimensions
Symbol
Inches
Min
Max
Millimeters
Min
Max
A
….
0.0472
…
1.2
A1
0.0020
0.0059
0.05
0.15
A2
0.0374
0.0413
0.95
1.05
D
0.4646
0.4803
11.8
12.2
D1
0.3898
0.3976
9.9
10.1
E
0.4646
0.4803
11.8
12.2
E1
0.3898
0.3976
9.9
10.1
L
0.0177
0.0295
0.45
0.75
L1
0.03937 REF
1.00 REF
T
0.0035
0.0079
0.09
0.2
T1
0.0038
0.0062
0.097
0.157
b
0.0102
0.0150
0.26
0.38
b1
0.0106
0.0130
0.27
0.33
R0
0.0031
0.0079
0.08
0.2
a
0°
7°
0°
7°
e
0.0256 BASE
0.65 BASE
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
10 of 12
ASM5I9774A
June 2005
rev 0.3
Ordering Information
Part Number
Marking
Package Type
Operating Range
ASM5I9774A-52-ET
ASM5I9774A
52-pin TQFP, Tray
Industrial
ASM5I9774A-52-ER
ASM5I9774A
52-pin TQFP – Tape and Reel
Industrial
ASM5I9774AG-52-ET
ASM5I9774AG
52-pin TQFP, Tray, Green
Industrial
ASM5I9774AG-52-ER
ASM5I9774AG
52-pin TQFP – Tape and Reel, Green
Industrial
Device Ordering Information
A S M 5 I 9 7 7 4 A G - 5 2 - E T
R = Tape & reel, T = Tube or Tray
O = SOT
S = SOIC
T = TSSOP
A = SSOP
V = TVSOP
B = BGA
Q = QFN
U = MSOP
E = TQFP
L = LQFP
U = MSOP
P = PDIP
D = QSOP
X = SC-70
DEVICE PIN COUNT
F = LEAD FREE AND RoHS COMPLIANT PART
G = GREEN PACKAGE
PART NUMBER
X= Automotive
I= Industrial
P or n/c = Commercial
(-40C to +125C) (-40C to +85C)
(0C to +70C)
1 = Reserved
2 = Non PLL based
3 = EMI Reduction
4 = DDR support products
5 = STD Zero Delay Buffer
6 = Power Management
7 = Power Management
8 = Power Management
9 = Hi Performance
0 = Reserved
ALLIANCE SEMICONDUCTOR MIXED SIGNAL PRODUCT
Licensed under US patent #5,488,627, #6,646,463 and #5,631,920.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
11 of 12
ASM5I9774A
June 2005
rev 0.3
Alliance Semiconductor Corporation
2575, Augustine Drive,
Santa Clara, CA 95054
Tel# 408-855-4900
Fax: 408-855-4999
www.alsc.com
Copyright © Alliance Semiconductor
All Rights Reserved
Part Number: ASM5I9774A
Document Version: 0.3
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to Alliance Semiconductor, dated 11-11-2003
© Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time without
notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein
represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this
data at any time, without notice. If the product described herein is under development, significant changes to these
specifications are possible. The information in this product data sheet is intended to be general descriptive information for
potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or
customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products
including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual
property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance).
All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of
products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any
other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical
components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant
injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer
assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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