Astec AIF04ZPFC-01NL Ac-dc converter module Datasheet

Technical Reference Note
AIF - PFC Power Factor
Correction Series
AIF - PFC 1600W AC-DC Converter Module
The PFC Power Factor Correction module is part of Astec’s family of advanced High Density modular power supply
components. Featuring high reliability and convenient control and monitoring functions, these modules are designed to
reduce product development time and enhance system performance. The PFC is designed to work over all typical line
voltages used worldwide, and provide unity power factor with very low levels of harmonic distortion in line current. The
PFC includes active start-up current control. Power Line Disturbance (PLD) circuitry copes with a wide range of input
voltage fluctuations..
Electrical Parameters
Input
Input range
85 – 264 VAC
120 - 370VDC (Configurable)
Input Surge
290Vac / 1s
Efficiency
95%@ 230Vac, 1600W (Typical)
Total Harmonic 10%
Distortion
Special Features
•
•
•
•
•
•
•
•
•
Unity Power Factor
DC input (Configurable)
High Efficiency - up to 95%
Universal input voltage and frequency range
Up to 1600W output power
Parallelable with current sharing within 10%
< 10% harmonic distortion conforming to IEC 10003-2 Compliance
100°C baseplate operating temperature.
High Reliability - over 1 million hours MTBF
@ baseplate temperature 50°C
Programmable Power Fail Warning Signal
EEPROM data storage via I2C interface
Power Density up to 290W/in3
•
•
•
• Switching Frequency 125KHz
Environmental Specifications
• Operating temperature: -20°C to +100°C (baseplate)
• Storage temperature: -40°C to +110°C
• Meet power line disturbance immunity specification
per IEC 61000-4-11 “ Generic Immunity Standards
against voltage dips, interruptions”
• Pb-free reflow compatible and ROHS Compliant
Control
Enable TTL compatible
(Positive & negative enable options)
Output
Output Voltage
Io =4.2A / Vi > 180Vac
Io = 0
380V typ
393V typ
Maximum output Power
85Vac ≤ Vin ≤ 120Vac 1000W
120Vac < Vin < 220Vac See P. 16
1600W
Vin ≥ 220Vac
Output voltage
Adjust range
76% - 100% of nominal
output
Overvoltage Protection 430V
Safety
UL, cUL
TUV
60950 Recognized
EN60950 Licensed
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AIF - PFC Power Factor
Correction Series
AIF - PFC SERIES
THIS SPECIFICATION COVERS THE REQUIREMENTS
FOR A New Full Brick 1600W AC/DC Converter
MODEL NAME
AIF04ZPFC-01L
AIF04ZPFC-01NL
AIF04ZPFC-02L
AIF04ZPFC-02NL
AIF04ZPFC-01NTL
AIF04ZPFC-01NNTL
AIF04ZPFC-02NTL
AIF04ZPFC-02NNTL
Vout,Iout
380V, 4.2A
380V, 4.2A
380V, 4.2A
380V, 4.2A
380V, 4.2A
380V, 4.2A
380V, 4.2A
380V, 4.2A
* 1600W max
Suffix
NL
L
NTL
Option
Negative Logic Enable
Positive Logic Enable
Non-thread hole
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AIF - PFC Power Factor
Correction Series
Electrical Specifications
Unless otherwise indicated, specifications apply over all operating input voltage and temperature conditions.
Standard test condition on a single unit.
Tambient:
L1:
L2:
Enable:
+Vout1:
−Vout1:
Trim(Vadj):
Output Cap:
25°C
115Vac, 220Vac
return pin for L1
Open
connect to load
connect to load (return)
connect to S GND
470uF x 2
ABSOLUTE MAXIMUM RATINGS
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute
stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of
those given in the operational sections of the specs. Exposure to absolute maximum ratings for extended periods
can adversely affect device reliability.
Parameter
Device
Symbol
Min
Typ
Max
Unit
Input Voltage:
Continuous:
Surge Voltage (1 sec)
All
All
VI
VI
85
-
264
290
Vac
Vac
Input Frequency
Operating Case Temperature
All
Tc
47
-20
50/60
-
63
100
Hz
ºC
Start up Case Temperature
All
100
ºC
Storage Temperature
All
TSTG
-40
-
110
ºC
Operating Humidity
All
-
-
-
95
%
All
-
-
-
2700
2700
1300
Vdc
Vdc
PF
Isolation
Input to Baseplate
Output to Baseplate
Baseplate Capacitance
-40
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AIF - PFC Power Factor
Correction Series
CONTROL SIGNALS
Control Function
TEMP MON - temperature
monitor signal
V ADJ - voltage adjust*
C MON - current monitor
signal
C SHARE - current share
function**
CLK OUT - clock output
Conditions
Adjust using external resistor
IO = 4.2A
IO = 20 to 100% IOrated
C SHARE pins of modules in
parallel connected
CLK IN open
CLK IN - clock input
PFWADJ - power fail
warning adjust
PFWADJ=0 to 2.05 VDC
PFWADJ=3.2 VDC
PFWADJ = 3.40VDC
PFW- power fail warning***
Input Power OK, IPFW = 0
Input Power Fail, IPFW = 15mA
(PFWshort to S_GND)
Load enabled, (ILD ENABLE = 0)
Load disabled, (ILD ENABLE = 15mA)
LD ENABLE short to S_GND
Negative Enable:
Module enabled
Module disabled
Positive Enable:
Module enabled
Module disabled
VENABLE = 0.8V
IPV_AUX = 0A
IPV_AUX = 20mA
LD ENABLE - load enable
PF ENABLE - module
enable***
PV_AUX***
Parameter
VTEMP MON Sensitivity
Source impedence
Vo
IC MON
IO/IC MON
C SHARE accuracy
Max no. of units
VCLK OUT
Clock freq.
Max fan out
VCLK IN
Clock freq
PFWset point
PFWset point
PFWset point
PFW ADJ current source
VPFW
VPFW
PFWcurrent source
VLD ENABLE
VLD ENABLE
LD ENABLE current source
Min
9.8
VPF ENABLE
VPF ENABLE
VPF ENABLE
VPF ENABLE
PF ENABLE current source
PV_AUX Voltage
PV_AUX Voltage
60
0.9
0.97
4.5
0.95
195
305
325
Typ
10
16
1
4.2
? %
5
1
Max
10.2
100
1.1
? 0
10
1.03
2
6
1.05
215
335
355
KΩ
% VOnom
mA
A/mA
%IO rated
Vp-p
MHz
15
0.4
15
0.4
-
Vp-p
MHz
VDC
VDC
VDC
mA
V
V
mA
V
V
mA
0
2.2
0.8
5
V
V
2.2
0
5
0.8
V
V
µA
V
V
12
0
–
12
0
–
1
205
320
340
1
13.7
0.2
2.9
13.7
0.2
2.9
400
11
9
8
* PFWis not valid when using voltage adjust feature
** For AIF04ZPFC-01L, total input current of all the modules must not exceed 16A rms
*** Only apply on primary side
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Units
mV/°C
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Correction Series
INPUT SPECIFICATIONS
Parameter
Operating Input Voltage
Device
Symbol
Min
All
VI
85
II,max
-
Input Current
(VI = 115Vac, Load = 1000W)
Inrush Transient
(Need external inrush limiting
circuit)
Power Factor
No Load Input Power
(VI = VI,nom )
Total Harmonic Distortion
(IEC1000-3-2)
Typ
-
-
Po ≥ 500W
Po ≥ 1000W
All
All
Max
Unit
264
VAC
10
A
20
Apk
-
0.96
0.98
-
0.97
0.99
-
3.8
W
-
-
-
10
%
Note:
1)
2)
3)
4)
5)
6)
Half cycle surge current due to input transient surge must be limited to 20A peak or less
Need external inrush limiting circuit
For AIF04ZPFC-01L, total input current for modules connected in parallel must not exceed 16A
For AIF04ZPFC-02L, negative rail input rectifiers must be provided by external circuitry. See P.24
Total harmonic distortion – input harmonics meet the requirements of IEC 1000-3-2
The PFC’s LD ENABLE signal is recommended to be used to enable the load in case of initial surge load condition
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Correction Series
OUTPUT SPECIFICATIONS
Parameter
Output Voltage
Io = 4.2A / VI > 180V
Io = 0
Device
Symbol
Min
Typ
Max
Unit
370
380
393
400
V
V
Maximum output power
For 85Vac ≤ VI ≤ 120Vac
For VI > 220 Vac
For 120Vac < VI < 220Vac
1000
1600
See P.17
W
W
Efficiency
VI = 115Vac, (1000W)
VI = 230Vac, (1000W)
VI = 230Vac, (1600W)
90
92
92
92
94
95
VI = 115Vac
VI = 230Vac
0.5
0.5
2.5
2.5
External Output Capacitor
470
%
%
%
Turn-On Time
4.0
3.5
Sec
Sec
3000
µF
Max
-
Unit
Hours
GENERAL SPECIFICATIONS
Parameter
Calculated MTBF (Io = 2.6A ; TB =
40°C, MIL-217FN2)
Weight
Device
All
Symbol
-
Min
-
Typ
450K
All
-
-
300 (9.6)
g(oz.)
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AIF - PFC Power Factor
Correction Series
FEATURE SPECIFICATIONS
Parameter
PF ENABLE Interface :
Device
Symbol
Min
Typ
Max
Unit
Positive Logic – No suffix
Low Logic – Module Off
High Logic – Module On
Negative Logic – Suffix “N”
Low Logic – Module On
High Logic – Module Off
All
All
Venable
Venable
0
2
0.8
5
V
V
All
All
Venable
Venable
0
2
0.8
5
V
V
Enable current source
(Venable = 0.8V)
All
400
µA
100
%Vo
430
V
Output Voltage Adjustment Range
Output Overvoltage Shutdown
(latch off)
-
All
76
420
Output ripple
-
11
Vin = 115Vac, Vo = 380V, Io = 2.6A
Vp-p
Undervoltage Lockout
Turn-on Point
Turn-off Point
All
All
-
79
57
84.5
62
V
V
105
120
°C
Overtemperature shutdown
(Baseplate temperature)
All
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AIF - PFC Power Factor
Correction Series
Function Description
This section explains how to implement the functions found on the AIF - PFC Series. All signals are on primary side.
PFC Enable Input (PF ENABLE)
The enable pin is a TTL compatible input used to turn the output of the module on or off.
For module with no suffix, the output is enabled when the PF ENABLE (pin 16) is open or driven to a logic high > 2.2V.
The output is disabled when the PF ENABLE is connected to S GND (pin 13) or driven to a logic low of < 0.8V (but not
negative).
For module with suffix “N”, the output is enabled when the PF ENABLE is connected to S GND or driven to a logic low <
0.8V (but not negative). The output is disabled when the PF ENABLE is open or driven to a logic high > 2.2V.
+O/P
+O/P
1
8
16
9
-O/P
PF ENABLE
PF ENABLE
S GND
9
1
S GND
8
16
-O/P
S GND (Signal Ground)
The S GND pin is connected to the internal common ground of the module. It is also internally connected to the –O/P
terminals.
NOTE:
When connecting S GND to external circuitry care must be taken to ensure that the current flowing through this pin is kept
below 25mA.
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Correction Series
DC-DC Converter Module Enable Output (LD ENABLE)
After the PFC power up sequence, the power to the load can be enabled. This can be performed manually or the PFC can
automatically enable the load using the LD ENABLE signal.
Depends on external inrush current limit circuit
Output stabilized
OUTPUT
VOLTAGE
HIGH
t on
LD
ENABLE
LOW
Initially the load is disabled and the LD ENABLE (pin 15) is at 0.4V (LOW). When the PFC power up sequence has
completed, the LD ENABLE voltage goes HIGH. And the LD ENABLE will stay high as long as Vin is above 175Vac or
Vout is above 250V, even if PF_ENABLE is in disable mode. (Please see the application example section at P.25 for the
external circuit to interlock the LD-ENABLE from PF_ENABLE)
The LD ENABLE pin is capable of delivering 2.7mA at 1.5V when HIGH. See electrical specifications for exact figures.
Power Fail Warning
If output voltage can not be maintained at the pre-programmed PFW threshold voltage, the PFW (pin 14) will go from
HIGH to LOW.
INPUT
VOLTAGE
PFWThreshold
OUTPUT
VOLTAGE
PFW
The output of the PFW signal can drive an opto-coupler to provide an isolated signal from primary side to the secondary
side. The nominal factory set PFW threshold is set at 340V.
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Correction Series
Power Fail Warning Adjust
The level at which a Power Fail Warning occurs can be programmed using the PFW Adjust input (pin 12). If the pin is left
unconnected then the PFW operates at the default factory set value.
The output from the PFW ADJ pin is a 1mA current source. To adjust the PFW threshold, a voltage source (0 – 4Volts) or a
programming resistance (0 – 4Kohm) referenced to s S GND (pin 13) should be connected. This allows adjustment of the
PFW threshold from 280V up to 340V. The value of resistance or voltage required can be read from the graph above.
Clock Signals (CLK IN, CLK OUT)
The PFC’s internal clock is accurate and stable over its full operating range and synchronization is not normally required,
but it can reduce noise in paralleled systems.
Clock signals can be wired in series (the CLK OUT pin of one module to the CLK IN pin of the next etc) in which case all
the modules will be synchronized with the first module in the chain. Alternatively, an external clock signal of TTL level at
1MHz ± 10% can be connected to the CLK IN pins of all the modules.
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Correction Series
From CLK OUT of
previous module
To CLK IN of
next module
+O/P
+O/P
8
1
8
1
9
16
9
16
-O/P
-O/P
From SGND of
previous module
To S GND of
next module
If the clock input to any module fails, the module will automatically switch back to its internal clock and will continue to
operate at full power even in current sharing systems.. The CLK IN and CLK OUT signals are AC coupled.
Temperature Monitoring (TEMP MON)
The TEMP MON pin provides an indication of the module’s internal temperature. The voltage at the TEMP MON pin is
proportional to the temperature of the module baseplate at 10mV per °C, where:
Module temperature (°C) = (Vtemp mon X 100) - 273
The temperature monitor signal can be used by thermal management systems (e.g. to control a variable speed fan). It can
also be used for overtemperature warning circuits and for thermal design verification of prototype power supplies and
heatsink.
3.73V
3.48V
VTEMP MON
3.23V
2.98V
2.73V
2.53V
-20 ∞C 0∞C
50∞C
100∞C
Module internal temperature
+O/P
8
1
9
16
-O/P
V
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Correction Series
Current Monitoring (C MON)
The C MON pin provides an indication of the amount of current supplied by the module. The output of the C MON pin is a
current source proportional to the output current of the module,
IO / I CMON = 4.2A/1mA
where
If a 4.2K Ohm resistor is connected then the voltage in Volts on the C MON pin is directly equivalent to the current supplied
by the module in Amps.
Maximum voltage on C MON is 6V
1.25mA
1.28mA
1.00mA
ICMON
0.75mA
0.50mA
0.25mA
0.00mA
0
2.1A
4.2A
5.4A
IO
0-1mA
+O/P
8
1
9
16
-O/P
4.2Kohm max
V
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Correction Series
Current Sharing (C SHARE)
To ensure that all modules in a parallel system accurately share current, the C SHARE pins on each module should be
connected together.
From C SHARE of
previous module
To C SHARE of
next module
+O/P
+O/P
8
1
8
1
9
16
9
16
-O/P
From S GND of
previous module
-O/P
To S GND of
next module
The voltage on the C SHARE pins represents the average load current per module. Each module compares this average with
its own current and adjusts its output voltage to correct the error. In this way the module maintains accurate current sharing
even under variable or light load conditions.
Note: 1) The S GND pins of each module must also be connected together to ensure accurate current sharing.
2) Current flow to S GND must less than 25mA
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Correction Series
Output Voltage Adjust (V ADJ)
The output voltage of the module may be accurately adjusted from 76% to 100% of the nominal output voltage. Adjustment
can be made using a resistor connected as below.
V -a d j v alu e c h a rt
40 0
39 0
38 0
37 0
V-out
36 0
35 0
34 0
33 0
32 0
31 0
30 0
1 .0
2 .3
5 .1
1 1 .4
2 5 .6
5 7 .7
12 9 .7
2 9 1.9
6 5 6.8
K -O h m
+O/P
8
1
9
16
-O/P
R
Vout = Vr * (1 + Rh * ( 1 / (Rj + R) + 1 / Rw)) + 10.94
Where
R is the resistor connected between the Vadj pin to S_GND (units in kOhm)
Vr = 5.029
Rh = 1084
Rw = 19.2
Rj = 58.5
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Correction Series
DC ENABLE
+O/P
8
S GND
DC ENABLE
9
1
16
-O/P
For using DC input, connect the DC ENABLE pin to S GND
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Correction Series
I2C EEPROM Content Programming (SDA, SCL)
This function is provided for product information storage, template as per customer define.
Connect RS232 (Printer Port) from PC to Test unit at 300Vdc in and test with Read/Write capability of the I2C EEPROM.
P in 2
P in 5
P in 8
P in 12
P in 13
P in 1 8 to 25
EEPROM CONTENT
The module is equipped with a 256 byte EEPROM, 24LC2BT-E/ST or equivalent. This device will be programmed during
the manufacturing process. The EEPROM content will include the following information:
-
Manufacturer name string “ ASTEC”
Product name and product number
Serial number assigned by manufacturer
Max output power
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Correction Series
DESIGN CONSIDERATIONS
Maximum Output Power Vs Input Voltage
The maximum output power available varies with the input voltage as shown below.
1750
OUTPUT POWER (W)
1600
1500
1250
1000
1000
750
85
230
120
100
264
200
300
INPUT VOLTAGE (Vac)
Efficiency Vs Input Voltage and Output Power
Efficiency vs. Load Current
100
Efficiency [%]
95
85Vin
90
110Vin
230Vin
85
264Vin
80
75
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
Load [A]
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Correction Series
Input Undervoltage Protection
An input undervoltage protection circuit protects the module under low input voltage conditions. Hysteresis is built into the
PFC Series module to allow for high levels of variation on the input supply voltage without causing the module to cycle on
and off. PFC modules will operate when the input exceeds 85Vac and turn off below 63Vac.
Input Fusing
ASTEC modules do not have an in-line fuse fitted internally. In order to comply with CSA, VDE and UL safety regulations
it is recommended that a fuse of 250Vac, 15A be fitted at the module’s input.
Output Capacitor
The PFC requires an output hold-up capacitor of between 470uF and 3000uF to prevent the module from disabling due to
fluctuations in output voltage. Ideally the capacitor should be connected directly to the PFC output pins. If this is not
possible the connection must be less than 50mm from the pins.
+O/P
8
1
+
9
470 to
3000µF
Output
to load
16
-O/P
<50mm
Selecting an External Output Capacitor
The output capacitor value is determined by the following factors :
1. RMS ripple current.
2. Peak-to-peak output ripple voltage.
3. Hold-up time.
4. Expected lifetime of the capacitor.
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Correction Series
RMS ripple current
The maximum permissible rms ripple current for the output capacitor should be greater than the rms ripple current for the
application. The ripple current for the PFC module can be approximated as
Irms = (PO/Eff) x 1/√(VO x Vrms)
where :
PO = output power (W)
Eff = efficiency
VO = output voltage (V)
Vrms = input rms voltage (V)
This gives the ripple current at 125KHz. The maximum ripple current for capacitors is usually specified at 120Hz. To
convert from 125KHz to 120Hz the Irms figure should be divided by 1.3 .
Peak to Peak Output Ripple Voltage
The ac input causes a ripple on the output voltage. The size of the ripple is inversely proportional to the size of the capacitor.
Therefore the maximum allowable ripple voltage should be decided in order to calculate the size of capacitor required. This
may be calculated using the following equation:
CO = PO / (2πf x Eff x VO x Vripple)
where :
CO = output capacitance (µF)
Eff = efficiency
f = input voltage frequency (Hz)
VO = output voltage (V)
Vripple = output ripple voltage (V)
Hold-Up Time Requirement
The output capacitor value is different for different hold-up time requirements. The minimum capacitance corresponding to
the required hold-up time of a system comprised of ASTEC DC/DC power modules and an PFC module can be calculated as
follows:
CO min = (2 x PO x Thold)/[(VO-Vripple)2 - (Vmin)2]
where :
CO min = output capacitance (µF)
PO = output power (W)
Thold = hold up time (sec)
VO = output voltage (V)
Vripple = output ripple voltage (V)
Vmin = minimum input voltage for DC/DC module
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Correction Series
For example:
A PFC module driving 3 AIF80A300 400W modules @ 5V. Efficiency of the AIF80A300 module is 88%, the minimum
input voltage is 250V, the output voltage of the PFC is 380V, the required hold-up time is 20mS and the peak-to-peak
voltage Vripple is chosen to be 16V.
CO min = 2 x (3 x 400/0.88) x 0.02 = 390µF (470 µF ± 20%)
[(380-16)2-2502]
This figure is the minimum capacitance. To allow for capacitor tolerances and aging effects the actual value should
generally be around 1.5 times greater.
PF & Load Enable Connections and Timing
The PFC module must be supplied with a PF ENABLE signal to initiate the start-up sequence. The output of the LD
ENABLE pin goes HIGH (ON) once the PFC has completed the start-up sequence.
It is recommended that the LD ENABLE signals is always used to enable the load, however, if the load is to be enabled
manually it is essential that the ton time has expired before enabling occurs.
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Correction Series
Connections to enable Astec DC-DC converters.
The output from the PFC’s LD ENABLE (pin 13) can directly drive an opto-coupler to provide an isolated signal to enable
the power output of one or more Astec DC-DC converter modules.
Load Enable Connection for Astec DC-DC Converters
+O/P
8
1
9
16
-O/P
AIF04ZPFC
to ENABLE pin of DC-DC
converter module
to -SENSE PIN / S COM pin
of DC - DC converter module
General Connections to enable a load
For enabling loads other than Astec DC-DC converters the following circuit can be used. The LD ENABLE pin can directly
drive a MOSFET with a 15V zener clamping the gate voltage.
+O/P
1
9
16
LD ENABLE
8
-O/P
AIF04ZPFC
RESISTIVE
LOAD
D
S
G
IRFP450
Conducted EMI
The PFC modules will require additional EMI filtering to enable the system to meet relevant EMI standards.
PFC modules have an effective input to ground (baseplate) capacitance of 1600pF. This should be accounted for when
calculating the maximum EMI ‘Y’ capacitance to meet ground leakage current specifications. An example filter circuit is
shown below.
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
L1
982µH
L3 370µH
L2 13mH
L
0.47µF
275Vac
Xcap
0.47µF
275Vac
Xcap
N
L2
L1
1000pF
250Vac
Ycap
1000pF
250Vac
Ycap
220K
1µF
275Vac
Xcap
220K
0.47µF
275Vac
Xcap
L3
4700pF
250Vac
Ycap
ACINPUT
Baseplate
4700pF
250Vac
Ycap
E
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
APPLICATION EXAMPLE
PFC module input connection example:
Baseplate
L
L1
8
1
9
16
AC INPUT
L2
LD ENABLE
Inrush current limit
circuit
PF ENABLE
EMI filter
circuit
S GND
N
+O/P
-O/P
AIF04ZPFC
E
Model AIF04ZPFC-02L Parallel Operation
The AIF04ZPFC-02L has been specifically designed for paralleling applications where the total input current exceeds
16Arms. For stand-alone applications or those where the total input current does not exceed 16Arms the AIF04ZPFC-01L is
recommended.
The AIF04ZPFC-02L requires external negative rail rectifiers to be implemented at the input to the system. It is possible to
operate the AIF04ZPFC-02L as a stand-alone configuration although the external negative rail rectifiers must still be
provided.
Current Sharing
In multi-module paralleled systems, all modules will share current to within ± 10% of the average load current per module
when the C-SHARE pins of each module are connected together.
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
Interlock circuit between LD ENABLE and PF ENABLE (Continues from P.9, LD
ENABLE)
Initially the load is disabled and the LD ENABLE (pin 15) is at 0.4V (LOW). When the PFC power up sequence has
completed, the LD ENABLE voltage goes HIGH. And the LD ENABLE will stay high as long as Vin is above 175Vac or
Vout is above 250V, even if PF_ENABLE is in disable mode. If the application needs the LD_EN goes low when the
PF_EN is disable, please use the following interlock circuitry.
LD_EN goes low when PF_EN is set low (AIF04ZPFC-01L)
LD_EN goes low when PF_EN is set high (AIF04ZPFC-01NL)
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
Synchronization
Modules are synchronized by connecting the CLK OUT pin of one module to the CLK IN of the next module in an open
daisy chain configuration. If the clock input to a module fails it will automatically revert to its internal clock and continue to
operate at full power.
L1
+O/P
C SHARE
CLK OUT
8
1
+
9
S GND
AC INPUT
85 to 264 Vac
L2
16
Output to
Astec DC-DC
Modules of
other loads
-O/P
AIF04ZPFC-02
External Diode Pair *
L1
+O/P
C SHARE
CLK IN
1
8
+
9
L2
S GND
AC INPUT
16
-O/P
AIF04ZPFC-02
* The current rate requirement of external rectifier for each line is 20A x number of units in parallel. For example, if there
are 3 pieces of AIF04ZPFC-02L in parallel, customer will need to put 60A (20A x 3) external rectifier for each line.
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
Recommend external Inrush Current Limit circuit
CIRCUIT(1): Using relay controlled from secondary side:
+
Vin
R1
R2
+
AIF04PFC
+
DC-DC
Converter
R3
Vout
-
ENABLE
LD_ENABLE
Operating Voltage of the
coil needs to match with
V out
CIRCUIT(2):Using relay controlled by Auxiliary supply on primary side:
+
+
Vin
-
R1
+
R2
+
AIF04ZPFC
Vout
-
Aux.Supply
LD_ENABLE
LED of opto-coupler for control
secondary circuit
D1
R3
Operating voltage of the
coil depends on the aux
supply
Q1
R4
In rush Limit for PFC Series
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
Brown Out Ride Through
Brown Out conditions occurs when there is a transient break in input current. During this period the external output bulk
capacitor holds up the voltage to the load until input current is restored. When the input voltage is restored the PFC module
will continue delivering power to the load
L1
+O/P
8
1
+
AC INPUT
85 to 265Vac
16
9
L2
Output to
AMPSSô
Modules or
other load
-O/P
APA
FOR BROWN OUT < 20ms
315V for Vadj to 76%
(390V for Vadj to 100%)
290V for Vadj to 76%
(380V for Vadj to 100%)
OUTPUT VOLTAGE
280V
250V(Min)
INPUT VOLTAGE
BROWN OUT
PFW
LOW
FOR BROWN OUT > 20ms
315V for Vadj to 76%
(390V for Vadj to 100%)
290V for Vadj to 76%
(380V for Vadj to 100%)
OUTPUT VOLTAGE
Load
Disabled
280V
Charging of
Output Capacitor
250V(Min)
INPUT VOLTAGE
BROWN OUT
PFW
LOW
LD ENABLE
LOW
After a Brown Out condition where the output voltage has not dropped below 250Vdc, the module will recover when input
power is restored. The PFW signal can be used to monitor input power loss.
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
Thermal Data
Natural convection thermal impedance of the PFC package without a heatsink is approximately 4°C/W.
A standard horizontal fin heatsink available from Astec (part number APA501-80-006) with 37mm fins and 8.8mm pitch,
will reduce module thermal impedance to 0.4°C /W with a forced air flow of 2.5 m/s (500 LFM) when mounted with a
thermal pad (ASTEC P/N APA502-80-001) between heatsink and module.
T hermal resistance heatsink to
ambient ( °C/W)
Heatsink Thermal Resistance
1.4
1.2
1
0.8
APA501-80-005
APA501-80-006
0.6
0.4
0.2
0
0
500
1000
1500
Air velocity (LFM)
Overtemperature Protection
If the module's internal temperature exceeds 105°C (typical), the module will protect itself by latching off
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
OUTLINE DRAWING
AIF04ZPFC-xxxNTL
AIF04ZPFC-xxxL
Case thickness can meet UL-V0 flammability standard.
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Technical Reference Note
AIF - PFC Power Factor
Correction Series
Comparison between AIF - PFC and APA100 series
AIF04ZPFC-01L
Input Voltage
Max Output Power
85Vac ≤ Vin ≤ 120Vac
Vin ≥ 220Vac
Vac under-voltage / Power
interrupt
APA100-101
1000W
1600W
Power line interrupt protection
APA100-101M
APA100-102
85 - 265Vac
750W
1200W
APA100-103
APA100-104
550W
950W
750W
1200W
Fast-Recovery
Meet power line disturbance immunity
specification per IEC61000-4-11
Full Recycle
Yes
Fixed at 250KHz
-20癈 - 100癈
No
Non-fixed Frequency
-20癈 - 85癈
Floating PV_AUX supply
V-AUX Frequency
Operating temperature
Remote on/off
EEPROM data storage
Inrush current limit circuit
Parallel Application
Input current
External Diode Pair
Full load Vo
LD_ENABLE trigger point
Minimum setting for PFW_ADJ
Encapsulated
Internal Fuse
Fully SMT design
QAV
Control pins
Power pins
Mounting Kits
Module colour
AIF04ZPFC-02L
85 - 264Vac
Various
Yes
external
Total Iin < 16Arms
No Need
No Limit
Yes
380Vdc
250Vdc output
280Vdc
Yes
No
Yes
Yes
16 pins
∅ 2.06mm
No Need
Emerson Blue
Not rated
internal
external
Total Iin < 16Arms
No Need
Negative logic only
No
internal
external
No limit
Yes
377Vdc
180Vdc output
205Vdc
Partial
external
Total Iin < 16Arms
No Need
Yes (10A)
No
No
No
No
14 pins
∅ 1.52mm
Need
Black
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