Mitel MT8940AC T1/cept digital trunk pll Datasheet

ISO-CMOS ST-BUS FAMILY

MT8940
T1/CEPT Digital Trunk PLL
Features
ISSUE 7
July 1993
Ordering Information
•
Provides T1 clock at 1.544 MHz locked to input
frame pulse
•
Sources CEPT (30+2) Digital Trunk/ST-BUS
clock and timing signals locked to internal or
external 8 kHz signal
•
TTL compatible logic inputs and outputs
•
Uncommitted 2-input NAND gate
•
Single 5 volt power supply
•
Low power ISO-CMOS technology
MT8940AC
MT8940AE
24 Pin Ceramic DIP
24 Pin Plastic DIP
-40°C to +85°C
Description
Applications
•
Synchronization and timing control for T1
and CEPT digital trunk transmission links
•
ST- BUS clock and frame pulse source
The MT8940 is a dual digital phase-locked loop
providing the timing and synchronization signals for
the T1 or CEPT transmission links and the ST-BUS.
The first PLL provides the T1 clock (1.544 MHz)
synchronized to the input frame pulse at 8 kHz. The
timing signals for the CEPT transmission link and the
ST-BUS are provided by the second PLL locked to
an internal or an external 8 kHz frame pulse signal.
The MT8940 is fabricated in MITEL’s ISO-CMOS
technology.
CVb
F0i
Variable
Clock
Control
DPLL #1
2:1 MUX
C12i
CV
ENCV
MS0
MS1
MS2
Frame Pulse
Control
Mode
Selection
Logic
Input
Selector
MS3
F0b
C4b
4.096 MHz
Clock
Control
C8Kb
C4o
ENC4o
C16i
DPLL #2
C2o
Clock
Generator
2.048 MHz
Clock
Control
Ai
C2o
ENC2o
Bi
Yo
VDD
VSS
RST
Figure 1 - Functional Block Diagram
3-27
27
MT8940
ISO-CMOS
ENVC
MS0
C12i
MS1
F0i
F0b
MS2
C16i
ENC4o
C8Kb
C4o
VSS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VDD
RST
CV
CVb
Yo
Bi
Ai
MS3
ENC2o
C2o
C2o
C4b
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
EN CV
Variable clock enable (TTL compatible input) - This input (pulled internally to VDD) directly
controls the three states of CV (pin 22) under all modes of operation. When HIGH, enables
CV and when LOW, puts it in high impedance condition. It also controls the three states of
CVb signal (pin 21) if MS1 is LOW. When ENCV is HIGH, the pin CVb is an output and when
LOW, it is in high impedance state. However, if MS1 is HIGH, CVb is always an input.
2
MS0
Mode select ‘0’ input (TTL compatible) - This input (pulled internally to VSS) in conjunction
with MS1 (pin 4) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and
2).
3
C12i
Clock 12.355 MHz input (TTL compatible) - Master clock input at 12.355 MHz ±100ppm
for DPLL #1.
4
MS1
Mode select-1 input (TTL compatible) - This input (pulled internally to VSS) in conjunction
with MS0 (pin 2) selects the major mode of operation for both DPLLs. (Refer to Tables 1 and
2)
5
F0i
Frame pulse input (TTL compatible) - This is the frame pulse input (pulled internally to
VDD) at 8 kHz. The DPLL #1 locks to the falling edge of this input to generate T1 (1.544
MHz) clock.
6
F0b
Frame pulse Bidirectional (TTL compatible input and Totem-pole output) - Depending
on the minor mode selected for the DPLL #2, it provides the 8 kHz frame pulse output or acts
as an input (pulled internally to VDD) to an external frame pulse.
7
MS2
Mode select-2 input (TTL compatible) - This input (pulled internally to VDD) in conjunction
with MS3 (pin 17) selects the minor mode of operation for the DPLL #2. (Refer to Table 3.)
8
C16i
Clock 16.388 MHz input (TTL compatible) - Master clock input at 16.388 MHz±32 ppm for
DPLL #2.
9
ENC4o
Enable 4.096 MHz clock (TTL compatible input) - This active high input (pulled internally
to VDD) enables C4o (pin 11) output. When LOW, the output C4o is in high impedance
condition.
3-28
ISO-CMOS
MT8940
Pin Description (continued)
Pin #
Name
Description
10
C8Kb
Clock 8 kHz- Bidirectional (TTL compatible input and open drain output with 100K
internal resistor to VDD) - This is the 8 kHz input signal on the rising edge of which DPLL #2
locks during its NORMAL mode. When DPLL #2 is in SINGLE CLOCK mode, this pin outputs
an 8 kHz signal provided by DPLL #1, which is also connected internally to DPLL #2.
11
C4o
Clock 4.096 MHz (Three state output) - This is the inverse of the signal appearing on pin
13 (C4b) at 4.096 MHz and has a rising edge in the frame pulse (F0b) window. The high
impedance state of this output is controlled by ENC4o (pin 9).
12
VSS
Ground (0 Volt)
13
C4b
Clock 4.096 MHz- Bidirectional (TTL compatible input and Totem-pole output) - When
the mode select bit MS3 (pin 17) is HIGH, it provides the 4.096 MHz clock output with the
falling edge in the frame pulse (F0b) window. When pin 17 is LOW, C4b is an input (pulled
internally to VDD) to an external clock at 4.096 MHz.
14
C2o
Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a falling edge in the frame pulse (F0b) window. The high impedance state of this output
is controlled by ENC2o (pin 16).
15
C2o
Clock 2.048 MHz (Three state output) - This is the divide by two output of C4b (pin 13) and
has a rising edge in the frame pulse (F0b) window. The high impedance state of this output is
controlled by ENC2o (pin 16).
16
ENC2o
Enable 2.048 MHz clock (TTL compatible input) - This active high input (pulled internally
to VDD) enables both C2o and C2o outputs (pins 14 and 15). When LOW, these outputs are
in high impedance condition.
17
MS3
Mode select 3 input (TTL compatible) - This input (pulled internally to VDD) in conjunction
with MS2 (pin 7) selects the minor mode of operation for DPLL #2. (Refer to Table 3.)
18,19
Ai, Bi
Inputs A and B (TTL compatible) -These are the two inputs (pulled internally to VSS) of the
uncommitted NAND gate.
20
Yo
21
CVb
Variable clock Bidirectional (TTL compatible input and Totem-pole output) - When
acting as an output (MS1-LOW) during the NORMAL mode of DPLL #1, this pin provides the
1.544 MHz clock locked to the input frame pulse F0i (pin 5). When MS1 is HIGH, it is an
input (pulled internally to VDD) to an external clock at 1.544 MHz or 2.048 MHz to provide the
internal signal at 8 kHz to DPLL #2.
22
CV
Variable clock (Three state output) - This is the inverse output of the signal appearing on
pin 21, the high impedance state of which is controlled ENCV (pin 1).
23
RST
Reset (Schmitt trigger input) -This input (active LOW) evokes reset condition for the
device.
24
VDD
VDD (+5V) Power supply.
Output Y (Totem pole output) - Output of the uncommitted NAND gate.
3-29
MT8940
ISO-CMOS
Functional Description
The MT8940 is a dual digital phase-locked loop
providing the timing and synchronization signals to
the interface circuits for T1 and CEPT (30+2)
Primary Multiplex Digital Transmission links. As
shown in Figure 1, it has two digital phase-locked
loops (DPLLs), associated output controls and the
mode selection logic circuits. The two DPLLs,
although similar in principle, operate independently
to provide T1 (1.544 MHz) and CEPT (2.048 MHz)
transmission clocks, and ST-BUS timing signals.
The principle of operation behind the two DPLLs is
shown in Figure 3. A master clock is divided down to
8 kHz where it is compared with the 8 kHz input, and
depending on the output of the phase comparison,
the master clock frequency is corrected. The
MT8940 achieves the frequency correction in both
directions by using the master clock at a slightly
higher frequency and dividing it unaltered or
stretching its period (at two discrete instants in a
frame) before the division depending on the phase
comparison output. When the input frequency is
Master Clock
(12.355 MHz/
16.388 MHz)
Frequency
Correction
The phase sampling is done once in a frame (8 kHz)
and the divisions are set at 8 and 193 for DPLL #1,
which locks on to the falling edge of the input at 8
kHz to generate T1 (1.544 MHz) clock. Although the
phase sampling duration is the same for DPLL #2,
the divisions are set at 8 and 256 to provide the
CEPT/ST-BUS clock at 2.048 MHz synchronized to
the rising edge of the input signal (8 kHz). The
master clock source is specified to be at 12.355 MHz
±100 ppm for DPLL #1 and 16.388 MHz ±32 ppm for
DPLL #2 over the entire temperature range of
operation.
The inputs MS0 to MS3 are used to select the
operating mode of the MT8940, see Tables 1 to 4. All
the outputs are individually controlled to the high
impedance condition by their respective enable
controls. The uncommitted NAND gate is available
for use in applications involving MITEL’s
MT8976/MH89760
(T1
interfaces)
and
MT8979/MH89790 (CEPT interfaces).
Modes of Operation
The operation of the MT8940 is categorized into
major and minor modes. The major modes are
defined for both DPLLs by the mode select pins MS0
and MS1. The minor modes are selected by MS2
and MS3, and are applicable only to DPLL #2. There
are no minor modes for DPLL #1.
÷8
Output
(1.544 MHz /
2.048 MHz)
Input (8 kHz)
Phase
Comparison
÷193 /
÷256
Figure 3 - DPLL Principle
higher, the unchanged master clock is divided, thus
effectively speeding-up the locally generated clock
and eventually pulling it in synchronization with the
input. If the input frequency is lower than the divided
master clock, the period of the master clock is
stretched by half a cycle, at two discrete instants in a
phase sampling period. This introduces a total delay
of one master clock period over the sampling
duration, which is then divided to generate the local
signal synchronous with the input. Once the output is
phase-locked to the active edge of the input, the
circuit will maintain the locked condition as long as
the input frequency is within the lock-in range (±1.04
Hz) of the DPLLs. The lock-in range is wide enough
to meet the CCITT line rate specification (1.544
MHz±130ppm and 2.048 MHz ±50ppm) for the High
Capacity Terrestrial Digital Service.
3-30
Major modes of the DPLL #1
DPLL #1 can be operated in three major modes as
selected by MS0 and MS1 (Table 1). When MS1 is
LOW, it is in NORMAL mode, which provides a T1
(1.544 MHz) clock signal locked to the falling edge of
the input frame pulse F0i (8 kHz). DPLL#1 requires a
master clock input of 12.355 MHz±100 ppm (C12i).
In the second and third major modes (MS1 is HIGH),
DPLL #1 is set to DIVIDE an external 1.544 MHz or
2.048 MHz signal applied at CVb (pin 21). The
division can be set by MS0 to be either 193 (LOW) or
256 (HIGH). In these modes, the 8 kHz output is
connected internally to DPLL #2, which operates in
SINGLE CLOCK mode.
Major modes of the DPLL #2
There are four major modes for DPLL #2 selectable
by MS0 and MS1, as shown in Table 2. In all these
modes DPLL #2 provides the CEPT PCM 30 timing,
and the ST-BUS clock and framing signals.
In NORMAL mode, DPLL #2 provides the CEPT and
ST-BUS compatible timing signals locked to the
rising edge of the 8 kHz input signal (C8Kb). These
ISO-CMOS
signals are the 4.096 MHz (C4o and C4b) and the
2.048 MHz (C2o and C2o) clocks, and the 8 kHz
MS0
MS1
Mode of
operation
X
0
NORMAL
0
1
Note:
1
1
DIVIDE-1
DIVIDE-2
Function
Provides the T1 (1.544
MHz) clock synchronized
to the falling edge of the
input frame pulse (F0i).
DPLL #1 divides the CVb
input by 193. The divided
output is connected to
DPLL #2.
DPLL #1 divides the CVb
input by 256. The divided
output is connected to
DPLL #2.
X: indicates don’t care
MS0
MS1
Mode of
operation
0
0
NORMAL
1
0
0
1
1
1
Table 1. Major Modes of the DPLL #1
frame pulse (F0b), which are derived from the 16.388
MHz master clock. This mode can also provide the
ST-BUS timing and framing signals with the input
(C8Kb) tied HIGH and the master clock set at 16.384
MHz. The DPLL makes no correction in this
configuration and provides the timing signals
compatible to the ST-BUS format without any jitter.
In FREE-RUN mode, DPLL #2 generates CEPT and
ST-BUS timing and framing signals with no external
inputs except the master clock set at 16.388 MHz.
Since the master clock source is set at a higher
frequency than the nominal value, the DPLL makes
the necessary corrections to deliver the averaged
timing signals compatible to the ST-BUS format.
The operation of DPLL #2 in SINGLE CLOCK-1
mode is identical to SINGLE CLOCK-2 mode,
providing the CEPT and ST-BUS compatible timing
signals synchronized to the internal 8 kHz signal
obtained from DPLL#1 in DIVIDE mode. When
SINGLE CLOCK-1 mode is selected for DPLL #2, it
automatically selects the DIVIDE-1 mode for DPLL
#1, and thus, an external 1.544 MHz clock signal
applied at CVb (pin 21) is divided by DPLL #1 to
generate the internal signal at 8 kHz onto which
DPLL #2 locks. Similarly when SINGLE CLOCK-2
mode is selected, DPLL #1 is in DIVIDE-2 mode,
with an external signal of 2.048 MHz providing the
internal 8 kHz signal to DPLL #2. In both these
modes, this internal signal is available on C8Kb (pin
10) and DPLL #2 locks to its falling edge to provide
the CEPT and ST-BUS compatible timing signals.
This is in contrast to the Normal mode where these
timing signals are synchronized with the rising edge
of the 8 kHz signal on C8Kb.
Minor modes of the DPLL #2
The minor modes for DPLL #2 depends upon the
status of the mode select bits MS2 and MS3 (pins 7
and 17).
MT8940
Function
Provides ST-BUS/CEPT
timing signals locked to the
rising edge of the 8kHz
input signal at C8Kb.
FREE-RUN Provides ST-BUS timing
and framing signals with no
external inputs, except the
master clock.
SINGLE
Provides the CEPT/STCLOCK-1 BUS compatible timing
signals locked to the falling
edge of the 8kHz internal
signal provided by DPLL
#1.
SINGLE
Provides CEPT/ST-BUS
CLOCK-2 timing signals locked to the
falling edge of the 8kHz
internal signal provided by
DPLL #1.
Table 2. Major Modes of the DPLL #2
When MS3 is HIGH, DPLL #2 operates in any of the
major modes as selected by MS0 and MS1.
When MS3 is LOW, it overrides the major mode
selected and DPLL #2 accepts an external clock of
4.096 MHz on C4b (pin 13) to provide the 2.048 MHz
clocks (C2o and C2o) and the 8 kHz frame pulse
(F0b) compatible with the ST-BUS format.
The mode select bit MS2, controls the signal
direction of F0b (pin 6). When MS2 is LOW, F0b is an
input for an external frame pulse at 8 kHz. This
MS2
MS3
Functional Description
1
1
0
1
0
0
1
0
Provides ST-BUS 4.096 MHz and 2.048
MHz clocks and 8kHz frame pulse
depending on the major mode selected.
Provides ST-BUS 4.096 MHz & 2.048 MHz
clocks depending on the major mode
selected while F0b acts as an input.
However, the input on F0b has no effect on
the operation of DPLL #2 unless it is in
FREE-RUN mode.
Overrides the major mode selected and
accepts properly phase related external
4.096 MHz clock and 8 kHz frame pulse to
provide the ST-BUS compatible clock at
2.048MHz.
Overrides the major mode selected and
accepts a 4.096 MHz external clock to
provide the ST-BUS clock and frame pulse
at 2.048 MHz and 8 kHz, respectively.
Table 3. Minor Modes of the DPLL #2
input is effective only if MS3 is also LOW and C4b is
accepting a 4.096 MHz external clock, which has a
proper phase relationship with the external input on
3-31
MT8940
ISO-CMOS
F0b (refer to Figure 15). Otherwise, the input on pin
F0b will have no bearing on the operation of DPLL
#2, unless it is in FREE-RUN mode as selected by
MS0 and MS1. In FREE-RUN mode, the input on
F0b is treated the same way as the C8Kb input in
NORMAL mode. The frequency of the input signal on
F0b should be 16 kHz for DPLL #2 to provide the STBUS compatible clocks at 4.096 MHz and 2.048
MHz.
When MS2 is HIGH, the F0b pin provides the STBUS frame pulse output locked to the 8kHz internal
or external signal as determined by the other mode
select pins MS0, MS1 and MS3.
Table 4 summarizes the modes of the two DPLLs. It
should be noted that each of the major modes
selected for DPLL #2 can have any of the minor
modes, although some of the combinations are
functionally similar. The required operation of both
DPLL#1 and DPLL#2 must be considered when
determining MS0-MS3.
M
O
D
E
#
MS
0
MS
1
MS
2
MS
3
0
0
0
0
0
NORMAL MODE
Properly phase related External 4.096 MHz
clock and 8 kHz frame pulse provide the STBUS clock at 2.048 MHz.
1
0
0
0
1
NORMAL MODE
NORMAL MODE
F0b is an input but has no function in this mode.
2
0
0
1
0
NORMAL MODE
External 4.096 MHz provides the ST-BUS clock
and Frame Pulse at 2.048 MHz and 8 kHz,
respectively.
Operating Modes
DPLL #1
DPLL #2
NORMAL MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz input signal (C8Kb).
3
0
0
1
1
NORMAL MODE:
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of the
input frame pulse (F0i).
4
0
1
0
0
DIVIDE-1 MODE
Same as mode ‘0’.
5
0
1
0
1
DIVIDE-1 MODE
SINGLE CLOCK-1 MODE
F0b is an input, but has no function in this
mode.
6
0
1
1
0
DIVIDE-1 MODE
Same as mode 2.
DIVIDE-1 MODE:
Divides the CVb input by 193. The divided
output is connected to DPLL #2.
SINGLE CLOCK-1 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
NORMAL MODE
Same as mode ‘0’.
NORMAL MODE
F0b is an input and DPLL #2 locks on to
it only if it is at 16 kHz to provide the ST-BUS
control signals.
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
10
1
0
1
0
NORMAL MODE
Same as mode 2.
FREE-RUN MODE:
Provides the ST-BUS timing signals with no
external inputs except the master clock.
11
1
0
1
1
NORMAL MODE
Provides the T1 (1.544 MHz) clock
synchronized to the falling edge of input frame
pulse (F0i).
12
1
1
0
0
DIVIDE-2 MODE
Same as mode ‘0’.
DIVIDE-2 MODE
13
1
1
0
1
SINGLE CLOCK-2 MODE:
F0b is an input, but has no function in this
mode.
14
1
1
1
0
15
1
1
1
1
DIVIDE-2 MODE
Same as mode 2.
DIVIDE-2 MODE:
Divides the CVb input by 256. The divided
output is connected to DPLL#2.
SINGLE CLOCK-2 MODE:
Provides the CEPT/ST-BUS compatible timing
signals locked to the 8 kHz internal signal
provided by DPLL #1.
Table 4. Summary of Modes of Operation - DPLL #1 and #2
3-32
ISO-CMOS
Applications
The following figures illustrate how the MT8940 can
be used in a minimum component count approach to
providing the timing and synchronization signals for
the Mitel T1 and CEPT interfaces, and the ST-BUS.
The hardware selectable modes and the
independent control over each PLL adds flexibility to
the interface circuits. It can be easily reconfigured to
provide the timing and control signals for both at the
master and slave ends of the link.
Synchronization and Timing Signals for the T1
Transmission Link
Figures 4 and 5 show examples of how to generate
the timing signals for the master and slave ends of a
T1 link.
At the master end of the link (Figure 4), DPLL #2 is
the source of the ST-BUS signals derived from the
4.096 MHz system clock. The frame pulse output is
looped back to DPLL #1 (in NORMAL mode), which
locks to it to generate the T1 line clock. The timing
relationship between the 1.544 MHz T1 clock and
the 2.048 MHz ST-BUS clock meets the
requirements of the MH89760/760B. The crystal
clock at 12.355 MHz is used by DPLL #1 to generate
the 1.544 MHz clock, while DPLL #2 uses the 4.096
MHz system clock to provide the ST-BUS timing
signals. The ST-BUS signals can also be obtained
from DPLL #2 in FREE-RUN mode, using a crystal
clock at 16.388 MHz instead of 4.096 MHz system
Synchronization and Timing Signals for the
CEPT Transmission Link
The MT8940 can be used to provide the timing and
synchronization signals for the MH89790/790B,
MITEL’s CEPT(30+2) digital trunk interface hybrid.
Since the operational frequencies of the ST-BUS and
the CEPT primary multiplex digital trunk are same,
only DPLL #2 is required to achieve synchronization
between the two.
Figures 6 and 7 show how the MT8940 can be used
to synchronize the ST-BUS and the CEPT
transmission link at the master and slave ends,
respectively.
VDD
MS0
CV
F0i
C12i
(ST-BUS
compatible)
At the slave end of the link (Figure 5) both the DPLLs
are in NORMAL mode with DPLL #2 providing the
ST-BUS timing signals locked to the 8 kHz frame
pulse (E8Ko) extracted from the received signal on
the T1 line. The regenerated frame pulse is looped
back to DPLL #1 to provide the T1 line clock as at
the master end. The 12.355 MHz and 16.388 MHz
crystal clock sources are necessary for DPLL #1 and
#2.
MT8940
MS1
MS2
MS3
4.096 MHz
System Clock
clock. The uncommitted NAND gate converts the
received signals, RxA and RxB of the MH89760 to a
single Return to Zero (RZ) input for the clock
extraction circuits of the MH89760. This is not
required for the MH89760B. The generated ST-BUS
signals can be used to synchronize the system and
the switching equipment at the master end.
MT8980/81
Crystal Clock
(12.355 MHz
±100 ppm)
MT8940
C4b
ENCV
C8Kb
C16i
ENC4o
ENC2o
Ai
Bi
VSS
ST-BUS
SWITCH
MH89760
C1.5i
DSTi
C2i
DSTo
F0i
CSTi
CSTo
C2o
TxT
F0b
Yo
TRANSMIT
RxA
TxR
RxB
RxT
RxD
RxR
T1
LINK
(1.544 Mbps)
RECEIVE
RST
MODE OF OPERATION FOR THE MT8940
DPLL #1 - NORMAL (MS0 = X; MS1 = 0)
DPLL #2 - OVERRIDE THE MAJOR MODES (MS2 = 1; MS3 = 0)
Figure 4 - Synchronization at the Master End of the T1 Transmission Link
3-33
MT8940
ISO-CMOS
Crystal Clock
MT8980/81
MT8940
(12.355 MHz
± 100 ppm)
VDD
MS0
MH89760
ST-BUS
SWITCH
MS1
MS2
MS3
CV
C1.5i
C2i
F0i
C12i
C4b
ENCV
C8Kb
C2o
F0i
DSTi
DSTo
CSTi
CSTo
TxT
C16i
ENC4o
ENC2o
Ai
F0b
Yo
Bi
VSS
Crystal Clock
RxA
TxR
RxB
RxT
RxD
RxR
TRANSMIT
T1
LINK
(1.544 Mbps)
RECEIVE
RST
(16.388 MHz
± 32 ppm)
Mode of Operation for the MT8940
DPLL #1 - NORMAL (MS1=0)
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 5 - Synchronization at the Slave End of the T1 Transmission Link
MT8980/81
MT8940
VDD
MS0
ST-BUS
SWITCH
MH89790
MS1
MS2
MS3
C4b
C2i
F0i
C12i
4.096 MHz
System Clock
ENCV
C8Kb
(ST-BUS
Compatible)
C16i
C2o
F0i
DSTo
CSTi0
CSTi1
CSTo
F0b
ENC4o
ENC2o
Ai
Yo
Bi
VSS
DSTi
RST
RxA
OUTA
RxB
OUTB
RxD
TRANSMIT
RxT
RECEIVE
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
RxR
Mode of Operation for the MT8940
DPLL #1 - NOT USED
DPLL #2 - OVERRIDE MAJOR MODES (MS0=X; MS1=X
MS2=1; MS3=0)
Figure 6 - Synchronization at the Master End of the CEPT Digital Transmission Link
Generation of ST-BUS Timing Signals
The MT8940 can source the properly formatted STBUS timing and control signals with no external
inputs except the crystal clock. This can be used as
the standard timing source for ST-BUS systems or
any other system with similar clock requirements.
Figure 8 shows two such applications using only
DPLL #2. In one case, the MT8940 is in FREE-RUN
3-34
mode with an oscillator input of 16.388 MHz. This
forces the DPLL to correct at a rate of 4 kHz to
maintain the ST-BUS clocks, which therefore, will be
jittered. In the other case, the oscillator input is
16.384 MHz (exactly eight times the output
frequency) and DPLL #2 operates in NORMAL mode
with C8Kb input tied HIGH. Since no corrections are
necessary, the output is free from jitter. DPLL #1 is
completely free in both cases and available for any
other purpose.
MT8940
ISO-CMOS
MT8940
MT8980/81
VDD
MS0
MH89790
MS1
MS2
MS3
C4b
C2i
F0i
C12i
C2o
F0i
CSTi1
CSTo
C16i
(16.388 MHz
± 32 ppm)
F0b
ENC4o
ENC2o
Ai
Yo
Bi
VSS
DSTo
CSTi0
ENCV
C8Kb
Crystal Clock
ST-BUS
SWITCH
DSTi
RxA
OUTA
RxB
OUTB
RxD
TRANSMIT
RxT
RECEIVE
RST
CEPT
PRIMARY
MULTIPLEX
DIGITAL
LINK
RxR
Mode of Operation for the MT8940
DPLL #1 - NOT USED
DPLL #2 - NORMAL (MS0=0; MS1=0; MS2=1; MS3=1)
Figure 7 - Synchronization at the Slave End of the CEPT Digital Transmission Link
MT8940
VDD
MS0
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0; MS2=1;
MS3=1)
(16.388 MHz
± 32 ppm)
MS1
MS2
MS3
C4o
F0i
C12i
C4b
ST-BUS
ENCV
C8Kb
TIMING
C2o
Crystal Clock
C16i
SIGNALS
ENC4o
ENC2o
Ai
C2o
Bi
F0b
VSS
VDD
MS0
MS1
Crystal Clock
MT8940
RST
(16.388 MHz
± 32 ppm)
DPLL #1 - NOT USED
DPLL #2 - NORMAL MODE
(MS0=0; MS1=0;
MS2=1; MS3=1)
MS2
MS3
C4o
F0i
C12i
C4b
ST-BUS
ENCV
C8Kb
TIMING
C2o
C16i
ENC4o
ENC2o
Ai
C2o
Bi
F0b
VSS
SIGNALS
RST
Figure 8 - Generation of the ST-BUS Timing Signals
3-35
MT8940
ISO-CMOS
Absolute Maximum Ratings*- Voltages are with respect to ground (VSS) unless otherwise stated.
Parameter
Symbol
Min
Max
Units
VDD
-0.3
7.0
V
VI
VSS-0.5
VDD+0.5
V
IIK/OK
±10
mA
1
Supply Voltage
2
Voltage on any pin
3
Input/Output Diode Current
4
Output Source or Sink Current
IO
±25
mA
5
DC Supply or Ground Current
IDD/ISS
±50
mA
6
Storage Temperature
150
o
7
Package Power Dissipation
TST
Ceramic DIP
LCC
-65
PD
PD
1200
600
C
mW
mW
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
5.0
5.25
V
Test Conditions
1
Supply Voltage
VDD
4.75
2
Input HIGH Voltage
VIH
2.4
VDD
V
For 400 mV noise margin
3
Input LOW Voltage
VIL
VSS
0.4
V
For 400 mV noise margin
4
Operating Temperature
TA
-40
85
oC
25
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated.
VDD =5.0 V±5%; VSS=0V; TA=-40 to 85°C.
Characteristics
1
S
U
P
Supply Current
Sym
Min
IDD
IDDS
Typ‡
Max
Units
Test Conditions
8
15
100
mA
Under clocked condition, with the
inputs tied to the same supply rail
as the corresponding pull-up /
down resistors.
2
Input HIGH voltage (For all the
inputs except pin 23)
VIH
2.0
V
3
Positive-going threshold
voltage (For pin 23)
V+
2.8
V
Input LOW voltage (For all the
inputs except pin 23)
VIL
0.8
V
5
Negative-going threshold
voltage (For pin 23)
V-
1.5
V
6
Output current HIGH (For all
the outputs except pin 10)
IOH
-9.5
mA
VOH=2.4 V
Output current LOW (For all the
outputs except pin 10)
IOL
4.5
mA
VOL=0.4 V
8
Output current LOW (pin 10)
IOL
2.0
mA
VOL=0.4 V
9
Leakage current on bidirectional pins and all inputs except
C12i, C16i, RST
IIZ/OZ
±150
µA
VI/O=VSS or VDD
10
Leakage current on all outputs
and C12i, C16i, RST inputs
IIZ/OZ
±10
µA
VI/O=VSS or VDD
4
7
I
N
O
U
T
±1
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-36
ISO-CMOS
MT8940
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 9)
Characteristics
Sym
Min
1
Frame pulse input (F0i) to CVb
output (1.544 MHz) delay
tF15H
-40
2
CVb output (1.544 MHz) rise
time
tr1.5
3
Typ‡
Max
Units
75
ns
10
15
ns
Test load circuit 1 (Fig. 17).
12
15
ns
Test load circuit 1 (Fig. 17).
D
P
L
L
CVb output (1.544 MHz) fall
time
tf1.5
CVb output (1.544 MHz) clock
period
tP15
648
690
ns
#1
CVb output (1.544 MHz) clock
width (HIGH)
tW15H
320
386
ns
6
CVb output (1.544 MHz) clock
width (LOW)
tW15L
314
327
ns
7
CV delay (HIGH to LOW)
t15HL
5
30
ns
8
CV delay (LOW to HIGH)
t15LH
-12
10
ns
4
5
Test Conditions
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
F0i
VIH
VIL
tF15H
tP15
tf1.5
tW15H
CVb
VOH
VOL
tW15L
t15HL
tr1.5
t15LH
CV
VOH
VOL
Figure 9 - Timing Information for DPLL #1 in NORMAL Mode
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 10)
Characteristics
1
2
3
4
5
D
P
L
L
#1
Sym
C8Kb output (8kHz) delay
(HIGH to HIGH)
tC8HH
C8Kb output (8 kHz) delay
(LOW to LOW)
tC8LL
C8Kb output duty cycle
Min
Typ‡
50
Max
Units
Test Conditions
130
ns
Test load circuit 2 (Fig. 17).
130
ns
Test load circuit 2 (Fig. 17).
%
%
In Divide -1 Mode
In Divide - 2 Mode
66
50
Inverted clock output delay
(HIGH to LOW)
tICHL
40
75
ns
Inverted clock output delay
(LOW to HIGH)
tICLH
35
60
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
3-37
MT8940
ISO-CMOS
VIH
CVb
VIL
tICHL
tICLH
VOH
CV
VOL
tC8HH
tC8LL
VOH
C8Kb
VOL
Figure 10 - DPLL #1 in DIVIDE Mode
tWFP
F0b
VOH
VOL
tFPL
tFPH
tfC4
trC4
VOH
C4b
VOL
t4oLH
t4oHL
VOH
C4o
VOL
t42LH
t42HL
tP2o
tW2oH
tfC2
trC2
VOH
C2o
VOL
tW2oL
t2oLH
t2oHL
VOH
C2o
VOL
Figure 11 - Timing Information on DPLL #2 Outputs
3-38
ISO-CMOS
MT8940
AC Electrical Characteristics†-Voltages are with respect to ground (VSS) unless otherwise stated.(Ref. Figures 11&12)
Typ‡
Max
Units
Test Conditions
-25
75
ns
Test load circuit 2 (Fig. 17)
on C8Kb.
tP4o
240
282
ns
Test load circuit 1 (Fig. 17).
C4b output clock width (HIGH)
tW4oH
123
165
ns
4
C4b output clock width (LOW)
tW4oL
110
123
ns
5
C4b output clock rise time
trC4
10
ns
Test load circuit 1 (Fig. 17).
6
C4b clock output fall time
tfC4
10
ns
Test load circuit 1 (Fig. 17).
7
Frame pulse output delay
(HIGH to LOW) from C4b
tFPL
50
ns
8
Frame pulse output delay
(LOW to HIGH) from C4b
tFPH
40
ns
Frame pulse (F0b) width
tWFP
245
ns
C4o delay - LOW to HIGH
t4oLH
45
ns
C4o delay - HIGH to LOW
t4oHL
45
ns
C4b to C2o delay (LOW to
HIGH)
t42LH
+10
ns
13
C4b to C2o delay (HIGH to
LOW)
t42HL
20
ns
14
C2o clock period
tP2o
486
523
ns
15
C2o clock width (HIGH)
tW2oH
244
291
ns
16
C2o clock width (LOW)
tW2oL
233
244
ns
17
C2o clock rise time
trC2
10
ns
Test load circuit 1 (Fig. 10).
18
C2o clock fall time
tfC2
10
ns
Test load circuit 1 (Fig. 10).
19
C2o delay - LOW to HIGH
t2oLH
20
ns
20
C2o delay - HIGH to LOW
t2oHL
30
ns
Characteristics
Sym
Min
1
C4b output delay (HIGH to
LOW) from C8Kb input/output
t84H
2
C4b output clock period
3
9
10
11
12
D
P
L
L
#2
200
-10
-5
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 17).
Test load circuit 1 (Fig. 10).
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
C8Kb
as
Output
VOH
C8Kb
as
Input
VIH
VOL
VIL
t84H
tW4oH
VOH
C4b
VOL
tP4o
tFPL
tFPH
tW4oL
VOH
F0b
VOL
Figure 12 - ST-BUS Timings from DPLL #2 and C8Kb Input/Output
3-39
MT8940
ISO-CMOS
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 13)
Characteristics
1
CV/CVb (1.544 MHz) Setup time
Sym
Min
tS15
25
Typ‡
Max
Units
Test Conditions
ns
2 CV/CVb (1.544 MHz) Hold time
tH15
110
ns
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VOH
F0b
Boundary between ST-BUS channel 2 bit 4 and
channel 2 bit 3
VOL
20 CYCLES
VOH
C2o
VOL
tH15
tS15
VOH
CV
VOL
tH15
tS15
VOH
CVb
VOL
Figure 13 - F0b from DPLL #2 is Looped Back as Input to DPLL #1 (T1 Line synchronized to ST-BUS)
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 14)
Characteristics
Sym
Min
Typ‡
Max
Units
1
Master clocks input rise time
tr
10
ns
2
Master clocks input fall time
tf
10
ns
3 C Master clock period
L (12.355MHz)
O
4 C Master clock period
K (16.388MHz)
S
5
Duty Cycle of master clocks
6
Lock-in Range (For each PLL)
Test Conditions
tP12
80.930
80.938
80.946
ns
For DPLL #1, while operating to
provide the T1 clock signal.
tP16
61.018
61.020
61.022
ns
For DPLL #2, while operating to
provide the CEPT and ST-BUS
timing signals.
45
50
55
%
+1.04
Hz
-1.5
With the Master clocks as shown
above.
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tr
Master clock
inputs
tf
2.4 V
1.5 V
0.4 V
tP12 or tP16
Figure 14 - Master Clock Inputs
3-40
ISO-CMOS
MT8940
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 15)
Characteristics
Sym
Min
1
F0b input pulse width (LOW)
tWFP
40
2
C4b input clock period
tP4o
.080
3
Frame pulse (F0b) setup time
tFS
25
Typ‡
Max
Units
Test Conditions
ns
50
µs
ns
4 Frame pulse (F0b) hold time
tFH
5
ns
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
tWFP
VIH
F0b
VIL
tFH
VIH
C4b
VIL
tFS
tP4o
Figure 15 - External Inputs on C4b and F0b for the DPLL #2
AC Electrical Characteristics† - Voltages are with respect to ground (VSS) unless otherwise stated. (Ref. Figure 16)
Characteristics
1
2
3
O
U
T
P
U
T
4
Sym
Min
Typ‡
Max
Units
Test Conditions
Delay from Enable to Output
(HIGH to THREE STATE)
tPHZ
15
65
ns
Test load circuit 3 (Fig.17)
Delay from Enable to Output
(LOW to THREE STATE)
tPLZ
10
55
ns
Test load circuit 3 (Fig.17)
Delay from Enable to Output
(THREE STATE to HIGH)
tPZH
40
ns
Test load circuit 3 (Fig.17)
Delay from Enable to Output
(THREE STATE to LOW)
tPZL
50
ns
Test load circuit 3 (Fig.17)
† Timing is over recommended temperature & power supply voltages
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
6 ns
tf
tr
6 ns
3.0 V
2.7 V
1.3 V
0.3 V
Enable
Input
tPZL
tPLZ
Output
LOW to
OFF
1.3 V
10%
tPHZ
tPZH
90%
Output
HIGH
to OFF
1.3 V
Outputs
Enabled
Outputs
Disabled
Outputs
Enabled
Figure 16 - Three State Outputs and Enable Timings
3-41
MT8940
ISO-CMOS
AC Electrical Characteristics† - Uncommitted NAND Gate
Voltages are with respect to ground (VSS) unless otherwise stated.
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Propagation delay (LOW to
HIGH), input Ai or Bi to output
tPLH
25
40
ns
Test load circuit 1 (Fig. 17)
2
Propagation delay (HIGH to
LOW), input Ai or Bi to output
tPHL
20
40
ns
Test load circuit 1 (Fig. 17)
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
VDD
VDD
RL=1kΩ
From
output
under test
Test
point
From
output
under test
Test
point
Test
point
From
output
under test
A
RL=1kΩ
S1
B
VSS
CL=50pF
Test load circuit- 1
CL=50pF
CL=50pF
Test load circuit- 2
Test load circuit- 3
Figure 17 - Test Load Circuits
3-42
Note: S1 is in position A
when measuring tPLZ
and tPZ and in position B
when measuring tPHZ and
tPZH