FEATURES FUNCTIONAL BLOCK DIAGRAM VISO VDD1 Isolated PWM feedback with built in compensation Primary side transformer driver for up to 2.5 W output power with 5 V input voltage Regulated adjustable output: 3.3 V to 24 V Up to 80% efficiency Quad dc-to-25 Mbps (NRZ) signal isolation channels 200 kHz to 1 MHz adjustable oscillator Soft start function at power-up Pulse-by-pulse overcurrent protection Thermal shutdown 5000 V rms isolation High common-mode transient immunity: >25 kV/μs 20-lead SOIC package with 8.3 mm creepage High temperature operation: 105°C RECT VREG VDDA PRIMARY CONTROLLER/ DRIVER ADuM4470/ ADuM4471/ ADuM4472/ ADuM4473/ ADuM4474 INTERNAL FEEDBACK REG SECONDARY CONTROLLER VDD2 5V FB OC I/OA I/OA CHA I/OB I/OC PRIMARY DATA I/O 4-CHANNEL CHB SECONDARY DATA I/O 4-CHANNEL I/OB I/OC CHC I/OD I/OD APPLICATIONS CHD GND1 Power supply start-up bias and gate drives Isolated sensor interfaces Process controls RS-232/RS-422/RS-485 transceivers GND2 10991-001 Data Sheet Isolated Switching Regulator with Quad-Channel Isolators ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Figure 1. GENERAL DESCRIPTION The regulated feedback provides a relatively flat efficiency curve over the full output power range. The ADuM447x enable a dcto-dc converter with a 3.3 V to 24 V isolated output voltage range from either a 5.0 V or a 3.3 V input voltage, with an output power of up to 2.5 W. The ADuM4470/ADuM4471/ADuM4472/ADuM4473/ ADuM44741 are quad-channel, digital isolators with a regulated dc-to-dc isolated power supply controller and an internal MOSFET driver. The dc-to-dc controller has an internal isolated PWM feedback from the secondary side, based on the iCoupler® chip scale transformer technology and complete loop compensation. This eliminates the need to use an optocoupler for feedback and compensates the loop for stability. The ADuM447x isolators provide four independent isolation channels in a variety of channel configurations and data rates. (The x in ADuM447x throughout this data sheet stands for the ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474.) The ADuM447x isolators provide a more stable output voltage and higher efficiency compared to unregulated isolated dcto-dc power supplies. The fully integrated feedback and loop compensation in a wide-body SOIC package provide a smaller form factor and 8.3 mm creepage distance solution. 1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7075 329 B2. Other patents pending. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ......................... 15 Applications ....................................................................................... 1 Typical Performance Characteristics ........................................... 20 Functional Block Diagram .............................................................. 1 Applications Information .............................................................. 26 General Description ......................................................................... 1 Theory of Operation .................................................................. 26 Revision History ............................................................................... 2 Application Schematics ............................................................. 26 Block Diagrams of I/O Channels.................................................... 3 Transformer Design ................................................................... 27 Specifications..................................................................................... 4 Transformer Turns Ratio ........................................................... 27 Electrical Characteristics—5 V Primary Input Supply/ 5 V Secondary Isolated Supply ................................................... 4 Transformer ET Constant ......................................................... 27 Electrical Characteristics—3.3 V Primary Input Supply/ 3.3 V Secondary Isolated Supply ................................................ 6 Transformer Isolation Voltage .................................................. 28 Electrical Characteristics—5 V Primary Input Supply/ 3.3 V Secondary Isolated Supply ................................................ 8 Transient Response .................................................................... 28 Transformer Primary Inductance and Resistance ................. 28 Switching Frequency .................................................................. 28 Electrical Characteristics—5 V Primary Input Supply/ 15 V Secondary Isolated Supply ............................................... 10 Component Selection ................................................................ 29 Package Characteristics ............................................................. 12 Thermal Analysis ....................................................................... 30 Regulatory Approvals (Pending) .............................................. 12 Propagation Delay-Related Parameters ................................... 30 Insulation and Safety-Related Specifications .......................... 12 DC Correctness and Magnetic Field Immunity........................... 30 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ............................................................................ 13 Power Consumption .................................................................. 31 Recommended Operating Conditions .................................... 13 Insulation Lifetime ..................................................................... 33 Absolute Maximum Ratings.......................................................... 14 Outline Dimensions ....................................................................... 34 ESD Caution ................................................................................ 14 Ordering Guide .......................................................................... 34 Printed Circuit Board (PCB) Layout ....................................... 29 Power Considerations ................................................................ 32 REVISION HISTORY 12/12—Revision 0: Initial Version Rev. 0 | Page 2 of 36 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 BLOCK DIAGRAMS OF I/O CHANNELS ADuM4470 10991-005 10991-002 ADuM4473 Figure 2. ADuM4470 Figure 5. ADuM4473 ADuM4471 10991-006 10991-003 ADuM4474 Figure 3. ADuM4471 Figure 6. ADuM4474 10991-004 ADuM4472 Figure 4. ADuM4472 Rev. 0 | Page 3 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY 4.5 V ≤ (VDD1 = VDDA) ≤ 5.5 V; VDD2 = VREG = VISO = 5.0 V; fSW = 500 kHz; all voltages are relative to their respective grounds; see the application schematic in Figure 48. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VDD2 = VREG = VISO = 5.0 V. Table 1. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Isolated Output Voltage Symbol Min Typ Max Unit Test Conditions/Comments VISO 4.5 5.0 5.5 V Feedback Voltage Setpoint Line Regulation VFB VISO (LINE) 1.15 1.25 1 1.37 10 V mV/V Load Regulation Output Ripple VISO (LOAD) VISO (RIP) 1 50 2 % mV p-p Output Noise VISO (NOISE) 100 mV p-p Switching Frequency fSW RON 1000 200 318 0.5 kHz kHz kHz Ω IISO = 0 mA, VISO = VFB × (R1 + R2)/R2 IISO = 0 mA IISO = 50 mA, VDD1 1 = VDDA 2 = 4.5 V to 5.5 V IISO = 50 mA to 200 mA 20 MHz bandwidth, COUT = 0.1 µF||47 µF, IISO = 100 mA 20 MHz bandwidth, COUT = 0.1 µF||47 µF, IISO = 100 mA ROC = 50 kΩ ROC = 270 kΩ VOC = VDD2 (open-loop) VUV+ VUV− VUVH 2.8 2.6 0.2 V V V 500 72 mA % 192 Switch On-Resistance Undervoltage Lockout, VDDA, VDD2 Supplies Positive Going Threshold Negative Going Threshold Hysteresis DC to 2 Mbps Data Rate 3 Maximum Output Supply Current 4 Efficiency at Maximum Output Current 5 iCoupler DATA CHANNELS DC to 2 Mbps Data Rate IDD1 Supply Current, No VISO Load ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 25 Mbps Data Rate (CRIZ Grade Only) IDD1 Supply Current, No VISO Load ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 Available VISO Supply Current 6 ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 IDD1 Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold IISO (MAX) 400 515 IDD1 (Q) f ≤ 1 MHz, VISO = 5.0 V IISO = IISO (MAX), f ≤ 1 MHz IISO = 0 mA, f ≤ 1 MHz 14 15 16 17 18 30 30 30 30 30 mA mA mA mA mA IDD1 (D) 44 46 48 50 52 mA mA mA mA mA 390 388 386 384 382 550 mA mA mA mA mA mA IISO (LOAD) IIA, IIB, IIC, IID VIH VIL −20 2.0 +0.01 +20 0.8 Rev. 0 | Page 4 of 36 µA V V IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz fSW = 500 kHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD1 = VDDA = 5 V, IISO = 400 mA Data Sheet Parameter Logic High Output Voltages Logic Low Output Voltages AC SPECIFICATIONS ADuM447xARIZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH − tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM447xCRIZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH − tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Symbol VOAH, VOBH, VOCH, VODH Min VDDA − 0.3, VISO − 0.3 VDDA − 0.5, VISO − 0.5 VOAL, VOBL, VOCL, VODL Typ 5.0 Max 4.8 Test Conditions/Comments IOx = −20 µA, VIx = VIxH V IOx = −4 mA, VIx = VIxH 0.0 0.1 V IOx = 20 µA, VIx = VIxH 0.0 0.4 V IOx = 4 mA, VIx = VIxH 1000 ns Mbps ns ns ns ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels PW 1 tPLH, tPHL PWD tPSK tPSKCD/tPSKOD Unit V 55 PW 100 40 50 50 tPSK tPSKCD 15 6 ns Mbps ns ns ps/°C ns ns tPSKCD 15 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDDA or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V or VISO, VCM = 1000 V, transient magnitude = 800 V tPLH, tPHL PWD 40 25 30 45 60 6 5 tR/tF |CMH| 25 2.5 35 ns kV/µs |CML| 25 35 kV/µs 1.0 Mbps fr 1 VDD1 is the power supply for the push-pull transformer. VDDA is the power supply of Side 1 of the ADuM447x. 3 The contributions of supply current values for all four channels are combined at identical data rates. 4 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 5 The power demands of the quiescent operation of the data channels were not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 6 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate. 2 Rev. 0 | Page 5 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet ELECTRICAL CHARACTERISTICS—3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY 3.0 V ≤ VDD1 = VDDA ≤ 3.6 V; VDD2 = VREG = VISO = 3.3 V; fSW = 500 kHz; all voltages are relative to their respective grounds; see the application schematic in Figure 48. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 3.3 V, VDD2 = VREG = VISO = 3.3 V. Table 2. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Isolated Output Voltage Symbol Min Typ Max Unit Test Conditions/Comments VISO 3.0 3.3 3.6 V Feedback Voltage Setpoint Line Regulation VFB VISO (LINE) 1.15 1.25 1 1.37 10 V mV/V Load Regulation Output Ripple VISO (LOAD) VISO (RIP) 1 50 2 % mV p-p Output Noise VISO (NOISE) 100 mV p-p Switching Frequency fSW RON 1000 200 318 0.6 kHz kHz kHz Ω IISO = 0 mA, VISO = VFB × (R1 + R2)/R2 IISO = 0 mA IISO = 50 mA, VDD1 1 = VDDA 2 = 4.5 V to 5.5 V IISO = 50 mA to 200 mA 20 MHz bandwidth, COUT = 0.1 µF||47 µF, IISO = 100 mA 20 MHz bandwidth, COUT = 0.1 µF||47 µF, IISO = 100 mA ROC = 50 kΩ ROC = 270 kΩ VOC = VDD2 (open-loop) VUV+ VUV− VUVH 2.8 2.6 0.2 V V V 68 mA % 192 Switch On-Resistance Undervoltage Lockout, VDDA, VDD2 Supplies Positive Going Threshold Negative Going Threshold Hysteresis DC to 2 Mbps Data Rate 3 Maximum Output Supply Current 4 Efficiency at Maximum Output Current 5 iCoupler DATA CHANNELS DC to 2 Mbps Data Rate IDD1 Supply Current, No VISO Load ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 25 Mbps Data Rate (CRIZ Grade Only) IDD1 Supply Current, No VISO Load ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 Available VISO Supply Current 6 ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 IDD1 Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold IISO (MAX) 515 250 IDD1 (Q) f ≤ 1 MHz, VISO = 5.0 V IISO = IISO (MAX), f ≤ 1 MHz IISO = 0 mA, f ≤ 1MHz 9 10 11 11 12 20 20 20 20 20 mA mA mA mA mA IDD1 (D) 28 29 31 32 34 mA mA mA mA mA 244 243 241 240 238 350 mA mA mA mA mA mA IISO (LOAD) IIA, IIB, IIC, IID VIH VIL −10 1.6 +0.01 +10 0.4 Rev. 0 | Page 6 of 36 µA V V IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz fSW = 500 kHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD1 = VDDA = 5 V, IISO = 400 mA Data Sheet Parameter Logic High Output Voltages Logic Low Output Voltages AC SPECIFICATIONS ADuM447xARIZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH − tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM447xCRIZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH − tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Symbol VOAH, VOBH, VOCH, VODH Min VDDA − 0.3, VISO − 0.3 VDDA − 0.5, VISO − 0.5 VOAL, VOBL, VOCL, VODL Typ 3.3 Max 3.1 Test Conditions/Comments IOx = −20 µA, VIx = VIxH V IOx = −4 mA, VIx = VIxH 0.0 0.1 V IOx = 20 µA, VIx = VIxH 0.0 0.4 V IOx = 4 mA, VIx = VIxH 1000 ns Mbps ns ns ns ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels PW 1 tPLH, tPHL PWD tPSK tPSKCD/tPSKOD Unit V 60 PW 100 40 50 50 tPSK tPSKCD 45 8 ns Mbps ns ns ps/°C ns ns tPSKCD 15 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDDA or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V or VISO, VCM = 1000 V, transient magnitude = 800 V tPLH, tPHL PWD 40 25 30 60 70 8 5 tR/tF |CMH| 25 2.5 35 ns kV/µs |CML| 25 35 kV/µs 1.0 Mbps fr 1 VDD1 is the power supply for the push-pull transformer. VDDA is the power supply of Side 1 of the ADuM447x. 3 The contributions of supply current values for all four channels are combined at identical data rates. 4 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 5 The power demands of the quiescent operation of the data channels were not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 6 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate. 2 Rev. 0 | Page 7 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY 4.5 V ≤ VDD1 = VDDA≤ 5.5 V; VDD2 = VREG = VISO = 3.3 V; fSW = 500 kHz; all voltages are relative to their respective grounds; see the application schematic in Figure 48. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VDD2 = VREG = VISO = 3.3 V. Table 3. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Isolated Output Voltage Symbol Min Typ Max Unit Test Conditions/Comments VISO 3.0 3.3 3.6 V Feedback Voltage Setpoint Line Regulation VFB VISO (LINE) 1.15 1.25 1 1.37 10 V mV/V Load Regulation Output Ripple VISO (LOAD) VISO (RIP) 1 50 2 % mV p-p Output Noise VISO (NOISE) 100 mV p-p Switching Frequency fSW RON 1000 200 318 0.5 kHz kHz kHz Ω IISO = 0 mA, VISO = VFB × (R1 + R2)/R2 IISO = 0 mA IISO = 50 mA, VDD1 1 = VDDA 2 = 4.5 V to 5.5 V IISO = 50 mA to 200 mA 20 MHz bandwidth, COUT = 0.1 µF||47 µF, IISO = 100 mA 20 MHz bandwidth, COUT = 0.1 µF||47 µF, IISO = 100 mA ROC = 50 kΩ ROC = 270 kΩ VOC = VDD2 (open-loop) VUV+ VUV− VUVH 2.8 2.6 0.2 V V V 70 mA % 192 Switch On-Resistance Undervoltage Lockout, VDDA, VDD2 Supplies Positive Going Threshold Negative Going Threshold Hysteresis DC to 2 Mbps Data Rate 3 Maximum Output Supply Current 4 Efficiency at Maximum Output Current 5 iCoupler DATA CHANNELS DC to 2 Mbps Data Rate IDD1 Supply Current, No VISO Load ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 25 Mbps Data Rate (CRIZ Grade Only) IDD1 Supply Current, No VISO Load ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 Available VISO Supply Current 6 ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 IDD1 Supply Current, Full VISO Load I/O Input Currents Logic High Input Threshold Logic Low Input Threshold IISO (MAX) 515 400 IDD1 (Q) f ≤ 1 MHz, VISO = 5.0 V IISO = IISO (MAX), f ≤ 1 MHz IISO = 0 mA, f ≤ 1 MHz 9 10 11 11 12 30 30 30 30 30 mA mA mA mA mA IDD1 (D) 33 33 33 33 33 mA mA mA mA mA 393 392 390 389 375 350 mA mA mA mA mA mA IISO (LOAD) IIA, IIB, IIC, IID VIH VIL −20 2.0 +0.01 +20 0.8 Rev. 0 | Page 8 of 36 µA V V IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz fSW = 500 kHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD1 = VDDA = 5 V, IISO = 400 mA Data Sheet Parameter Logic High Output Voltages Logic Low Output Voltages AC SPECIFICATIONS ADuM447xARIZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH − tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM447xCRIZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH − tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Symbol VOAH, VOBH, VOCH, VODH Min VDDA − 0.3, VISO − 0.3 VDDA − 0.5, VISO − 0.5 VOAL, VOBL, VOCL, VODL Typ 3.3 Max 3.1 Test Conditions/Comments IOx = −20 µA, VIx = VIxH V IOx = −4 mA, VIx = VIxH 0.0 0.1 V IOx = 20 µA, VIx = VIxH 0.0 0.4 V IOx = 4 mA, VIx = VIxH 1000 ns Mbps ns ns ns ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels PW 1 tPLH, tPHL PWD tPSK tPSKCD/tPSKOD Unit V 55 PW 100 40 50 50 tPSK tPSKCD 15 8 ns Mbps ns ns ps/°C ns ns tPSKCD 15 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDDA or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V or VISO, VCM = 1000 V, transient magnitude = 800 V tPLH, tPHL PWD 40 25 30 50 70 8 5 tR/tF |CMH| 25 2.5 35 ns kV/µs |CML| 25 35 kV/µs 1.0 Mbps fr 1 VDD1 is the power supply for the push-pull transformer. VDDA is the power supply of Side 1 of the ADuM447x. 3 The contributions of supply current values for all four channels are combined at identical data rates. 4 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 5 The power demands of the quiescent operation of the data channels were not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 6 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate. 2 Rev. 0 | Page 9 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet ELECTRICAL CHARACTERISTICS—5 V PRIMARY INPUT SUPPLY/15 V SECONDARY ISOLATED SUPPLY 4.5 V ≤ VDD1 = VDDA ≤ 5.5 V; VREG = VISO = 15 V; VDD2 = 5.0 V; fSW = 500 kHz; all voltages are relative to their respective grounds; see the application schematic in Figure 49. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDDA = 5.0 V, VREG = VISO = 15 V, VDD2 = 5.0 V. Table 4. DC-to-DC Converter Static Specifications Parameter DC-TO-DC CONVERTER SUPPLY Isolated Output Voltage Feedback Voltage Setpoint VDD2 Linear Regulator Regulator Voltage Symbol Min Typ Max Unit Test Conditions/Comments VISO 13.8 15 16.2 V VFB 1.15 1.25 1.37 V IISO = 0 mA, VISO = VFB × (R1 + R2)/R2 IISO = 0 mA 4.5 5.0 5.5 V mV/V Dropout Voltage Line Regulation VISO (LINE) 0.5 1 1.5 20 Load Regulation Output Ripple VISO (LOAD) VISO (RIP) 1 200 3 Output Noise VISO (NOISE) 500 mV p-p Switching Frequency fSW RON 1000 200 318 0.5 kHz kHz kHz Ω VUV+ VUV− VUVH 2.8 2.6 0.2 V V V 78 mA % 192 Switch On-Resistance Undervoltage Lockout, VDDA, VDD2 Supplies Positive Going Threshold Negative Going Threshold Hysteresis DC to 2 Mbps Data Rate 3 Maximum Output Supply Current 4 Efficiency at Maximum Output Current 5 iCoupler DATA CHANNELS DC to 2 Mbps Data Rate IDD1 Supply Current, No VISO Load ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 25 Mbps Data Rate (CRIZ Grade Only) IDD1 Supply Current, No VISO Load ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 Available VISO Supply Current 6 ADuM4470 ADuM4471 ADuM4472 ADuM4473 ADuM4474 IDD1 Supply Current, Full VISO Load IISO (MAX) 515 100 % mV p-p IDD1 (Q) VREG = 7 V to 15 V, IDD2 = 0 mA to 50 mA IDD2 = 50 mA IISO = 50 mA, VDD1 1 = VDDA 2 = 4.5 V to 5.5 V IISO = 20 mA to 80 mA 20 MHz bandwidth, COUT = 0.1 µF||47 µF, IISO = 100 mA 20 MHz bandwidth, COUT = 0.1 µF||47 µF, IISO = 100 mA ROC = 50 kΩ ROC = 270 kΩ VOC = VDD2 (open-loop) f ≤ 1 MHz, VISO = 5.0 V IISO = IISO (MAX), f ≤ 1 MHz IISO = 0 mA, f ≤ 1 MHz 25 27 29 31 33 45 45 45 45 45 mA mA mA mA mA IDD1 (D) 73 83 93 102 112 mA mA mA mA mA 91 89 86 83 80 425 mA mA mA mA mA mA IISO (LOAD) Rev. 0 | Page 10 of 36 IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz IISO = 0 mA, CL = 15 pF, f = 12.5 MHz fSW = 500 kHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 15 pF, f = 12.5 MHz CL = 0 pF, f = 0 MHz, VDD1 = VDDA = 5 V, IISO = 400 mA Data Sheet Parameter I/O Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages Logic Low Output Voltages AC SPECIFICATIONS ADuM447xARIZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH − tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM447xCRIZ Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH − tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing Directional Channels Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Symbol IIA, IIB, IIC, IID VIH VIL VOAH, VOBH, VOCH, VODH Min −20 2.0 Typ +0.01 VDDA − 0.3, VISO − 0.3 VDDA − 0.5, VISO − 0.5 Max +20 5.0 Unit µA V V V IOx = −20 µA, VIx = VIxH 4.8 V IOx = −4 mA, VIx = VIxH 0.8 VOAL, VOBL, VOCL, VODL 0.0 0.1 V IOx = 20 µA, VIx = VIxH 0.0 0.4 V IOx = 4 mA, VIx = VIxH 1000 ns Mbps ns ns ns ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels PW 1 tPLH, tPHL PWD tPSK tPSKCD/tPSKOD Test Conditions/Comments 55 PW 100 40 50 50 tPSK tPSKCD 15 6 ns Mbps ns ns ps/°C ns ns tPSKCD 15 ns CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VIx = VDDA or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V or VISO, VCM = 1000 V, transient magnitude = 800 V tPLH, tPHL PWD 40 25 30 45 60 6 5 tR/tF |CMH| 25 2.5 35 ns kV/µs |CML| 25 35 kV/µs 1.0 Mbps fr 1 VDD1 is the power supply for the push-pull transformer. VDDA is the power supply of Side 1 of the ADuM447x. The contributions of supply current values for all four channels are combined at identical data rates. 4 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget. 5 The power demands of the quiescent operation of the data channels were not separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of the internal power consumption. 6 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum data rate. 2 3 Rev. 0 | Page 11 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet PACKAGE CHARACTERISTICS Table 5. Parameter Resistance (Input to Output) 1 Capacitance (Input to Output)1 IC Junction to Ambient Thermal Resistance Symbol RI-O CI-O θJA Thermal Shutdown Thermal Shutdown Threshold Thermal Shutdown Hysteresis TSSD TSSD-HYS 1 2 Min Typ 1012 2.2 45 Max 150 20 Unit Ω pF °C/W °C °C Test Conditions/Comments f = 1 MHz Thermocouple located at center of package underside, test conducted on 4-layer board with thin traces 2 TJ rising The device is considered a 2-terminal device: Pin 1 to Pin 10 are shorted together; and Pin 11 to Pin 20 are shorted together. See the Thermal Analysis section for thermal model definitions. REGULATORY APPROVALS (PENDING) Table 6. UL Recognized under the UL 1577 component recognition program 1 Single protection, 5000 V rms isolation voltage File E214100 1 2 CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 600 V rms (848 V peak) maximum working voltage Reinforced insulation per CSA60950-1-03 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage Reinforced insulation per IEC 60601-1 250 V rms (353 V peak) maximum working voltage File 205078 VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 849 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM447x is proof tested by applying an insulation test voltage of ≥6000 V rms for 1 sec (current leakage detection limit = 10 µA). In accordance with DIN V VDE V 0884-10, each of the ADuM447x is proof tested by applying an insulation test voltage of ≥1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY-RELATED SPECIFICATIONS Table 7. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 5000 >8.0 Unit V rms mm Minimum External Tracking (Creepage) L(I02) >8.3 mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group 0.017 min mm >400 V II Rev. 0 | Page 12 of 36 Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure maintenance of the safety data. The asterisk (*) marking on packages denotes DIN V VDE V 0884-10 approval. Table 8. Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Test Conditions/Comments VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values Symbol Characteristic Unit VIORM Vpd (m) I to IV I to IV I to III 40/105/21 2 849 1592 V peak V peak 1273 1018 V peak V peak VIOTM VIOSM 6000 6000 V peak V peak TS PVDDA, PVREG RS 150 2.78 >109 °C W Ω Vpd (m) VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 10 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 7) Case Temperature Side 1, Side 2 PVDDA, PVREG Power Dissipation Insulation Resistance at TS VIO = 500 V 500 400 300 200 100 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 10991-007 SAFE OPERATING VDD1 CURRENT (mA) 600 Figure 7. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-10 RECOMMENDED OPERATING CONDITIONS Table 9. Parameter Temperature Operating Temperature Supply Voltage VDD1 at VISO = 3.3 V VDD1 at VISO = 3.3 V VDD1 at VISO = 5.0 V Load Minimum Load Symbol Min Max Unit TA −40 +105 °C VDD1 VDD1 VDD1 3.0 4.5 4.5 3.6 5.5 5.5 V V V IISO (MIN) 10 Rev. 0 | Page 13 of 36 mA ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 10. Parameter Storage Temperature Range (TST) Ambient Operating Temperature Range (TA) Supply Voltages VDDA, VDD2 1, 2 VREG, X1, X21 Input Voltage (VIA, VIB, VIC, VID) Output Voltage (VOA, VOB, VOC, VOD) Average Output Current per Pin Common-Mode Transients 3 1 Rating −55°C to +150°C −40°C to +105°C −0.5 V to +7.0 V −0.5 V to +20.0 V −0.5 V to +VDDI + 0.5 V −0.5 V to VDDO +0.5 V −10 mA to +10 mA −100 kV/µs to +100 kV/µs All voltages are relative to their respective ground. VDD1 is the power supply for the push-pull transformer, and VDDA is the power supply of Side 1 of the ADuM447x. 3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latchup or permanent damage. 2 Table 11. Maximum Continuous Working Voltage Supporting 50-Year Minimum Lifetime1 Parameter AC Voltage, Bipolar Waveform AC Voltage, Unipolar Waveform DC Voltage 1 Max 848 Unit V peak 848 V peak 848 V peak Constraint 50-year minimum lifetime 50-year minimum lifetime 50-year minimum lifetime Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more information. ESD CAUTION Rev. 0 | Page 14 of 36 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS X1 1 20 VREG *GND1 2 NC 3 X2 4 VIA 5 19 GND2* ADuM4470 TOP VIEW (Not to Scale) 18 VDD2 17 FB 16 VOA VIB 6 15 VOB VIC 7 14 VOC VID 8 13 VOD VDDA 9 *GND1 10 12 OC 11 GND2* *PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. 10991-008 NOTES 1. THE PIN LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THIS PIN TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. Figure 8. ADuM4470 Pin Configuration Table 12. ADuM4470 Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 NC X2 VIA VIB VIC VID VDDA GND2 OC 13 14 15 16 17 VOD VOC VOB VOA FB 18 VDD2 20 VREG Description Transformer Driver Output 1. Ground Reference for Isolator Primary. This pin is not connected internally (see Figure 8). Transformer Driver Output 2. Logic Input A. Logic Input B. Logic Input C. Logic Input D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1. Connect a 0.1 μF bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Output D. Logic Output C. Logic Output B. Logic Output A. Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB × (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. Internal Supply Voltage Pin for the Secondary Side. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 μF bypass capacitor from VDD2 to GND2. Input of the Internal Regulator to Power the Secondary Side Controller. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V. Rev. 0 | Page 15 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 X1 1 20 VREG *GND1 2 19 GND2* 18 VDD2 17 FB 16 VOA VIB 6 15 VOB VIC 7 14 VOC VOD 8 13 VID VDDA 9 12 OC *GND1 10 11 GND2* NC 3 X2 4 VIA 5 ADuM4471 TOP VIEW (Not to Scale) Data Sheet *PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. 10991-009 NOTES 1. THE PIN LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THIS PIN TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. Figure 9. ADuM4471 Pin Configuration Table 13. ADuM4471 Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 NC X2 VIA VIB VIC VOD VDDA GND2 OC 13 14 15 16 17 VID VOC VOB VOA FB 18 VDD2 20 VREG Description Transformer Driver Output 1. Ground Reference for Isolator Primary. This pin is not connected internally (see Figure 9). Transformer Driver Output 2. Logic Input A. Logic Input B. Logic Input C. Logic Output D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1. Connect a 0.1 µF bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Input D. Logic Output C. Logic Output B. Logic Output A. Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB × (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. Internal Supply Voltage Pin for the Secondary Side. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 µF bypass capacitor from VDD2 to GND2. Input of the Internal Regulator to Power the Secondary Side Controller. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V. Rev. 0 | Page 16 of 36 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 X1 1 20 VREG *GND1 2 19 GND2* 18 VDD2 17 FB 16 VOA VIB 6 15 VOB VOC 7 14 VIC VOD 8 13 VID VDDA 9 12 OC *GND1 10 11 GND2* NC 3 X2 4 VIA 5 ADuM4472 TOP VIEW (Not to Scale) *PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. 10991-010 NOTES 1. THE PIN LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THIS PIN TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. Figure 10. ADuM4472 Pin Configuration Table 14. ADuM4472 Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 NC X2 VIA VIB VOC VOD VDDA GND2 OC 13 14 15 16 17 VID VIC VOB VOA FB 18 VDD2 20 VREG Description Transformer Driver Output 1. Ground Reference for Isolator Primary. This pin is not connected internally (see Figure 10). Transformer Driver Output 2. Logic Input A. Logic Input B. Logic Output C. Logic Output D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1. Connect a 0.1 µF bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Input D. Logic Input C. Logic Output B. Logic Output A. Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB × (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. Internal Supply Voltage Pin for the Secondary Side. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 µF bypass capacitor from VDD2 to GND2. Input of the Internal Regulator to Power the Secondary Side Controller. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V. Rev. 0 | Page 17 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 X1 1 20 VREG *GND1 2 19 GND2* 18 VDD2 17 FB 16 VOA VOB 6 15 VIB VOC 7 14 VIC VOD 8 13 VID VDDA 9 12 OC *GND1 10 11 GND2* NC 3 X2 4 VIA 5 ADuM4473 TOP VIEW (Not to Scale) Data Sheet *PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. 10991-011 NOTES 1. THE PIN LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THIS PIN TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. Figure 11. ADuM4473 Pin Configuration Table 15. ADuM4473 Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 NC X2 VIA VOB VOC VOD VDDA GND2 OC 13 14 15 16 17 VID VIC VIB VOA FB 18 VDD2 20 VREG Description Transformer Driver Output 1. Ground Reference for Isolator Primary. This pin is not connected internally (see Figure 11). Transformer Driver Output 2. Logic Input A. Logic Output B. Logic Output C. Logic Output D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1. Connect a 0.1 µF bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Input D. Logic Input C. Logic Input B. Logic Output A. Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB × (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. Internal Supply Voltage Pin for the Secondary Side. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 µF bypass capacitor from VDD2 to GND2. Input of the Internal Regulator to Power the Secondary Side Controller. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V. Rev. 0 | Page 18 of 36 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 X1 1 20 *GND1 2 19 GND2* 18 VDD2 NC 3 X2 4 ADuM4474 VREG 17 FB 16 VIA VOB 6 15 VIB VOC 7 14 VIC VOD 8 13 VID VOA 5 TOP VIEW (Not to Scale) VDDA 9 12 OC *GND1 10 11 GND2* *PIN 2 AND PIN 10 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND1 IS RECOMMENDED. PIN 11 AND PIN 19 ARE INTERNALLY CONNECTED, AND CONNECTING BOTH TO GND2 IS RECOMMENDED. 10991-012 NOTES 1. THE PIN LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THIS PIN TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. Figure 12. ADuM4474 Pin Configuration Table 16. ADuM4474 Pin Function Descriptions Pin No. 1 2, 10 3 4 5 6 7 8 9 11, 19 12 Mnemonic X1 GND1 NC X2 VOA VOB VOC VOD VDDA GND2 OC 13 14 15 16 17 VID VIC VIB VIA FB 18 VDD2 20 VREG Description Transformer Driver Output 1. Ground Reference for Isolator Primary. This pin is not connected internally (see Figure 12). Transformer Driver Output 2. Logic Output A. Logic Output B. Logic Output C. Logic Output D. Primary Supply Voltage 3.0 V to 5.5 V. Connect to VDD1. Connect a 0.1 µF bypass capacitor from VDDA to GND1. Ground Reference for Isolator Side 2. Oscillator Control Pin. When OC = logic high = VDD2, the secondary controller runs open-loop. To regulate the output voltage, connect a resistor between the OC pin and GND2, and the secondary controller runs at a frequency of 200 kHz to 1 MHz, as programmed by the resistor value. Logic Input D. Logic Input C. Logic Input B. Logic Input A. Feedback Input from the Secondary Output Voltage, VISO. Use a resistor divider from VISO to the FB pin to make the VFB voltage equal to the 1.25 V internal reference level using the VISO = VFB × (R1 + R2)/R2 formula. The resistor divider is required even in open-loop mode to provide soft start. Internal Supply Voltage Pin for the Secondary Side. When a sufficient external voltage is supplied to VREG, the internal regulator regulates the VDD2 pin to 5.0 V. Otherwise, VDD2 should be in the 3.0 V to 5.5 V range. Connect a 0.1 µF bypass capacitor from VDD2 to GND2. Input of the Internal Regulator to Power the Secondary Side Controller. VREG should be in the 5.5 V to 15 V range to regulate the VDD2 output to 5.0 V. Rev. 0 | Page 19 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 90 1500 1400 80 1300 1200 70 1100 EFFICIENCY (%) fSW (kHz) 1000 900 800 700 600 500 60 50 40 30 400 20 200 +105°C +25°C –40°C 10 100 0 50 100 150 200 250 300 350 400 450 500 ROC (kΩ) 0 10991-013 0 0 100 150 200 250 300 350 400 LOAD CURRENT (mA) Figure 16. 5 V Input to 5 V Output Efficiency over Temperature with Coilcraft Transformer (CR7983-CL) at 500 kHz fSW Figure 13. Switching Frequency (fSW) vs. ROC Resistance 90 80 80 70 70 60 EFFICIENCY (%) 60 50 40 30 0 0 50 100 150 200 250 300 350 400 LOAD CURRENT (mA) 40 30 20 fSW = 1MHz fSW = 700kHz fSW = 500kHz fSW = 200kHz 10 50 5V IN TO 5V OUT 5V IN TO 3.3V OUT 3.3V IN TO 3.3V OUT 10 0 Figure 14. Typical Efficiency at 5 V Input to 5 V Output at Various Switching Frequencies with 1:2 Coilcraft Transformer (CR7983-CL) 0 50 100 150 200 250 300 350 400 LOAD CURRENT (mA) 10991-017 20 10991-014 EFFICIENCY (%) 50 10991-016 300 Figure 17. Single-Supply Efficiency with Coilcraft Transformer (CR7983-CL) at 500 kHz fSW 70 90 80 60 70 EFFICIENCY (%) EFFICIENCY (%) 50 60 50 40 30 40 30 20 fSW = 1MHz fSW = 700kHz fSW = 500kHz fSW = 200kHz 0 0 50 100 150 200 250 LOAD CURRENT (mA) 300 350 400 0 10991-015 10 fSW = 1MHz fSW = 700kHz fSW = 500kHz fSW = 200kHz 10 Figure 15. Typical Efficiency at 5 V Input to 5 V Output at Various Switching Frequencies with1:2 Halo Transformer (TGSAD-260V8LF) 0 50 100 LOAD CURRENT (mA) 150 200 10991-018 20 Figure 18. Typical Efficiency at 3.3 V Input to 5 V Output at Various Switching Frequencies with 1:3 Coilcraft Transformer (CR7984-CL ) Rev. 0 | Page 20 of 36 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 70 80 60 70 60 EFFICIENCY (%) 40 30 20 40 30 20 10 +105°C +25°C –40°C 0 25 50 75 100 125 150 175 200 LOAD CURRENT (mA) 0 10991-019 0 Figure 19. Typical Efficiency at 3.3 V In to 5 V Out over Temperature with 1:3 Coilcraft Transformer (CR7984-CL) at 500 kHz fsw 0 70 60 60 EFFICIENCY (%) 70 30 20 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 LOAD CURRENT (mA) 40 50 60 70 80 90 100 110 120 130 140 50 40 30 10 Figure 20. 5 V Input to 15 V Output Efficiency at Various Switching Frequencies with 1: 3 Coilcraft Transformer (CR7984-CL) 5V IN TO 12V OUT 5V IN TO 15V OUT 0 10991-020 0 30 20 fSW = 1MHz fSW = 700kHz fSW = 500kHz fSW = 200kHz 10 20 Figure 22. 5 V Input to 15 V Output Efficiency over Temperature with Coilcraft Transformer (CR7984-CL) at 500 kHz fSW 80 40 10 LOAD CURRENT (mA) 80 50 +105°C +25°C –40°C 10991-022 10 EFFICIENCY (%) 50 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 LOAD CURRENT (mA) 10991-023 EFFICIENCY (%) 50 Figure 23. Double-Supply Efficiency with Coilcraft Transformer (CR7985-CL) at 500 kHz fSW 90 15 80 10 ICH (mA) 60 50 40 5 20 fSW = 1MHz fSW = 700kHz fSW = 500kHz fSW = 200kHz 10 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 LOAD CURRENT (mA) Figure 21. 5 V Input to 15 V Output Efficiency at Various Switching Frequencies with 1:3 Halo Transformer (TGSAD-290V8LF) VCC = 5V, VISO = 5V VCC = 5V, VISO = 3.3V VCC = 3.3V, VISO = 3.3V 0 0 5 10 15 DATA RATE (Mbps) 20 25 10991-024 30 10991-021 EFFICIENCY (%) 70 Figure 24. Typical Single-Supply ICH Supply Current per Forward Data Channel (15 pF Output Load) Rev. 0 | Page 21 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 30 15 Data Sheet VCC = 5V, VISO = 15V VCC = 5V, VISO = 12V 25 20 ICH (mA) ICH (mA) 10 15 10 5 0 5 10 15 20 25 DATA RATE (Mbps) 0 10991-025 0 0 10 15 20 25 DATA RATE (Mbps) Figure 25. Typical Single-Supply ICH Supply Current per Reverse Data Channel (15 pF Output Load) 5 5 10991-028 5 VCC = 5V, VISO = 5V VCC = 5V, VISO = 3.3V VCC = 3.3V, VISO = 3.3V Figure 28. Typical Double-Supply Current ICH Per Forward Data Channel (15 pF Output Load) 30 VCC = 5V, VISO = 5V VCC = 5V, VISO = 3.3V VCC = 3.3V, VISO = 3.3V VCC = 5V, VISO = 15V VCC = 5V, VISO = 12V 25 4 ICH (mA) IISO(D) (mA) 20 3 2 15 10 1 0 5 10 15 20 25 DATA RATE (Mbps) Figure 26. Typical Single-Supply IISO(D) Dynamic Supply Current per Output Channel (15 pF Output Load) 0 10 15 20 25 Figure 29. Typical Double-Supply ICH Supply Current per Reverse Data Channel (15 pF Output Data) 5 VCC = 5V, VISO = 5V VCC = 5V, VISO = 3.3V VCC = 3.3V, VISO = 3.3V 4 4 3 3 2 5 DATA RATE (Mbps) IISO(D) (mA) VCC = 5V, VISO = 15V VCC = 5V, VISO = 12V 2 1 1 0 5 10 15 DATA RATE (Mbps) 20 25 0 10991-027 0 Figure 27. Typical Single-Supply IISO(D) Dynamic Supply Current per Input Channel (15 pF Output Load) 0 5 10 15 DATA RATE (Mbps) 20 25 10991-030 IISO(D) (mA) 5 0 10991-026 0 10991-029 5 Figure 30. Typical Double-Supply IISO(D) Dynamic Supply Current per Output Channel (15 pF Output Load) Rev. 0 | Page 22 of 36 Data Sheet 5 VCC = 5V, VISO = 15V VCC = 5V, VISO = 12V 4 4 3 3 VISO (V) IISO(D) (mA) 5 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 2 2 1 1 0 5 10 15 20 25 DATA RATE (Mbps) 0 10991-031 0 Figure 31. Typical Double-Supply IISO(D) Dynamic Supply Current per Input Channel 0 5 10 15 20 25 30 TIME (ms) 10991-034 LOAD = 10mA LOAD = 50mA LOAD = 400mA Figure 34. Typical VISO Startup 3.3 V Input to 3.3 V Output with 10 mA, 50 mA, and 250 mA Output Load 6 5 5 4 VISO (V) VISO (V) 4 3 3 2 2 1 LOAD = 10mA LOAD = 50mA LOAD = 400mA LOAD = 10mA LOAD = 50mA LOAD = 400mA 0 5 10 15 20 25 30 TIME (ms) 0 10991-032 0 Figure 32. Typical VISO Startup 5 V Input to 5 V Output with 10 mA, 50 mA, and 400 mA Output Load 0 5 10 15 20 25 30 TIME (ms) 10991-035 1 Figure 35. Typical VISO Startup 5 V Input to 15 V Output with 10 mA, 20 mA, and 100 mA Output Load 5 5.75 COUT = 47µF, L1 = 47µH 5.25 VISO (V) 4 VISO (V) 4.75 3 4.25 5.75 COUT = 47µF, L1 = 100µH 5.25 4.75 2 1 0 0 5 10 15 TIME (ms) 20 25 30 Figure 33. Typical VISO Startup 5 V Input to 3.3 V Output with 10 mA, 50 mA, and 400 mA Output Load 90% LOAD 0.5 10% LOAD 0 –2 10991-033 LOAD = 10mA LOAD = 50mA LOAD = 400mA 0 2 4 6 TIME (ms) 8 10 12 14 10991-036 ILOAD (A) 4.25 1.0 Figure 36. Typical VISO Load Transient Response 5 V Input to 5 V Output at 10% to 90% of 400 mA Load at 500 kHz fSW Rev. 0 | Page 23 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 4.0 3.5 4.75 3.0 3.5 4.75 3.0 4.25 1.0 2.5 1.0 ILOAD (A) 5.25 90% LOAD 0.5 10% LOAD 0 –2 0 2 4 6 8 10 12 14 TIME (ms) Figure 37. Typical VISO Load Transient Response 5 V Input to 5 V Output at 10% to 90% of 400 mA Load at 500 kHz fSW with 0.1 µF Feedback Capacitor 3.0 VISO (V) 3.0 COUT = 47µF, L1 = 100µH 3.0 3.0 2.5 1.0 2.5 1.0 ILOAD (A) 3.5 90% LOAD 10% LOAD 2 4 6 8 10 12 14 TIME (ms) Figure 38. Typical VISO Load Transient Response 5 V Input to 3.3 V Output at 10% to 90% of 400 mA Load at 500 kHz fSW 14 VISO (V) 3.0 3.0 14 2.5 1.0 12 0.2 ILOAD (A) 16 10% LOAD 0 2 4 6 TIME (ms) 8 90% LOAD 0 2 10 12 14 Figure 39. Typical VISO Load Transient Response 5 V Input to 3.3 V Output at 10% to 90% of 400 mA Load at 500 kHz fSW with 0.1 µF Feedback Capacitor 4 8 6 10 12 14 COUT = 47µF, L1 = 47µH 12 18 3.5 0 –2 14 Figure 41. Typical VISO Load Transient Response 3.3 V Input to 3.3 V Output at 10% to 90% of 250 mA Load at 500 kHz fSW with 0.1 µF Feedback Capacitor 16 90% LOAD 12 10% LOAD 3.5 0.5 10 COUT = 47µF, L1 = 100µH 18 COUT = 47µF, L1 = 100µH 8 TIME (ms) COUT = 47µF, L1 = 47µH 2.5 4.0 6 0.5 0 –2 COUT = 47µF, L1 = 100µH 90% LOAD 0.1 10% LOAD 0 –2 10991-039 VISO (V) 4.0 4 COUT = 47µF, L1 = 47µH 2.5 4.0 3.5 0 2 4.0 3.5 0 –2 0 Figure 40. Typical VISO Load Transient Response 3.3 V Input to 3.3 V Output at 10% to 90% of 250 mA Load at 500 kHz fSW 3.5 0.5 90% LOAD 10% LOAD TIME (ms) COUT = 47µF, L1 = 47µH 2.5 4.0 COUT = 47µF, L1 = 100µH 0.5 0 –2 10991-038 ILOAD (A) VISO (V) 4.0 ILOAD (A) 2.5 4.0 10991-041 COUT = 47µF, L1 = 100µH COUT = 47µF, L1 = 47µH 0 2 4 6 TIME (ms) 8 10 12 14 10991-042 4.25 5.75 VISO (V) 5.25 10991-040 COUT = 47µF, L1 = 47µH 10991-037 ILOAD (A) VISO (V) 5.75 Data Sheet Figure 42. Typical VISO Load Transient Response 5 V Input to 15 V Output at 10% to 90% of 100 mA Load at 500 kHz fSW Rev. 0 | Page 24 of 36 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 18 COUT = 47µF, L1 = 47µH 3.36 16 12 18 VISO (V) VISO (V) 14 COUT = 47µF, L1 = 100µH 3.32 3.28 16 14 3.24 20 X1 (V) 90% LOAD 0.1 10 0 –2 0 2 4 6 8 10 12 14 TIME (ms) 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (ms) Figure 43. Typical VISO Load Transient Response 5 V Input to 15 V Output at 10% to 90% of 100 mA Load at 500 kHz fSW with 0.1 µF Feedback Capacitor 10991-046 10% LOAD 10991-043 ILOAD (A) 12 0.2 Figure 46. Typical VISO Output Ripple, 3.3 V Input to 3.3 V Output at 250 mA Load at 500 kHz fSW 15.08 5.06 15.06 15.04 VISO (V) VISO (V) 5.02 4.98 15.02 15.00 14.98 14.96 10 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (ms) Figure 44. Typical VISO Output Ripple, 5 V Input to 5 V Output at 400 mA Load at 500 kHz fSW VISO (V) 3.32 3.28 10 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (ms) 10991-045 X1 (V) 3.24 20 –1.5 0 –2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0 TIME (ms) Figure 47. Typical VISO Output Ripple, 5 V Input to 15 V Output at 100 mA Load at 500 kHz fSW 3.36 0 –2.0 10 Figure 45. Typical VISO Output Ripple, 5 V Input to 3.3 V Output at 400 mA Load at 500 kHz fSW Rev. 0 | Page 25 of 36 10991-047 X1 (V) 14.94 20 10991-044 X1 (V) 4.94 20 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet APPLICATIONS INFORMATION THEORY OF OPERATION L1 47µH D1 T1 VDD1 CFB R1 CIN D2 VDD1 X1 1 NC 3 X2 4 I/OA 5 VDD1 0.1µF 20 VREG ADuM4470/ ADuM4471/ ADuM4472/ ADuM4473/ ADuM4474 0.1µF 19 GND2 18 VDD2 +5V 17 FB VFB 16 I/OA I/OB 6 15 I/OB I/OC 7 14 I/OC R2 I/OD 8 13 I/OD VDDA 9 12 OC GND1 10 11 GND2 ROC 100kΩ 10991-048 GND1 2 VISO = VFB × (R1 + R2)/R2 FOR VISO = 3.3V OR 5V CONNECT VREG , VDD2 , AND VISO. Figure 48. Single Power Supply L1 47µH D1 T1 VISO = +12V TO +24V COUT1 47µF VDD1 CIN UNREGULATED +6V TO +12V COUT2 47µF D2 L2 47µH D3 R1 D4 CFB VDD1 NC 3 X2 4 I/OA 5 VDD1 0.1µF 20 VREG ADuM4470/ ADuM4471/ ADuM4472/ ADuM4473/ ADuM4474 19 GND2 0.1µF 18 VDD2 +5V 17 FB VFB 16 I/OA I/OB 6 15 I/OB I/OC 7 14 I/OC I/OD 8 13 I/OD VDDA 9 12 OC GND1 10 11 GND2 R2 ROC 100kΩ 10991-049 X1 1 GND1 2 APPLICATION SCHEMATICS The ADuM447x have three main application schematics (see Figure 48 to Figure 50). Figure 48 has a center-tapped secondary and two Schottky diodes providing full wave rectification for a single output, typically for power supplies of 3.3 V, 5 V, 12 V, and 15 V. For single supplies when VISO = 3.3 V or VISO = 5 V, see the note in Figure 48 about connecting together VREG, VDD2, and VISO. Figure 49 is a voltage doubling circuit that can be used for a single supply whose output exceeds 15 V, which is the largest supply that can be connected to the regulator input, Pin VREG, of the part. With Figure 49, the output voltage can be as high as 24 V and the VREG pin only about 12 V. When using the circuit shown in Figure 49, to obtain an output voltage lower than 10 V (for example, VDD1 = 3.3 V, VISO = 5 V), connect VREG to VISO directly. Figure 50, which also uses a voltage doubling secondary circuit, shows an example of a coarsely regulated, positive power supply and an unregulated, negative power supply for outputs of approximately ±5 V, ±12 V, and ±15 V. For any circuit in Figure 48, Figure 49, or Figure 50, the isolated output voltage (VISO) can be set using the voltage dividers, R1 and R2 (with values of 1 kΩ to 100 kΩ), in the application schematics using the following equation: VISO = +3.3V TO +15V COUT 47µF VISO = VFB × (R1 + R2)/R2 FOR VISO = 15V OR LESS, VREG CAN CONNECT TO VISO. Figure 49. Doubling Power Supply L1 47µH D1 T1 VISO = COARSELY REGULATED +5V TO +15V COUT1 47µF VDD1 UNREGULATED –5V TO –15V COUT2 47µF D2 CIN L2 47µH D3 R1 D4 CFB VDD1 X1 1 GND1 2 NC 3 X2 4 I/OA 5 I/OB 6 VDD1 0.1µF R1 + R2 R2 where VFB is the internal feedback voltage, which is approximately 1.25 V. V ISO = V FB × 20 VREG ADuM4470/ ADuM4471/ ADuM4472/ ADuM4473/ ADuM4474 19 GND2 0.1µF 18 VDD2 +5V 17 FB VFB 16 I/OA R2 15 I/OB I/OC 7 14 I/OC I/OD 8 13 I/OD VDDA 9 12 OC GND1 10 11 GND2 ROC 100kΩ VISO = VFB × (R1 + R2)/R2 Figure 50. Positive and Unregulated Negative Supply Rev. 0 | Page 26 of 36 10991-050 The dc-to-dc converter section of the ADuM447x uses a secondary side controller architecture with isolated pulse-width modulation (PWM) feedback. VDD1 power is supplied to an oscillating circuit that switches current to the primary of an external power transformer using internal push-pull switches at the X1 and X2 pins. Power transferred to the secondary side of the transformer is full-wave rectified with external Schottky diodes (D1 and D2), filtered with the L1 inductor and COUT capacitor, and regulated to the isolated power supply voltage from 3.3 V to 15 V. The secondary (VISO) side controller regulates the output by using a feedback voltage, VFB, from a resistor divider on the output and creating a PWM control signal that is sent to the primary (VDD1) side by a dedicated iCoupler data channel labeled VFB. The primary side PWM converter varies the duty cycle of the X1 and X2 switches to modulate the oscillator circuit and control the power being sent to the secondary side. This feedback allows for significantly higher power and efficiency. The ADuM447x implements undervoltage lockout (UVLO) with hysteresis on the VDDA and VDD2 power inputs. This feature ensures that the converter does not go into oscillation due to noisy input power or slow power-on ramp rates. A minimum load current of 10 mA is recommended to ensure optimum load regulation. Smaller loads can generate excess noise on the output because of short or erratic PWM pulses. Excess noise generated this way can cause regulation problems in some circumstances. Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 TRANSFORMER DESIGN Transformers that have been designed for use in the circuits shown in Figure 48, Figure 49, and Figure 50 are listed in Table 17. The design of a transformer for the ADuM447x can differ from some isolated dc-to-dc converter designs that do not regulate the output voltage. The output voltage is regulated by a PWM controller in the ADuM47x that varies the duty cycle of the primary side switches in response to a secondary side feedback voltage, VFB, received through an isolated digital channel. The internal controller has a limit of 40% maximum duty cycle. TRANSFORMER TURNS RATIO To determine the transformer turns ratio, and taking into account the losses for the primary switches and the losses for the secondary diodes and inductors, the external transformer turns ratio for the ADuM447x can be calculated by NS VISO + VD = N P VDD1 ( MIN ) × D × 2 (1) where: NS/NP is the primary to secondary turns ratio. VISO is the isolated output supply voltage. VD is the Schottky diode voltage drop (0.5 V maximum). VDD1(MIN) is the minimum input supply voltage. D is the duty cycle = 0.30 for a 30% typical duty cycle, 40% is maximum, and a multiplier factor of 2 is used for the pushpull switching cycle. In Figure 50, the circuit also uses double windings and diode pairs to create a doubler circuit; however, because a positive and negative output voltage is created, VISO is used in the equation: NS VISO + VD = N P VDD1 ( MIN ) × D × 2 (3) where: NS/NP is the primary to secondary turns ratio. VISO is the isolated output supply voltage and is used in the equation because the circuit uses two pairs of diodes, creating a doubler circuit with a positive and negative output. VD is the Schottky diode voltage drop (0.5 V maximum). VDD1(MIN) is the minimum input supply voltage, and a multiplier factor of 2 is used for the push-pull switching cycle. D is the duty cycle; in this case, a higher duty cycle of D = 0.35 for a 35% typical duty cycle (40% is maximum) was used in the Figure 50 circuit to reduce the maximum voltages seen by the diodes for a ±15 V supply. For example, using the circuit in Figure 50 and the +5 V to ±15 V reference design in Table 17, with VDD1(MIN) = 4.5 V, the turns ratio is NS/NP = 5. TRANSFORMER ET CONSTANT For example, using the circuit in Figure 48 and the 5 V to 5 V reference design in Table 17, with VDD1 (MIN) = 4.5 V, the turns ratio is NS/NP = 2. For a similar 3.3 V input to 3.3 V output, isolated single power supply, and with VDD1(MIN) = 3.0 V, the turns ratio is also NS/NP = 2. Therefore, the same transformer turns ratio NS/NP = 2 can be used for the three single power applications (5 V to 5 V, 5 V to 3.3 V, and 3.3 V to 3.3 V). In Figure 49, the circuit uses double windings and diode pairs to create a doubler circuit; therefore, half the output voltage, VISO/2, is used in the equation: VISO + VD NS 2 = N P VDD1 ( MIN ) × D × 2 For example, using the circuit in Figure 49 and the 5 V to 15 V reference design in Table 17, with VDD1(MIN) = 4.5 V, the turns ratio is NS/NP = 3. The next transformer design factor to consider is the ET constant. This constant determines the minimum V × µs constant of the transformer over the operating temperature. ET values of 14 V × µs and 18 V × µs were selected for the ADuM447x designs listed in Table 17 using the following equation: ET ( MIN ) = VDD1 ( MAX ) f SW ( MIN ) × 2 (4) where: VDD1(MAX) is the maximum input supply voltage. fSW(MIN) is the minimum primary switching frequency = 300 kHz in startup, and a multiplier factor of 2 is used for the push-pull switching cycle. (2) NS/NP is the primary to secondary turns ratio. VISO/2 is used in the equation because the circuit uses two pairs of diodes creating a doubler circuit. VD is the Schottky diode voltage drop (0.5 V maximum). VDD1(MIN) is the minimum input supply voltage. D is duty cycle, which equals 0.30 for a 30% typical duty cycle, 40% is maximum, and a multiplier factor of 2 is used for the push-pull switching cycle. Rev. 0 | Page 27 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 TRANSFORMER PRIMARY INDUCTANCE AND RESISTANCE Another important characteristic of the transformer for designs with the ADuM447x is the primary inductance. Transformers for the ADuM447x are recommended to have between 60 μH to 100 μH of inductance per primary winding. Values of primary inductance in this range are needed for smooth operation of the ADuM447x pulse-by-pulse current-limit circuit, which can help protect against buildup of saturation currents in the transformer. If the inductance is specified for the total of both primary windings, for example, as 400 μH, the inductance of one winding is ¼ of two equal windings, or 100 μH. Another important characteristic of the transformer for designs with the ADuM447x is primary resistance. Primary resistance as low as is practical (less than 1 Ω) helps reduce losses and improves efficiency. The dc primary resistance can be measured and specified, and is shown for the transformers in Table 17. TRANSFORMER ISOLATION VOLTAGE Isolation voltage and isolation type should be determined for the requirements of the application and then specified. The transformers in Table 17 have been specified for 2500 V rms for supplemental or basic isolation and for 1500 V rms functional isolation. Other isolation levels and isolation voltages can be specified and requested from the manufacturers in Table 17 or from other manufacturers. SWITCHING FREQUENCY The ADuM447x switching frequency can be adjusted from 200 kHz to 1 MHz by changing the value of the ROC resistor shown in Figure 48, Figure 49, and Figure 50. The value of the ROC resistor needed for the desired switching frequency can be Data Sheet determined from the switching frequency vs. the ROC resistance curve shown in Figure 13. The output filter inductor value and output capacitor value for the ADuM447x application schematics have been designed to be stable over the switching frequency range from 500 kHz to 1 MHz, when loaded from 10% to 90% of the maximum load. The ADuM447x also has an open-loop mode where the output voltage is not regulated and is dependent on the transformer turns ratio, NS/NP, and the conditions of the output, including output load current and the losses in the dc-to-dc converter circuit. This open-loop mode is selected when the OC pin is connected high to the VDD2 pin. In open-loop mode, the switching frequency is 318 kHz. TRANSIENT RESPONSE The load transient response of the output voltage of the ADuM447x for 10% to 90% of the full load is shown in Figure 36 to Figure 43 for the application schematics in Figure 48 to Figure 50. The response shown is slow but stable and can have more output change than desired for some applications. The output voltage change with load transient has been reduced, and the output has been shown to remain stable by adding more inductance to the output circuits, as shown in the second VISO output waveform in Figure 36 to Figure 43. For additional improvement in transient response, add a 0.1 μF ceramic capacitor (CFB) in parallel with the high feedback resistor. As shown in Figure 36 to Figure 43, this value helps reduce the overshoot and undershoot during load transients. Table 17. Transformer Reference Designs Part No. CR7983-CL CR7984-CL CR7985-CL TGRAD-560V8LF TGRAD-590V8LF Manufacturer Coilcraft Coilcraft Coilcraft Halo Electronics Halo Electronics Turns Ratio, PRI:SEC 1CT:2CT 1CT:3CT 1CT:5CT 1CT:2CT 1CT:3CT ET Constant (V × μs Min) 18 18 18 14 14 Total Primary Inductance (μH) 256 256 256 398 398 Rev. 0 | Page 28 of 36 Total Primary Resistance (Ω) 0.2 0.2 0.2 0.8 0.8 Isolation Voltage (rms) 5000 5000 5000 5000 5000 Isolation Type Reinforced Reinforced Reinforced Supplemental Supplemental Reference Figure 48 Figure 49 Figure 50 Figure 48 Figure 49 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 COMPONENT SELECTION PRINTED CIRCUIT BOARD (PCB) LAYOUT Power supply bypassing is required at the input and output supply pins. Note that a low ESR ceramic bypass capacitor of 0.1 µF is required on Side 1 between Pin 9 and Pin 10, and on Side 2 between Pin 18 and Pin 19, as close to the chip pads as possible. Note that the total lead length between the ends of the low ESR capacitor and the VDDx and GNDx pins must not exceed 2 mm. See Figure 51 for the recommended PCB layout. Inductors must be selected based on the value and supply current needed. Most applications with switching frequencies between 500 kHz and 1 MHz and load transients between 10% and 90% of full load are stable with the 47 µH inductor value listed in Table 18. Values as large as 200 µH can be used for power supply applications with a switching frequency as low as 200 kHz to help stabilize the output voltage or for improved load transient response (see Figure 36 to Figure 39). Inductors in a small 1212 or 1210 size are listed in Table 18 with a 47 µH value and a 0.41 A current rating to handle the majority of applications below a 400 mA load, and with a 100 µH value and a 0.34 A current rating to handle a load to 300 mA. Schottky diodes are recommended for their low forward voltage to reduce losses and their high reverse voltage of up to 40 V to withstand the peak voltages available in the doubling circuit shown in Figure 49 and Figure 50. Table 18. Suggested Components Part Number GRM32ER71A476KE15L Manufacturer Murata GRM32ER71C226KEA8L Murata GRM31CR71A106KA01L Murata MBR0540T1-D ON Semiconductor LQH3NPN470MM0 Murata ME3220-104KL Coilcraft LQH6PPN470M43 Murata LQH6PPN101M43 Murata Value 47 µF, 10 V, X7R, 1210 22 µF, 16 V, X7R, 1210 10 µF, 10 V, X7R, 1206 0.5 A, 40 V, Schottky, SOD-123 47 µH, 0.41 A, 1212 100 µH, 0.34 A, 1210 47 µH, 1.10 A, 2424 100 µH, 0.80 A, 2424 VREG GND2 NC VDD2 X2 FB VIA/VOA VOA/VIA VIB/VOB VOB/VIB VIC/VOC VOC/VIC VID/VOD VOD/VID VDDA OC GND1 GND2 10991-051 The power supply section of the ADuM447x uses a high oscillator frequency to efficiently pass power through the external power transformer. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor; ripple suppression and proper regulation require a large value capacitor. To suppress noise and reduce ripple, large-valued ceramic capacitors of X5R or X7R dielectric type are recommended. The recommended capacitor value is 10 µF for VDD1 and 47 µF for VISO. These capacitors have a low ESR and are available in moderate 1206 or 1210 sizes for voltages up to 10 V. For output voltages larger than 10 V, two 22 µF ceramic capacitors can be used in parallel. See Table 18 for suggested components. X1 GND1 Figure 51. Recommended PCB Layout In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause voltage differentials between pins, exceeding the absolute maximum ratings specified in Table 10, thereby leading to latch-up and/or permanent damage. The ADuM447x are power devices that dissipate about 1 W of power when fully loaded and running at maximum speed. Because it is not possible to apply a heat sink to an isolation device, the devices primarily depend on heat dissipation into the PCB through the GNDx pins. If the devices are used at high ambient temperatures, take care to provide a thermal path from the GNDx pins to the PCB ground plane. The board layout shows enlarged pads for the GNDx pins (Pin 2 and Pin 10 on Side 1 and Pin 11 and Pin 19) on Side 2). Large diameter vias should be implemented from the pad to the ground planes and power planes to increase thermal conductivity and to reduce inductance. Multiple vias in the thermal pads can significantly reduce temperatures inside the chip. The dimensions of the expanded pads are left to the discretion of the designer and the available board space. Rev. 0 | Page 29 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 PROPAGATION DELAY-RELATED PARAMETERS Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component (see Figure 52). The propagation delay to a logic low output may differ from the propagation delay to a logic high output. INPUT (VIx) 50% OUTPUT (VOx) tPHL 10991-052 tPLH 50% Figure 52. Propagation Delay Parameters Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately the input signal timing is preserved. The 3.3 V operating condition of the ADuM447x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude of >1.0 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (−dβ/dt)∑πrn2; n = 1, 2, … , N where: β is magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM447x and an imposed requirement that the induced voltage be, at most, 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 53. 100 DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 µs, periodic sets of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than approximately 5 µs, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 17) by the watchdog timer circuit. This situation should occur in the ADuM447x devices only during power-up and power-down operations. 1 0.1 0.01 Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM447x component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM447x components operating under the same conditions. 10 0.001 1k 1M 10k 10M 100k MAGNETIC FIELD FREQUENCY (Hz) 100M 10991-053 The ADuM447x consist of two internal die attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, the die are treated as a thermal unit, with the highest junction temperature reflected in the θJA from Table 5. The value of θJA is based on measurements taken with the parts mounted on a JEDEC standard, 4-layer board with fine width traces and still air. Under normal operating conditions, the ADuM447x operate at a full load across the full temperature range without derating the output current. However, following the recommendations in the Printed Circuit Board (PCB) Layout section decreases thermal resistance to the PCB, allowing increased thermal margins in high ambient temperatures. The ADuM447x has an thermal shutdown circuit that shuts down the dc-todc converter and the outputs of the ADuM447x when a die temperature of about 160°C is reached. When the die cools below about 140°C, the ADuM447x dc-to-dc converter and outputs turn on again. The limitation on the ADuM447x magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this can occur. MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kGauss) THERMAL ANALYSIS Data Sheet Figure 53. Maximum Allowable External Magnetic Flux Density For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V, which is still well above the 0.5 V sensing threshold of the decoder. Rev. 0 | Page 30 of 36 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM447x transformers. Figure 54 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown in Figure 54, the ADuM447x are extremely immune and can be affected only by extremely large currents operated at a high frequency that is very close to the component. For the 1 MHz example, a 0.5 kA current needs to be placed 5 mm away from the ADuM447x to affect component operation. The following relationship allows the total IDD1 current to be 1k MAXIMUM ALLOWABLE CURRENT (kA) Dynamic I/O current is consumed only when operating a channel at speeds higher than the refresh rate of fr. The dynamic current of each channel is determined by its data rate. Figure 24 and Figure 28 show the current for a channel in the forward direction, meaning that the input is on the VDDA and VDD2 side of the part. Figure 25 and Figure 29 show the current for a channel in the reverse direction, meaning that the input is on the VISO side of the part. Figure 24, Figure 25, Figure 28, or Figure 29 assume a typical 15 pF output load. IDD1 = (IISO × VISO)/(E × VDD1) + Σ ICHn; n = 1 to 4 DISTANCE = 1m 100 where: IDD1 is the total supply input current. IISO is the current drawn by the secondary side external load. E is the power supply efficiency at the given output load from Figure 17 or Figure 23 at the VISO, VDDA, and VDD2 condition of interest. ICHn is the current drawn by a single channel determined from Figure 24, Figure 25, Figure 28, or Figure 29, depending on channel direction. 10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1 10k 100k 1M 10M 10991-054 0.01 1k 100M MAGNETIC FIELD FREQUENCY (Hz) Figure 54. Maximum Allowable Current for Various Current-to-ADuM447x Spacings In combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages that are sufficiently large to trigger the thresholds of succeeding circuitry. Take care in the layout of such traces to avoid this possibility. POWER CONSUMPTION The VDDA power supply input provides power to the iCoupler data channels, as well as to the power converter. For this reason, the quiescent currents drawn by the data converter and the primary and secondary I/O channels cannot be determined separately. All of these quiescent power demands have been combined into the IDDA (Q) current, as shown in Figure 55. The total IDD supply current is equal to the sum of the quiescent operating current; the dynamic current, IDDA (D), demanded by the I/O channels; and any external IISO load. IDDA (Q) IDDA (D) The maximum external load can be calculated by subtracting the dynamic output load from the maximum allowable load. IISO (LOAD) = IISO (MAX) − Σ IISO (D)n; n = 1 to 4 IDDP (D) The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional current must be included in the analysis of IDD1 and IISO (LOAD). IISO IISO (D) SECONDARY DATA I/O 4-CHANNEL 10991-055 PRIMARY DATA I/O 4-CHANNEL CONVERTER SECONDARY (6) where: IISO (LOAD) is the current available to supply an external secondary side load. IISO (MAX) is the maximum external secondary side load current available at VISO. IISO (D)n is the dynamic load current drawn from VISO by an output or input channel, as shown for a single supply in Figure 26 or Figure 27 or for a double supply in Figure 30 or Figure 31. FEEDBACK CONVERTER PRIMARY (5) Figure 55. Power Consumption Within the ADuM447x Rev. 0 | Page 31 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 POWER CONSIDERATIONS Soft Start Mode and Current-Limit Protection When the ADuM447x first receives power from VDDA, it is in soft start mode, and the output voltage, VISO, is increased gradually while it is below the start-up threshold. In soft start mode, the width of the PWM signal is increased gradually by the primary converter to limit the peak current during VISO power-up. When the output voltage is larger than the startup threshold, the PWM signal can be transferred from the secondary controller to the primary converter, and the dc-todc converter switches from soft start mode to the normal PWM control mode. If a short circuit occurs, the push-pull converter shuts down for about 2 ms and then enters soft start mode. If, at the end of soft start, a short circuit still exists, the process is repeated, which is called hiccup mode. If the short circuit is cleared, the ADuM447x enters normal operation. The ADuM447x also have a pulse-by-pulse current limit, which is active in startup and normal operation and protects the primary switches, X1 and X2, from exceeding approximately 1.2 A peak. This current limit also protects the transformer windings. Data Channel Power Cycle The ADuM447x data input channels on the primary side and the data input channels on the secondary side are protected from premature operation by UVLO circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive, and all input channel drivers and refresh circuits are idle. Outputs are held in a low state. This is to prevent transmission of undefined states during power-up and power-down operations. Data Sheet The primary side input channels sample the input and send a pulse to the inactive secondary output. The secondary side converter begins to accept power from the primary, and the VISO voltage starts to rise. When the secondary side UVLO is reached, the secondary side outputs are initialized to their default low state until data, either a transition or a dc refresh pulse, is received from the corresponding primary side input. It can take up to 1 µs after the secondary side is initialized for the state of the output to correlate with the primary side input. Secondary side inputs sample their state and transmit it to the primary side. Outputs are valid one propagation delay after the secondary side becomes active. Because the rate of charge of the secondary side is dependent on the soft start cycle, loading conditions, input voltage, and output voltage level selected, take care in the design to allow the converter to stabilize before valid data is required. When power is removed from VDDA, the primary side converter and coupler shut down when the UVLO level is reached. The secondary side stops receiving power and starts to discharge. The outputs on the secondary side hold the last state that they received from the primary until either the UVLO level is reached and the outputs are placed in their default low state, or the outputs detect a lack of activity from the inputs and the outputs are set to their default value before the secondary power reaches UVLO. During the application of power to VDDA, the primary side circuitry is held idle until the UVLO preset voltage is reached. At that time, the data channels are initialized to their default low output state until they receive data pulses from the secondary side. Rev. 0 | Page 32 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 The insulation lifetime of the ADuM447x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates, depending on whether the waveform is dc, bipolar ac, or unipolar ac. Figure 56, Figure 57, and Figure 58 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. A 50-year operating lifetime under the bipolar ac condition determines the Analog Devices recommended maximum working voltage. In the case of dc or unipolar ac voltage, the stress on the insulation is significantly lower. This allows operation at higher working Rev. 0 | Page 33 of 36 RATED PEAK VOLTAGE 0V Figure 56. Bipolar AC Waveform RATED PEAK VOLTAGE 0V Figure 57. DC Waveform RATED PEAK VOLTAGE 0V NOTES 1. THE VOLTAGE IS SHOWN SINUSOIDAL FOR ILLUSTRATION PURPOSES ONLY. IT IS MEANT TO REPRESENT ANY VOLTAGE WAVEFORM VARYING BETWEEN 0 AND SOME LIMITING VALUE. THE LIMITING VALUE CAN BE POSITIVE OR NEGATIVE, BUT THE VOLTAGE CANNOT CROSS 0V. Figure 58. Unipolar AC Waveform 10991-058 All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. Analog Devices, Inc., conducts an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM447x. Accelerated life testing is performed using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined, allowing calculation of the time to failure at the working voltage of interest. The values shown in Table 11 summarize the peak voltages for 50 years of service life in several operating conditions. In many cases, the working voltage approved by agency testing is higher than the 50-year service life voltage. Operation at working voltages that are higher than the service life voltage listed leads to premature insulation failure. voltages while still achieving a 50-year service life. The working voltages listed in Table 11 can be applied while maintaining the 50-year minimum lifetime, provided that the voltage conforms to either the dc or unipolar ac voltage cases. Treat any crossinsulation voltage waveform that does not conform to Figure 57 or Figure 58 as a bipolar ac waveform, and limit its peak voltage to the 50-year lifetime voltage value listed in Table 11. 10991-056 INSULATION LIFETIME 10991-057 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 Data Sheet OUTLINE DIMENSIONS 15.40 15.30 15.20 1.93 REF 20 11 7.60 7.50 7.40 10.51 10.31 10.11 10 PIN 1 MARK 2.64 2.54 2.44 2.44 2.24 0.30 0.20 0.10 COPLANARITY 0.1 0.71 0.50 0.31 0.25 BSC GAGE PLANE 45° SEATING PLANE 1.27 BSC 1.01 0.76 0.51 0.46 0.36 0.32 0.23 8° 0° COMPLIANT TO JEDEC STANDARDS MS-013 11-15-2011-A 1 Figure 59. 20-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-20-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADuM4470ARIZ ADuM4470ARIZ-RL ADuM4470CRIZ ADuM4470CRIZ-RL ADuM4471ARIZ ADuM4471ARIZ-RL ADuM4471CRIZ ADuM4471CRIZ-RL ADuM4472ARIZ ADuM4472ARIZ-RL ADuM4472CRIZ ADuM4472CRIZ-RL ADuM4473ARIZ ADuM4473ARIZ-RL ADuM4473CRIZ ADuM4473CRIZ-RL ADuM4474ARIZ ADuM4474ARIZ-RL ADuM4474CRIZ ADuM4474CRIZ-RL 1 Number of Inputs, VDD1 Side 4 4 4 4 3 3 3 3 2 2 2 2 1 1 1 1 0 0 0 0 Number of Inputs, VISO Side 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 Maximum Data Rate (Mbps) 1 1 25 25 1 1 25 25 1 1 25 25 1 1 25 25 1 1 25 25 Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel 20-Lead SOIC_IC Wide Body 20-Lead SOIC_IC Wide Body 13” Tape and Reel Z = RoHS Compliant Part. Rev. 0 | Page 34 of 36 Package Option RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 RI-20-1 Ordering Quantity 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 1,000 Data Sheet ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 NOTES Rev. 0 | Page 35 of 36 ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474 NOTES ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10991-0-12/12(0) Rev. 0 | Page 36 of 36 Data Sheet