Vishay IRFS11N50APBF Power mosfet Datasheet

IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Power MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
• Low Gate Charge Qg results in Simple Drive
Requirement
500
RDS(on) (Ω)
VGS = 10 V
0.52
Qg (Max.) (nC)
52
Qgs (nC)
13
Qgd (nC)
18
Configuration
Available
• Improved Gate, Avalanche and Dynamic dV/dt RoHS*
COMPLIANT
Ruggedness
• Fully
Characterized
Capacitance
Avalanche Voltage and Current
Single
and
• Effective Coss Specified
D
• Lead (Pb)-free Available
D2PAK (TO-263)
APPLICATIONS
• Switch Mode Power Supply (SMPS)
G
• Uninterruptible Power Supply
• High Speed Power Switching
G D
TYPICAL SMPS TOPOLOGIES
S
S
• Two Transistor Forward
N-Channel MOSFET
• Half and Full Bridge
• Power Factor Correction Boost
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
D2PAK (TO-263)
D2PAK (TO-263)
D2PAK (TO-263)
IRFS11N50APbF
IRFS11N50ATRRPbFa
IRFS11N50ATRLPbFa
SiHFS11N50A-E3
SiHFS11N50ATR-E3a
SiHFS11N50ATL-E3a
IRFS11N50A
-
IRFS11N50ATRLa
SiHFS11N50A
-
SiHFS11N50ATLa
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
Gate-Source Voltage
VGS
Continuous Drain Current
VGS at 10 V
Pulsed Drain Currenta
Linear Derating Factor
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
Maximum Power Dissipation
Peak Diode Recovery dV/dtc
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
TC = 25 °C
TC = 100 °C
ID
IDM
TC = 25 °C
EAS
IAR
EAR
PD
dV/dt
TJ, Tstg
for 10 s
LIMIT
± 30
11
7.0
44
1.3
275
11
17
170
6.9
- 55 to + 150
300d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 19 mH, RG = 25 Ω, IAS = 5.5 A (see fig. 12).
c. ISD ≤ 5.5 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91286
S-Pending-Rev. A, 22-Jul-08
WORK-IN-PROGRESS
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IRFS11N50A, SiHFS11N50A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum Junction-to-Case (Drain)
RthJC
-
0.75
Case-to-Sink, Flat, Greased Surface
RthCS
0.50
-
Maximum Junction-to-Ambient
RthJA
-
62
UNIT
°C/W
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
Zero Gate Voltage Drain Current
Drain-Source On-State Resistance
Forward Transconductance
VDS
VGS = 0 V, ID = 250 µA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.060
-
V/°C
VGS(th)
VDS = VGS, ID = 250 µA
2.0
-
4.0
V
nA
IGSS
IDSS
RDS(on)
gfs
VGS = ± 30 V
-
-
± 100
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
-
-
0.52
Ω
VDS = 50 V, ID = 6.6 A
6.1
-
-
S
ID = 6.6 Ab
VGS = 10 V
µA
Dynamic
Input Capacitance
Ciss
VGS = 0 V,
-
1423
-
Output Capacitance
Coss
VDS = 25 V,
-
208
-
Reverse Transfer Capacitance
Crss
f = 1.0 MHz, see fig. 5
-
8.1
-
Output Capacitance
Coss
VDS = 1.0 V, f = 1.0 MHz
-
2000
-
VDS = 400 V, f = 1.0 MHz
-
55
-
-
97
-
-
-
52
-
-
13
-
-
18
-
14
-
-
35
-
-
32
-
-
28
-
-
-
11
S
-
-
44
Vb
-
-
1.5
V
-
510
770
ns
-
3.4
5.1
µC
Effective Output Capacitance
Coss eff.
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Qgd
Turn-On Delay Time
td(on)
Rise Time
Turn-Off Delay Time
Fall Time
VGS = 0 V
tr
td(off)
tf
VDS = 0 V to 400
VGS = 10 V
Vc
ID = 11 A, VDS = 400 V
see fig. 6 and 13b
VDD = 250 V, ID = 11 A
RG = 9.1 Ω, RD = 22 Ω,
see fig. 10b
pF
nC
ns
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
TJ = 25 °C, IS = 11 A, VGS = 0
TJ = 25 °C, IF = 11 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising fom 0 to 80 % VDS.
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Document Number: 91286
S-Pending-Rev. A, 22-Jul-08
IRFS11N50A, SiHFS11N50A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
Fig. 1 - Typical Output Characteristics
Fig. 2 - Typical Output Characteristics
Document Number: 91286
S-Pending-Rev. A, 22-Jul-08
Fig. 3 - Typical Transfer Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
Document Number: 91286
S-Pending-Rev. A, 22-Jul-08
IRFS11N50A, SiHFS11N50A
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+
- VDD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
10 %
VGS
td(on)
Fig. 9 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T.
RG
IAS
20 V
tp
Driver
+
A
- VDD
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
Document Number: 91286
S-Pending-Rev. A, 22-Jul-08
IAS
Fig. 12b - Unclamped Inductive Waveforms
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IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 12d - Typical Drain-to-Source Voltage
vs. Avalanche Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
+
QGS
QGD
D.U.T.
-
VDS
VGS
VG
3 mA
Charge
Fig. 13a - Basic Gate Charge Waveform
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IG
ID
Current sampling resistors
Fig. 13b - Gate Charge Test Circuit
Document Number: 91286
S-Pending-Rev. A, 22-Jul-08
IRFS11N50A, SiHFS11N50A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
D.U.T
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
•
•
•
•
RG
dV/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by duty factor "D"
D.U.T. - device under test
Driver gate drive
P.W.
+
Period
D=
+
-
VDD
P.W.
Period
VGS = 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Body diode
VDD
forward drop
Inductor current
Ripple ≤ 5 %
ISD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91286.
Document Number: 91286
S-Pending-Rev. A, 22-Jul-08
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Vishay
Disclaimer
All product specifications and data are subject to change without notice.
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Document Number: 91000
Revision: 18-Jul-08
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