Cypress CY7C199D-10VXI 256k (32k x 8) static ram Datasheet

CY7C199D
256K (32K x 8) Static RAM
Functional Description [1]
Features
• Pin- and function-compatible with CY7C199C
The CY7C199D is a high-performance CMOS static RAM
organized as 32,768 words by 8 bits. Easy memory expansion
is provided by an active LOW Chip Enable (CE), an active
LOW Output Enable (OE) and tri-state drivers. This device has
an automatic power-down feature, reducing the power
consumption when deselected. The input and output pins (IO0
through IO7) are placed in a high-impedance state when:
• High speed
— tAA = 10 ns
• Low active power
— ICC = 80 mA @ 10 ns
• Low CMOS standby power
• Deselected (CE HIGH)
— ISB2 = 3 mA
• Outputs are disabled (OE HIGH)
• 2.0V Data Retention
• When the write operation is active(CE LOW and WE LOW)
• Automatic power-down when deselected
Write to the device by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight IO pins (IO0
through IO7) is then written into the location specified on the
address pins (A0 through A14).
• CMOS for optimum speed/power
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Pb-free 28-pin 300-Mil wide Molded SOJ and
28-pin TSOP I packages
Read from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins appears on the IO pins.
Logic Block Diagram
IO0
INPUT BUFFER
IO1
IO2
SENSE AMPS
ROW DECODER
32K x 8
ARRAY
IO3
IO4
IO5
IO6
CE
IO7
POWER
DOWN
A14
A13
A10
OE
A12
COLUMN DECODER
WE
A11
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05471 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 01, 2007
[+] Feedback
CY7C199D
Pin Configurations
SOJ
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
IO 0
IO 1
IO 2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
IO 7
IO 6
IO 5
IO 4
IO 3
OE
A1
A2
A3
A4
WE
V CC
A5
A6
A7
A8
A9
A 10
A 11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
TSOP I
Top View
(not to scale)
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A0
CE
IO 7
IO 6
IO 5
IO 4
IO 3
GND
IO 2
IO 1
IO 0
A 14
A 13
A 12
Selection Guide
CY7C199D-10
Unit
Maximum Access Time
10
ns
Maximum Operating Current
80
mA
Maximum CMOS Standby Current
3
mA
Document #: 38-05471 Rev. *D
Page 2 of 10
[+] Feedback
CY7C199D
Maximum Ratings
DC Input Voltage [2] ............................... –0.5V to VCC + 0.5V
Exceeding the maximum ratings may impair the useful life of
the device. These user guidelines are not tested.
Output Current into Outputs (LOW)............................. 20 mA
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC to Relative GND [2] ... –0.5V to +6.0V
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ................................................... > 200 mA
Operating Range
DC Voltage Applied to Outputs
in High-Z State [2] ...................................–0.5V to VCC + 0.5V
Range
Ambient
Temperature
VCC
Speed
Industrial
–40°C to +85°C
5V ± 0.5V
10 ns
Electrical Characteristics (Over the Operating Range)
7C199D-10
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
IOH=–4.0 mA
VOL
Output LOW Voltage
IOL=8.0 mA
Min
Max
2.4
[2]
Unit
V
0.4
V
2.0
VCC + 0.5
V
–0.5
0.8
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage [2]
IIX
Input Leakage Current
GND < VI < VCC
–1
+1
µA
IOZ
Output Leakage Current
GND < VO < VCC, Output Disabled
–1
+1
µA
ICC
VCC Operating Supply Current
VCC = Max,
IOUT = 0 mA,
f = fmax = 1/tRC
100 MHz
80
mA
83 MHz
72
mA
66 MHz
58
mA
40 MHz
37
mA
ISB1
Automatic CE
Power-down Current— TTL Inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fmax
10
mA
ISB2
Automatic CE
Power-down Current— CMOS Inputs
Max VCC, CE > VCC – 0.3V
VIN > VCC – 0.3V or VIN < 0.3V, f = 0
3
mA
Note:
2. VIL(min) = –2.0V and VIH(max) = VCC + 1V for pulse durations of less than 5 ns.
Document #: 38-05471 Rev. *D
Page 3 of 10
[+] Feedback
CY7C199D
Capacitance [3]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz, VCC = 5.0V
Max
Unit
8
pF
8
pF
Thermal Resistance [3]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Test Conditions
Still Air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
SOJ
TSOP I
Unit
59.16
54.65
°C/W
40.84
21.49
°C/W
AC Test Loads and Waveforms [4]
Z = 50Ω
ALL INPUT PULSES
OUTPUT
3.0V
50 Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
30pF*
GND
10%
90%
10%
90%
1.5V
Rise Time: ≤ 3 ns
(a)
High-Z characteristics:
(b)
Fall Time: ≤ 3 ns
R1 480Ω
5V
OUTPUT
R2
255Ω
5 pF
INCLUDING
JIG AND SCOPE
(c)
Notes:
3. Tested initially and after any design or process changes that may affect these parameters.
4. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
Document #: 38-05471 Rev. *D
Page 4 of 10
[+] Feedback
CY7C199D
Switching Characteristics (Over the Operating Range) [5]
7C199D-10
Parameter
Description
Min
Max
Unit
Read Cycle
tpower [6]
VCC(typical) to the first access
100
µs
tRC
Read Cycle Time
10
ns
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
10
ns
OE LOW to Data Valid
5
ns
tDOE
tLZOE
[7]
OE LOW to Low-Z
tHZOE
[7, 8]
OE HIGH to High-Z
[7]
CE LOW to Low-Z
tLZCE
tHZCE [7, 8]
tPU
[9]
tPD
[9]
10
3
CE LOW to Power-up
ns
5
3
ns
ns
5
0
CE HIGH to Power-down
Write Cycle
ns
0
CE HIGH to High-Z
ns
ns
ns
10
ns
[10, 11]
tWC
Write Cycle Time
10
ns
tSCE
CE LOW to Write End
7
ns
tAW
Address Set-up to Write End
7
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-up to Write Start
0
ns
tPWE
WE Pulse Width
7
ns
tSD
Data Set-up to Write End
5
ns
tHD
Data Hold from Write End
0
ns
tHZWE [7]
tLZWE
[7, 8]
WE LOW to High-Z
WE HIGH to Low-Z
6
3
ns
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less for all speeds, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of
the specified IOL/IOH and 30-pF load capacitance.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of “AC Test Loads and Waveforms [4]” on page 4. Transition is measured ±200 mV from steady-state voltage.
9. This parameter is guaranteed by design and is not tested.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a
write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD .
Document #: 38-05471 Rev. *D
Page 5 of 10
[+] Feedback
CY7C199D
Data Retention Characteristics (Over the Operating Range)
Parameter
VDR
Conditions
VCC for Data Retention
[3]
Min
Operation Recovery Time
Unit
V
3
Chip Deselect to Data Retention Time
tR [12]
Max
2.0
VCC = VDR = 2.0V, CE > VCC – 0.3V,
VIN > VCC – 0.3V or VIN < 0.3V
Data Retention Current
ICCDR
tCDR
Description
mA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
4.5V
4.5V
VDR > 2V
tR
tCDR
CE
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [13, 14]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled) [14, 15]
tRC
CE
tACE
OE
DATA OUT
tDOE
tLZOE
HIGH IMPEDANCE
tHZOE
tHZCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
HIGH
IMPEDANCE
tPD
tPU
ICC
50%
50%
ISB
Notes:
12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 50 µs or stable at VCC(min) > 50 µs.
13. Device is continuously selected. OE, CE = VIL.
14. WE is HIGH for read cycle.
15. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05471 Rev. *D
Page 6 of 10
[+] Feedback
CY7C199D
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled) [10, 16, 17]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA IO
tHD
DATA IN VALID
Write Cycle No. 2 (WE Controlled) [10, 16, 17]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA IO
NOTE 18
tHD
DATAIN VALID
tHZOE
Write Cycle No. 3 (WE Controlled, OE LOW) [11, 17]
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tSD
DATA IO
NOTE 18
tHD
DATAIN VALID
tHZWE
tLZWE
Notes:
16. Data IO is high impedance if OE = VIH.
17. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
18. During this period the IOs are in the output state and input signals should not be applied.
Document #: 38-05471 Rev. *D
Page 7 of 10
[+] Feedback
CY7C199D
Truth Table
CE
WE
OE
H
X
X
High Z
Inputs/Outputs
Deselect/Power-down
Mode
Standby (ISB)
Power
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Deselect, Output disabled
Active (ICC)
Ordering Information
Speed
(ns)
10
Package
Diagram
Ordering Code
Operating
Range
Package Type
CY7C199D-10VXI
51-85031
28-pin (300-Mil) Molded SOJ (Pb-Free)
CY7C199D-10ZXI
51-85071
28-pin TSOP Type I (Pb-free)
Industrial
Please contact your local Cypress sales representative for availability of these parts.
Package Diagrams
Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
MAX.
3. DIMENSIONS IN INCHES
DETAIL
A
EXTERNAL LEAD DESIGN
PIN 1 ID
14
1
0.291
0.300
15
0.330
0.350
28
OPTION 1
0.697
0.713
A
Document #: 38-05471 Rev. *D
0.014
0.020
OPTION 2
SEATING PLANE
0.120
0.140
0.050
TYP.
0.026
0.032
0.013
0.019
0.007
0.013
0.004
0.025 MIN.
0.262
0.272
51-85031-*C
Page 8 of 10
[+] Feedback
CY7C199D
Package Diagrams (continued)
Figure 2. 28-pin Thin Small Outline Package Type 1 (8x13.4 mm), 51-85071
51-85071-*G
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05471 Rev. *D
Page 9 of 10
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the
use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to
be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback
CY7C199D
Document History Page
Document Title: CY7C199D, 256K (32K x 8) Static RAM
Document Number: 38-05471
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
201560
See ECN
SWI
Advance Information data sheet for C9 IPP
*A
233728
See ECN
RKF
DC parameters modified as per EROS (Spec # 01-02165)
Pb-free Offering in Ordering Information
*B
262950
See ECN
RKF
Removed 28-LCC Pinout and Package Diagrams
Added Data Retention Characteristics table
Added Tpower Spec in Switching Characteristics table
Shaded Ordering Information
*C
307594
See ECN
RKF
Reduced Speed bins to -10, -12 and -15 ns
*D
820660
See ECN
VKN
Converted from Preliminary to Final
Removed 12 ns and 15 ns speed bin
Removed Commercial Operating range
Removed “L” part
Removed 28-pin PDIP and 28-pin SOIC package
Changed Overshoot spec from VCC+2V to VCC+1V in footnote #2
Changed ICC spec from 60 mA to 80 mA for 100 MHz speed bin
Added ICC specs for 83 MHz, 66 MHz and 40 MHz speed bins
Updated Thermal Resistance table
Updated Ordering Information Table
Document #: 38-05471 Rev. *D
Page 10 of 10
[+] Feedback
Similar pages