ON MMSF2P02E Power mosfet Datasheet

MMSF2P02E
Preferred Device
Power MOSFET
2 Amps, 20 Volts
P−Channel SO−8
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a low reverse recovery time. MiniMOSt
devices are designed for use in low voltage, high speed switching
applications where power efficiency is important. Typical applications
are dc−dc converters, and power management in portable and battery
powered products such as computers, printers, cellular and cordless
phones. They can also be used for low voltage motor controls in mass
storage products such as disk drives and tape drives. The avalanche
energy is specified to eliminate the guesswork in designs where
inductive loads are switched and offer additional safety margin against
unexpected voltage transients.
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery
Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO−8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed
• Avalanche Energy Specified
• Mounting Information for SO−8 Package Provided
• IDSS Specified at Elevated Temperature
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
20
Vdc
Gate−to−Source Voltage − Continuous
VGS
± 20
Vdc
Drain Current
− Continuous @ TA = 25°C (Note 2.)
− Continuous @ TA = 100°C
− Single Pulse (tp ≤ 10 μs)
ID
ID
Adc
IDM
2.5
1.7
13
PD
2.5
Watts
TJ, Tstg
− 55 to
150
°C
216
mJ
Total Power Dissipation @ TA = 25°C
(Note 2.)
Operating and Storage Temperature Range
EAS
Thermal Resistance − Junction to Ambient
(Note 2.)
RθJA
50
°C/W
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 seconds
TL
260
°C
G
S
MARKING
DIAGRAM
SO−8
CASE 751
STYLE 13
S4P01
LYWW
1
L
Y
WW
= Location Code
= Year
= Work Week
PIN ASSIGNMENT
N−C
1
8
Drain
Source
2
7
Drain
Source
3
6
Drain
Gate
4
5
Drain
Top View
1. Negative sign for P−Channel device omitted for clarity.
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided),
10 sec. max.
August, 2006 − Rev. 6
P−Channel
D
Apk
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 20 Vdc, VGS = 5.0 Vdc,
IL = 6.0 Apk, L = 12 mH, RG = 25 Ω)
© Semiconductor Components Industries, LLC, 2006
2 AMPERES
20 VOLTS
RDS(on) = 250 mW
8
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1.)
Rating
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1
ORDERING INFORMATION
Device
Package
MMSF2P02ER2
SO−8
Shipping
2500 Tape & Reel
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MMSF2P02E/D
MMSF2P02E
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) (Note 3.)
Characteristic
Symbol
Min
Typ
Max
Unit
20
−
−
24.7
−
−
−
−
−
−
1.0
10
−
−
100
1.0
2.0
4.7
3.0
−
−
−
0.19
0.3
0.25
0.4
gFS
1.0
2.8
−
Mhos
Ciss
−
340
475
pF
Coss
−
220
300
Crss
−
75
150
td(on)
−
20
40
tr
−
40
80
td(off)
−
53
106
tf
−
41
82
td(on)
−
13
26
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 μAdc)
Temperature Coefficient (Positive)
V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C)
IDSS
Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0)
IGSS
Vdc
mV/°C
μAdc
nAdc
ON CHARACTERISTICS (Note 4.)
Gate Threshold Voltage
(VDS = VGS, ID = 250 μAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance
(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)
RDS(on)
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc)
Vdc
mV/°C
Ohm
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 5.)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 5.0 Vdc,
RG = 6.0 Ω)
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 6.0 Ω)
Fall Time
Gate Charge
(VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
ns
ns
tr
−
29
58
td(off)
−
30
60
tf
−
28
56
QT
−
10
15
Q1
−
1.1
−
Q2
−
3.3
−
Q3
−
2.5
−
VSD
−
1.5
2.0
Vdc
trr
−
34
64
ns
ta
−
18
−
tb
−
16
−
QRR
−
0.035
−
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 4.)
(IS = 2.0 Adc, VGS = 0 Vdc)
Reverse Recovery Time
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/μs)
Reverse Recovery Stored Charge
3. Negative sign for P−Channel device omitted for clarity.
4. Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2%.
5. Switching characteristics are independent of operating junction temperature.
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2
μC
MMSF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4
4.1 V
3.9 V
1
3.7 V
3.5 V
3.3 V
0
0.4
0.8
1.2
1.6
100°C
2
25°C
TJ = −55°C
1
3
3.5
4
4.5
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.6
ID = 1 A
TJ = 25°C
0.5
0.4
0.3
0.2
0.1
0
3
3
0
2.5
2
4
7
6
5
8
10
9
0.6
TJ = 25°C
0.5
0.4
VGS = 4.5
0.3
0.2
10 V
0.1
0
0.5
1
1.5
2
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
2.0
100
VGS = 10 V
ID = 2 A
VGS = 0 V
1.5
I DSS , LEAKAGE (nA)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
I D , DRAIN CURRENT (AMPS)
4.3 V
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
I D , DRAIN CURRENT (AMPS)
3
2
VDS ≥ 10 V
TJ = 25°C
4.7 V
4.5 V
0
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)
4
5V
VGS = 10 7 V
1.0
0.5
0
−50
−25
0
25
50
75
100
125
TJ = 125°C
10
100°C
1
150
0
4
8
12
16
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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20
MMSF2P02E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
VDS = 0 V
12
TJ = 25°C
Ciss
800
C, CAPACITANCE (pF)
VGS = 0 V
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
1000
600
Crss
400
Ciss
Coss
200
Crss
0
10
5
0
VGS
5
10
15
20
25
QT
9
12
VGS
VDS
6
3
4
Q3
0
ID = 2 A
TJ = 25°C
2
VDS
8
Q2
Q1
0
30
16
4
6
8
Qg, TOTAL GATE CHARGE (nC)
10
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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0
12
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
MMSF2P02E
100
2
VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25°C
IS, SOURCE CURRENT (AMPS)
t, TIME (ns)
TJ = 25°C
VGS = 0 V
td(off)
tr
tf
td(on)
10
1
10
RG, GATE RESISTANCE (OHMS)
1.6
1.2
0.8
0.4
0
0.6
100
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
di/dt = 300 A/μs
1.6
Figure 10. Diode Forward Voltage
versus Current
100
I D , DRAIN CURRENT (AMPS)
Standard Cell Density
trr
High Cell Density
trr
tb
ta
I S , SOURCE CURRENT
0.8
1
1.2
1.4
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
10
VGS = 20 V
SINGLE PULSE
TC = 25°C
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided), 10s max.
1 ms
10 ms
1
dc
0.1
0.01
0.1
t, TIME
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 11. Reverse Recovery Time (trr)
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100
MMSF2P02E
EAS, SINGLE PULSE DRAIN−TO−SOURCE
AVALANCHE ENERGY (mJ)
250
ID = 6 A
200
150
100
50
0
25
50
75
100
150
125
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
10
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
Normalized to θja at 10s.
Chip
0.0022 Ω
0.0210 Ω
0.2587 Ω
0.0020 F
0.0207 F
0.3517 F
0.7023 Ω
0.6863 Ω
0.01
0.01
3.1413 F
108.44 F
SINGLE PULSE
0.001
1.0E−05
1.0E−04
1.0E−03
1.0E−02
1.0E−01
t, TIME (s)
1.0E+00
Figure 14. Thermal Response
di/dt
IS
trr
ta
tb
TIME
0.25 IS
tp
IS
Figure 15. Diode Reverse Recovery Waveform
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1.0E+01
1.0E+02
Ambient
1.0E+03
MMSF2P02E
INFORMATION FOR USING THE SO−8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must
be the correct size to ensure proper solder connection
interface between the board and the package. With the
correct pad geometry, the packages will self−align when
subjected to a solder reflow process.
0.060
1.52
0.275
7.0
0.155
4.0
0.024
0.6
0.050
1.270
inches
mm
SO−8 POWER DISSIPATION
into the equation for an ambient temperature TA of 25°C,
one can calculate the power dissipation of the device which
in this case is 2.5 Watts.
The power dissipation of the SO−8 is a function of the
input pad size. This can vary from the minimum pad size
for soldering to the pad size given for maximum power
dissipation. Power dissipation for a surface mount device is
determined by TJ(max), the maximum rated junction
temperature of the die, RθJA, the thermal resistance from
the device junction to ambient; and the operating
temperature, TA. Using the values provided on the data
sheet for the SO−8 package, PD can be calculated as
follows:
PD =
PD =
150°C − 25°C
50°C/W
= 2.5 Watts
The 50°C/W for the SO−8 package assumes the
recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.5 Watts using the
footprint shown. Another alternative would be to use a
ceramic substrate or an aluminum core board such as
Thermal Cladt. Using board material such as Thermal
Clad, the power dissipation can be doubled using the same
footprint.
TJ(max) − TA
RθJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values
SOLDERING PRECAUTIONS
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the
maximum temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should
be allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and
result in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied
during cooling.
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within
a short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and
soldering should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering
method, the difference shall be a maximum of 10°C.
* * Soldering a device without preheating can cause
excessive thermal shock and stress which can result in
damage to the device.
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MMSF2P02E
TYPICAL SOLDER HEATING PROFILE
temperature versus time. The line on the graph shows the
actual temperature that might be experienced on the surface
of a test board at or near a central solder joint. The two
profiles are based on a high density and a low density
board. The Vitronics SMD310 convection/infrared reflow
soldering system was used to generate this profile. The type
of solder used was 62/36/2 Tin Lead Silver with a melting
point between 177 −189°C. When this type of furnace is
used for solder reflow work, the circuit boards and solder
joints tend to heat first. The components on the board are
then heated by conduction. The circuit board, because it has
a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may
be up to 30 degrees cooler than the adjacent solder joints.
For any given circuit board, there will be a group of
control settings that will give the desired heat pattern. The
operator must set temperatures for several heating zones
and a figure for belt speed. Taken together, these control
settings make up a heating “profile” for that particular
circuit board. On machines controlled by a computer, the
computer remembers these profiles from one operating
session to the next. Figure 13 shows a typical heating
profile for use when soldering a surface mount device to a
printed circuit board. This profile will vary among
soldering systems, but it is a good starting point. Factors
that can affect the profile include the type of soldering
system in use, density and types of components on the
board, type of solder used, and the type of board or
substrate material being used. This profile shows
STEP 1
PREHEAT
ZONE 1
“RAMP”
200°C
STEP 2
STEP 3
VENT
HEATING
“SOAK” ZONES 2 & 5
“RAMP”
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
160°C
STEP 5
STEP 6
STEP 7
HEATING
VENT
COOLING
ZONES 4 & 7
205° TO 219°C
“SPIKE”
PEAK AT
170°C
SOLDER
JOINT
150°C
150°C
100°C
140°C
100°C
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
5°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
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MMSF2P02E
PACKAGE DIMENSIONS
SO−8
CASE 751−07
ISSUE V
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
A
8
5
S
B
0.25 (0.010)
M
Y
M
1
4
−Y−
K
G
C
N
X 45 _
SEATING
PLANE
−Z−
0.10 (0.004)
H
M
D
0.25 (0.010)
M
Z Y
S
X
J
S
XXXXXX
ALYW
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
STYLE 13:
PIN 1.
2.
3.
4.
5.
6.
7.
8.
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0_
8_
0.010
0.020
0.228
0.244
N.C.
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
MiniMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC).
Thermal Clad is a registered trademark of the Bergquist Company.
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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