Sony CXP87500 Cmos 8-bit single chip microcomputer Datasheet

CXP87500
CMOS 8-bit Single Chip Microcomputer
Description
The CXP87500 is a CMOS 8-bit single chip microcomputer of piggyback/evaluator combined type,
which is developed for evaluating the function of the
CXP87532/87540.
Piggyback/
evaluator type
100 pin PQFP (Ceramic)
Features
• A wide instruction set (213 instructions) which
LQFP supported
QFP supported
covers various types of data
– 16-bit operation/multiplication and division/
boolean bit operation instructions
• Minimum instruction cycle
326ns at 12.288MHz operation
• Applicable EPROM
LCC type 27C512
(Maximum 40Kbytes are available)
• Incorporated RAM capacity
1344bytes
• Peripheral functions
– Arithmetic coprocessor
Signed multiplication and division, signed sum of products.
high speed execution of many bits shift rotation operation
– A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 13µs/12.288MHz)
Incorporated 3-stage FIFO for A/D conversion data
– Serial interface
Incorporated buffer RAM (auto transfer for 1 to 128bytes),
2-channel
– Timer
8-bit timer
8-bit timer/counter
19-bit time base timer
– High precision timing pattern generator
PPG 11-pin, 32-stage programmable
– PWM output
12-bit, 2-channel (repetitive frequency 48kHz)
8-bit, 3-channel (repetitive frequency 48kHz)
– Servo input control
Capstan FG, drum FG/PG, reel FG input
– FRC capture unit
Incorporated 28-bit and 8-stage FIFO
• Interruption
12 factors, 12 vectors, multi-interruption possible
• Standby mode
Sleep/stop
• Package
100-pin ceramic PQFP
Note) Mask option depends on the type of the CXP87500. Refer to the Products List for details.
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E93X12B81-PS
CXP87500
PE5/PWM3
PE4/PWM2
PE3/PWM1
PE2/PWM0
PE1/EC/INT2
PE0/INT0
NMI
VDD
Vss
NC
PA7/ATFS2
PA6/AREA
PA5/ATFS3
PA4/ATFS1
PA3/PROUT
PA2/PPO10
PA1/PPO9
PA0/PPO8
PB7/PPO7
PB6/PPO6
Pin Assignment in Piggyback Mode (QFP package)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
78
PK0/RFDT
PB2/PPO2
4
77
PK1/MCLK
PB1/PPO1
5
76
PK2
PB0/PPO0
6
75
PK3
PC7
7
74
PG0/EXI0
PC6
8
73
PG1/EXI1
PC5
9
72
PG2/DREF
PC4
10
71
PG3/DPG
PC3
11
PC2
12
PC1
13
PC0
14
PD7
15
PD6
16
PD5
17
4
A6
3
2
A13
PE7/SWP
3
A14
79
PB3/PPO3
VDD
PB4/PPO4
NC
PE6/PWM4
A15
80
2
A12
1
A7
PB5/PPO5
1 32 31 30
29
5
A8
A5
6
28
A9
A4
7
27
A11
A3
8
26
NC
A2
9
25
OE
A0
A10
24
10
A1
CE
23
11
70
PG4/DFG
69
PG5/CFG
68
PG6/RFG0
67
PG7/RFG1
66
PF0/AN0
65
PF1/AN1
64
PF2/AN2
63
PF3/AN3
62
PF4/AN4
61
PF5/AN5
PD4
18
PD3
19
PD2
20
PD1
21
60
PF6/AN6
PD0
22
59
PF7/AN7
58
AVDD
NC
D0
D7
22
12
13
D6
21
D5
D4
D3
NC
GND
D2
D1
14 15 16 17 18 19 20
PI7
23
PI6
24
57
AVREF
PI5
25
56
AVss
PI4
26
55
SCK0
PI3
27
54
SO0
PI2
28
53
SI0
PI1
29
52
CS0
PI0
30
51
PH0/SCK1
PH1/SO1
PH2/SI1
PH4
PH3/CS1/INT1
PH5
PH6
PH7
XTAL
EXTAL
Vss
RST
MP
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 90) is always connected to VDD.
2. VSS (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) is always connected to GND.
–2–
CXP87500
PK0/RFDT
PE6/PWM4
PE7/SWP
PE5/PWM3
PE3/PWM1
PE4/PWM2
PE2/PWM0
PE0/INT0
PE1/EC/INT2
NMI
VDD
VSS
PA7/ATFS2
NC
PA6/AREA
PA4/ATFS1
PA5/ATFS3
PA3/PROUT
PA1/PPO9
PA2/PPO10
PA0/PPO8
PB6/PPO6
PB7/PPO7
PB4/PPO4
PB5/PPO5
Pin Assignment in Piggyback Mode (LQFP package)
AA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PK1/MCLK
74
PK2
73
PK3
72
PG0/EXI0
5
71
PG1/EXI1
PC6
6
70
PG2/DREF
PC5
7
69
PG3/DPG
PC4
8
68
PG4/DFG
PC3
9
67
PG5/CFG
PC2
10
66
PG6/RFG0
PC1
11
PC0
12
PD7
13
PB3/PPO3
1
PB2/PPO2
2
PB1/PPO1
3
PB0/PPO0
4
PC7
PD6
14
PD5
15
PD4
16
PD3
17
PD2
18
PD1
19
PD0
20
PI7
A15
1
28
VDD
A12
2
27
A14
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
OE
A2
8
21
A10
A1
9
20
CE
A0
10
19
D7
D0
11
18
D6
D1
12
17
D5
D2
13
16
D4
GND
14
15
D3
65
PG7/RFG1
64
PF0/AN0
63
PF1/AN1
62
PF2/AN2
61
PF3/AN3
60
PF4/AN4
59
PF5/AN5
58
PF6/AN6
57
PF7/AN7
56
AVDD
21
55
AVREF
PI6
22
54
AVSS
PI5
23
53
SCK0
PI4
24
52
SO0
PI3
25
51
SI0
Note) 1. NC (Pin 88) is always connected to VDD.
2. VSS (Pins 39 and 86) are both connected to GND.
3. MP (Pin 37) is always connected to GND.
–3–
CS0
PH0/SCK1
PH2/SI1
PH1/SO1
PH3/CS1/INT1
PH5
PH4
PH6
PH7
EXTAL
VSS
XTAL
RST
MP
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PI0
PJ7
PI2
PI1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP87500
PE5/PWM3
PE4/PWM2
PE3/PWM1
PE2/PWM0
PE1/EC/INT2
PE0/INT0
NMI
VDD
Vss
NC
PA7/ATFS2
PA6/AREA
PA5/ATFS3
PA4/ATFS1
PA3/PROUT
PA2/PPO10
PA1/PPO9
PA0/PPO8
PB7/PPO7
PB6/PPO6
Pin Assignment in Evaluator Mode (QFP package)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
PK0/RFDT
PB2/PPO2
4
77
PK1/MCLK
PB1/PPO1
5
76
PK2
PB0/PPO0
6
75
PK3
PC7
7
74
PG0/EXI0
PC6
8
73
PG1/EXI1
PC5
9
72
PG2/DREF
PC4
10
71
PG3/DPG
PC3
11
PC2
12
PC1
13
PC0
14
PD7
15
PD6
16
PD5
17
PD4
18
PD3
19
PD2
20
A6/D6
2
3
4
A13
78
A14
3
VDD
PE7/SWP
PB3/PPO3
NC
PE6/PWM4
79
A15
80
2
A12
1
PB4/PPO4
A7/D7
PB5/PPO5
1 32 31 30
29
5
A8
A5/D5
6
28
A9
A4/D4
7
27
A11
A3/D3
26
8
A2/D2
25
9
A1/D1
E/P
22
12
RD
A10
23
11
NC
HALT
24
10
A0/D0
NC
13
I/T
MON
21
14 15 16 17 18 19 20
70
PG4/DFG
69
PG5/CFG
68
PG6/RFG0
67
PG7/RFG1
66
PF0/AN0
65
PF1/AN1
64
PF2/AN2
63
PF3/AN3
62
PF4/AN4
61
PF5/AN5
PF6/AN6
PF7/AN7
24
PI5
RST
PI6
C1
23
C2
PI7
NC
59
GND
22
SYNC
21
PD0
WR
PD1
60
58
AVDD
57
AVREF
25
56
AVss
PI4
26
55
SCK0
PI3
27
54
SO0
PI2
28
53
SI0
PI1
29
52
CS0
PI0
30
51
PH0/SCK1
PH1/SO1
PH2/SI1
PH3/CS1/INT1
PH4
PH5
PH6
PH7
EXTAL
XTAL
Vss
RST
MP
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Note) 1. NC (Pin 90) is always connected to VDD.
2. VSS (Pins 41 and 88) are both connected to GND.
3. MP (Pin 39) is always connected to GND.
–4–
CXP87500
PE7/SWP
PK0/RFDT
PE6/PWM4
PE5/PWM3
PE3/PWM1
PE4/PWM2
PE1/EC/INT2
PE2/PWM0
PE0/INT0
NMI
VSS
NC
VDD
PA6/AREA
PA7/ATFS2
PA5/ATFS3
PA3/PROUT
PA4/ATFS1
PA2/PPO10
PA0/PPO8
PA1/PPO9
PB7/PPO7
PB5/PPO5
PB6/PPO6
PB4/PPO4
Pin Assignment in Evaluator Mode (LQFP package)
AA
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
PK1/MCLK
74
PK2
73
PK3
72
PG0/EXI0
5
71
PG1/EXI1
PC6
6
70
PG2/DREF
PC5
7
69
PG3/DPG
PC4
8
68
PG4/DFG
PC3
9
67
PG5/CFG
PC2
10
66
PG6/RFG0
PC1
11
PC0
12
PD7
13
PB3/PPO3
1
PB2/PPO2
2
PB1/PPO1
3
PB0/PPO0
4
PC7
PD6
14
PD5
15
PD4
16
PD3
17
PD2
18
PD1
19
PD0
20
A15
1
28
VDD
A12
2
27
A14
A7/D7
3
26
A13
A6/D6
4
25
A8
A5/D5
5
24
A9
A4/D4
6
23
A11
A3/D3
7
22
HALT
A2/D2
8
21
A10
A1/D1
9
20
E/P
A0/D0
10
19
I/T
RD
11
18
MON
WR
12
17
RST
SYNC
13
16
C1
GND
14
15
C2
65
PG7/RFG1
64
PF0/AN0
63
PF1/AN1
62
PF2/AN2
61
PF3/AN3
60
PF4/AN4
59
PF5/AN5
58
PF6/AN6
57
PF7/AN7
56
AVDD
PI7
21
55
AVREF
PI6
22
54
AVSS
PI5
23
53
SCK0
PI4
24
52
SO0
PI3
25
51
SI0
Note) 1. NC (Pin 88) is always connected to VDD.
2. VSS (Pins 39 and 86) are both connected to GND.
3. MP (Pin 37) is always connected to GND.
–5–
CS0
PH0/SCK1
PH2/SI1
PH1/SO1
PH4
PH3/CS1/INT1
PH5
PH6
PH7
EXTAL
XTAL
VSS
RST
MP
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ7
PJ6
PI0
PI2
PI1
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
CXP87500
EPROM Read Timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, VSS = 0V reference)
Item
Symbol
Pin
Min.
Address → data
input delay time
tACC
A0 to A15
D0 to D7
Address → data
hold time
tIH
A0 to A15
D0 to D7
Max.
Unit
100
ns
ns
0
0.8VDD
A0 to A15
Address data
0.2VDD
tACC
tIH
0.8VDD
D0 to D7
Input data
0.2VDD
Products List
Products
Mask
Optional item
CXP87532
Piggyback/evaluator
CXP87540
100-pin plastic QFP/LQFP
Package
32Kbytes
ROM capacity
40Kbytes
CXP87500-U01Q
CXP87500-U01R
100-pin ceramic
PQFP
EPROM 40Kbytes
Pull-up resistance for reset pin
Existent/Non-existent
Existent
Power on reset circuit
Existent/Non-existent
Existent
CMOS schmitt/TTLschmitt
TTL schmitt
Buffer amplifier/Normal input
Buffer amplifier
Input circuit
format∗1
PG0 to PG7, PK1
PK0
∗1 On PK1/MCLK pin and PG0/EXI0 to PG7/RFG1 pin, the input circuit format of CMOS schmitt or TTL
schmitt can be selected to every pin.
On PK0/RFDT pin, buffer amplifier or normal input circuit format can be selected.
–6–
CXP87500
Piggyback mode/evaluator mode can be switched as shown below.
Piggyback mode
Piggyback/evaluator product
Evaluator mode
Pin 1 marking
LCC type EPROM
Pin 1 marking
Pin 1 index
Note)
CPU probe
EPROM adaptor
Pin 1 marking
Note) Evaluator cap should be
connected to CPU probe.
Pin 1 index
CPU probe for LQFP
–7–
CXP87500
Package Outline
Unit: mm
100PIN PQFP (CERAMIC)
18.7
PIN NO. 1 INDEX
16.3 ± 0.2
INDEX
100
81
81
80
PIN No. 1 INDEX
1
80
0.65 ± 0.05
1
100
0.3 ± 0.08
14.22
18.12 ± 0.2
1.27 ± 0.13
12.02
30
0.7
1.0
0.3
6.0
24.7
22.3 ± 0.25
4.5
51
31
1.3 ± 0.3
51
50
9.48
11.66
30
50
31
0.45
15.58 ± 0.2
PACKAGE STRUCTURE
PACKAGE MATERIAL
PQFP-100C-L01
LEAD TREATMENT
GOLD PLATING
EIAJ CODE
AQFP100-C-0000-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
5.7g
10.44 MAX
+ 0.05
0.15 – 0.02
0.50 ± 0.25
JEDEC CODE
3.57 ± 0.36
CERAMIC
SONY CODE
100PIN PQFP (CERAMIC)
16.0 ± 0.4
12.4
14.0 ± 0.2
75
51
76
0.5 ± 0.05
+ 0.08
0.18 – 0.03
1.5
3.2 ± 0.2
0.5 ± 0.05
12.0 ± 0.15
+ 0.08
0.18 – 0.03
0.8 ± 0.2
26
100
1
INDEX
12.0 ± 0.15
50
25
12.8 ± 0.2
INDEX
6.9
+ 0.15
0.2 – 0.13
+ 0.05
0.127 – 0.02
3.32
PACKAGE STRUCTURE
PACKAGE MATERIAL
CERAMIC
SONY CODE
PQFP-100C-L02
LEAD TREATMENT
GOLD PLATING
EIAJ CODE
AQFP100-C-1414-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
2.2g
JEDEC CODE
–8–
Similar pages