ON MC100EPT25DR2 −3.3v / −5v differential ecl to 3.3v lvttl translator Datasheet

MC100EPT25
−3.3V / −5VDifferential ECL
to +3.3V LVTTL Translator
Description
The MC100EPT25 is a Differential ECL to LVTTL translator. This
device requires +3.3 V, −3.3 V to −5.2 V, and ground. The small
outline 8−lead package and the single gate of the EPT25 make it ideal
for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a single−ended
input mode. In this mode the VBB output is tied to the D input for a
inverting buffer or the D input for a non−inverting buffer. If used, the
VBB pin should be bypassed to ground with at least a 0.01 mF
capacitor.
Features
• 1.1 ns Typical Propagation Delay
• Maximum Frequency > 275 MHz Typical
• Operating Range: VCC = 3.0 V to 3.6 V;
MARKING DIAGRAMS*
8
8
1
SOIC−8
D SUFFIX
CASE 751
1
8
8
1
VEE = −5.5 V to −3.0 V; GND = 0 V
24 mA TTL Outputs
Q Output Will Default LOW with Inputs Open or at VEE
VBB Output
Open Input Default State
Safety Clamp on Inputs
Pb−Free Packages are Available
KPT25
ALYW
G
TSSOP−8
DT SUFFIX
CASE 948R
1
KP25
ALYWG
G
3V MG
G
•
•
•
•
•
•
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DFN8
MN SUFFIX
CASE 506AA
A
L
Y
W
M
G
1
4
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 14
1
Publication Order Number:
MC100EPT25/D
MC100EPT25
VEE
D
D
1
8
LVTTL
2
3
7
6
Table 1. PIN DESCRIPTION
VCC
Q
NC
LVECL/ECL
VBB
4
5
GND
PIN
FUNCTION
Q
LVTTL Output
D*, D*
Differential ECL Input Pair
VCC
Positive Supply
VBB
Output Reference Voltage
GND
Ground
VEE
Negative Supply
NC
No Connect
EP
Exposed pad must be connected
to a sufficient thermal conduit.
Electrically connect to the most
negative supply or leave floating
open.
Figure 1. 8−Lead Pinout (Top View) and Logic Diagram
* Pins will default LOW when left open.
Table 2. ATTRIBUTES
Characteristics
Value
Internal Input Pulldown Resistor
75 kW
Internal Input Pullup Resistor
ESD Protection
N/A
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
TSSOP−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL−94 V−0 @ 0.125 in
111 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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2
MC100EPT25
Table 3. MAXIMUM RATINGS
Rating
Unit
VCC
Symbol
Positive Power Supply
Parameter
GND = 0 V
Condition 1
VEE = −5.0 V
3.8
V
VEE
Negative Power Supply
GND = 0 V
VCC = +3.3 V
−6
V
VIN
Input Voltage
GND = 0 V
0 to VEE
V
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 SOIC
8 SOIC
190
130
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 SOIC
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
8 TSSOP
8 TSSOP
185
140
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
8 TSSOP
41 to 44
°C/W
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
DFN8
DFN8
129
84
°C/W
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
265
°C
Pb
Pb−Free
Condition 2
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 4. NECL DC CHARACTERISTICS VCC = 3.3 V; VEE = −5.5 V to −3.0 V; GND = 0.0 V (Note 2)
−40°C
Symbol
Characteristic
25°C
85°C
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
8.0
16
25
8.0
16
25
8.0
16
25
mA
IEE
Power Supply Current
VIH
Input HIGH Voltage Single−Ended
−1225
−880
−1225
−880
−1225
−880
mV
VIL
Input LOW Voltage Single−Ended
−1945
−1625
−1945
−1625
−1945
−1625
mV
VBB
Output Voltage Reference
−1525
−1325
−1525
−1325
−1525
−1325
mV
VIHCMR
Input HIGH Voltage Common Mode
Range (Note 3)
0.0
V
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
−1425
VEE + 2.0
0.0
−1425
VEE + 2.0
0.0
150
0.5
VEE + 2.0
150
0.5
−1425
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
2. Input parameters vary 1:1 with GND.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 5. TTL OUTPUT DC CHARACTERISTICS VCC = 3.3 V; VEE = −5.5 V to −3.0 V; GND = 0.0 V; TA = −40°C to 85°C
Symbol
Characteristic
Condition
Min
VOH
Output HIGH Voltage
IOH = −3.0 mA
VOL
Output LOW Voltage
IOL = 24 mA
ICCH
Power Supply Current
6
ICCL
Power Supply Current
7
Typ
Max
2.2
Unit
V
0.5
V
10
14
mA
12
17
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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3
MC100EPT25
Table 6. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; VEE = −5.5 V to −3.0 V; GND = 0.0 V (Note 4)
−40°C
Min
Characteristic
Symbol
fmax
Maximum Frequency
(See Figure 2 Fmax/JITTER)
275
tPLH, tPHL
Propagation Delay to Output Differential
(Cross−Point to 1.5 V)
500
tSKPP
Device−to−Device Skew (Note 5)
tJITTER
Random Clock Jitter (RMS)
(See Figure 2 Fmax/JITTER)
VPP
Input Voltage Swing (Differential)
tr
tf
Output Rise/Fall Times
(0.8 V − 2.0 V)
Typ
25°C
Max
Min
Typ
275
950
1300
800
0.2
<1
150
800
1200
300
900
474
1160
600
1400
Min
Typ
Max
275
950
500
Q, Q
85°C
Max
1600
Unit
MHz
800
960
1600
ps
500
ps
0.2
<1
ps
500
0.2
<1
150
800
1200
150
800
1200
mV
300
900
459
1100
600
1400
300
900
457
1100
600
1400
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured with a 750 mV 50% duty−cycle clock source. RL = 500 W to GND and CL = 20 pF to GND. Refer to Figure 3.
5. Skews are measured between outputs under identical conditions.
7
2800
VOH
6
2000
5
1600
4
1200
3
VOL 0.5 V
2
800
400
0
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉÉ
(JITTER)
25
100
175
250
325
400
FREQUENCY (MHz)
Figure 2. Fmax/Jitter
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4
475
550
1
625
JITTEROUT ps (RMS)
VOUTpp (mV)
2400
É
É
MC100EPT25
APPLICATION
TTL RECEIVER
CHARACTERISTIC TEST
*CL includes
fixture
capacitance
CL *
RL
AC TEST LOAD
GND
Figure 3. TTL Output Loading Used for Device Evaluation
ORDERING INFORMATION
Package
Shipping†
SOIC−8
98 Units / Rail
MC100EPT25DG
SOIC−8
(Pb−Free)
98 Units / Rail
MC100EPT25DR2
SOIC−8
2500 / Tape & Reel
MC100EPT25DR2G
SOIC−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT25DT
TSSOP−8
100 Units / Rail
MC100EPT25DTG
TSSOP−8
(Pb−Free)
100 Units / Rail
MC100EPT25DTR2
TSSOP−8
2500 / Tape & Reel
MC100EPT25DTR2G
TSSOP−8
(Pb−Free)
2500 / Tape & Reel
MC100EPT25MNR4
DFN8
1000 / Tape & Reel
DFN8
(Pb−Free)
1000 / Tape & Reel
Device
MC100EPT25D
MC100EPT25MNR4G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MC100EPT25
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPSt I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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6
MC100EPT25
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AH
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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7
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
MC100EPT25
PACKAGE DIMENSIONS
TSSOP−8
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948R−02
ISSUE A
8x
0.15 (0.006) T U
0.10 (0.004)
S
2X
L/2
L
8
5
1
PIN 1
IDENT
0.15 (0.006) T U
K REF
S
M
T U
V
S
0.25 (0.010)
B
−U−
4
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED 0.25 (0.010)
PER SIDE.
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
6. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE −W−.
S
M
A
−V−
F
DETAIL E
C
0.10 (0.004)
−T− SEATING
PLANE
D
−W−
G
DETAIL E
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8
DIM
A
B
C
D
F
G
K
L
M
MILLIMETERS
MIN
MAX
2.90
3.10
2.90
3.10
0.80
1.10
0.05
0.15
0.40
0.70
0.65 BSC
0.25
0.40
4.90 BSC
0_
6_
INCHES
MIN
MAX
0.114
0.122
0.114
0.122
0.031
0.043
0.002
0.006
0.016
0.028
0.026 BSC
0.010
0.016
0.193 BSC
0_
6_
MC100EPT25
PACKAGE DIMENSIONS
DFN8
CASE 506AA−01
ISSUE D
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A
B
PIN ONE
REFERENCE
2X
0.10 C
2X
0.10 C
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
TOP VIEW
0.08 C
SEATING
PLANE
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.20
0.30
2.00 BSC
1.10
1.30
2.00 BSC
0.70
0.90
0.50 BSC
0.20
−−−
0.25
0.35
A
0.10 C
8X
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
E
(A3)
SIDE VIEW
A1
C
D2
e
e/2
4
1
8X
L
E2
K
8
5
8X
b
0.10 C A B
0.05 C
NOTE 3
BOTTOM VIEW
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
MC100EPT25/D
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