2.5 Ω CMOS Low Power Dual 2:1 Mux/Demux USB 1.1 Switch ADG787 FEATURES FUNCTIONAL BLOCK DIAGRAM USB 1.1 signal switching compliant −3 dB bandwidth, 150 MHz Tiny 10-lead LFCSP and MSOP packages, 10-ball WLCSP package Single-supply 1.8 V to 5.5 V operation Low on resistance 2.5 Ω typical 3.45 Ω maximum at 85°C Typical power consumption: <0.1 μW ADG787 S1A D1 S1B IN1 IN2 S2A D2 SWITCHES SHOWN FOR A LOGIC 0 INPUT APPLICATIONS 05250-001 S2B Figure 1. USB 1.1 signal switching circuits Cellular phones PDAs MP3 players Battery-powered systems Headphone switching Audio and video signal routing Communications systems GENERAL DESCRIPTION The ADG787 is a low voltage, CMOS device that contains two independently selectable single-pole, double-throw (SPDT) switches. It is designed as a general analog-to-digital switch and can also be used for routing USB 1.1 signals. MASK: FS (12Mbps) This device offers low on resistance of typically 2.5 Ω, making the part an attractive solution for applications that require low distortion through the switch. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. The ADG787 exhibits break-before-make switching action. 1 05250-032 The ADG787 comes in a 10-ball WLCSP, a tiny 10-lead LFCSP, and a tiny 10-lead MSOP. These packages make the ADG787 the ideal solution for space-constrained applications. 20.0ns/DIV VIN = 3V p-p TA = 25°C Figure 2. Eye Pattern; 12 Mbps, VDD = 4.2 V, PRBS 31 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. ADG787 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................6 Applications....................................................................................... 1 Truth Table .....................................................................................6 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................7 General Description ......................................................................... 1 Test Circuits ................................................................................ 11 Specifications..................................................................................... 3 Terminology .................................................................................... 13 Absolute Maximum Ratings............................................................ 5 Outline Dimensions ....................................................................... 14 ESD Caution.................................................................................. 5 Ordering Guide .......................................................................... 15 REVISION HISTORY 5/06—Rev. 0 to Rev. A Updated Formatting ...........................................................Universal Changes to Table 1............................................................................ 3 Changes to Table 3............................................................................ 5 Changes to Ordering Guide .......................................................... 15 1/05—Revision 0: Initial Version Rev. A | Page 2 of 16 ADG787 SPECIFICATIONS VDD = 4.2 V to 5.5 V, GND = 0 V, unless otherwise noted. Table 1. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (ΔRON) +25°C 2.5 3 0.02 B Version 1 Unit 0 to VDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max 3.45 0.1 On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tON 0.65 0.8 ±0.05 ±0.05 nA typ nA typ μA typ μA max pF typ VIN = VINL or VINH ±0.1 RL = 50 Ω, CL = 35 pF VS = 3 V; see Figure 31 RL = 50 Ω, CL = 35 pF VS = 3 V; see Figure 31 CL = 50 pF; VS = 3 V 14 −63 −110 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ −63 dB typ 0.03 −0.2 145 16 40 % dB typ MHz typ pF typ pF typ 0.005 μA typ μA max 0.005 2.5 Break-Before-Make Time Delay (tBBM) 10 22 6 0.15 5 Total Harmonic Distortion (THD + N) Insertion Loss −3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD 1 1 2 VDD = 4.2 V, VS = 0 V to VDD IS = 10 mA VDD = 5.5 V VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 29 VS = VD = 1 V or 4.5 V; see Figure 30 V min V max Propagation Delay Skew, tSKEW Charge Injection Off Isolation Channel-to-Channel Crosstalk VDD = 4.2 V, VS = 0 V to VDD, IS = 10 mA See Figure 28 VDD = 4.2 V, VS = 3.5 V, IS = 10 mA 2.0 0.8 13 19 3 5 0.06 tOFF 0.95 Test Conditions/Comments RL = 50 Ω, CL = 35 pF VS1 = VS2 = 3 V; see Figure 32 VD = 1 V, RS = 0 Ω, CL = 1 nF; see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 S1A to S2A/S1B to S2B; RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37 S1A to S1B/S2A to S2B; RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 36 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 2 V p-p RL = 50 Ω, CL = 5 pF; see Figure 36 RL = 50 Ω, CL = 5 pF; see Figure 36 VDD = 5.5 V Digital inputs = 0 V or 5.5 V Temperature ranges: B version: −40°C to +85°C for the MSOP and LFCSP packages, and −25°C to +85°C for the WLCSP package. Guaranteed by design, not production tested. Rev. A | Page 3 of 16 ADG787 VDD = 2.7 V to 3.6 V, GND = 0 V, unless otherwise noted. Table 2. Parameter ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (ΔRON) On Resistance Flatness (RFLAT (ON)) LEAKAGE CURRENTS Source Off Leakage, IS (OFF) Channel On Leakage, ID, IS (ON) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current IINL or IINH CIN, Digital Input Capacitance DYNAMIC CHARACTERISTICS 2 tON +25°C 4 5.75 0.07 0.3 1.6 2.3 6 0.35 2.6 ±0.01 ±0.01 nA typ nA typ μA typ μA max pF typ VIN = VINL or VINH RL = 50 Ω, CL = 35 pF VS = 1.5 V; see Figure 31 RL = 50 Ω, CL = 35 pF VS = 1.5 V; see Figure 31 CL = 50 pF; VS = 1.5 V 10 −63 −110 ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ −63 dB typ 0.07 −0.24 145 16 40 % dB typ MHz typ pF typ pF typ 0.005 μA typ μA max 2 15 35 7 0.12 5 1 1 2 VDD = 2.7 V, VS = 0 V to VDD IS = 10 mA; see Figure 28 VDD = 2.7 V, VS = 1.5 V IS = 10 mA VDD = 2.7 V, VS = 0 V to VDD IS = 10 mA VDD = 3.6 V VS = 0.6 V/3.3 V, VD = 3.3 V/0.6 V; see Figure 29 VS = VD = 0.6 V or 3.3 V; see Figure 30 ±0.1 0.005 Break-Before-Make Time Delay (tBBM) Total Harmonic Distortion (THD + N) Insertion Loss −3 dB Bandwidth CS (OFF) CD, CS (ON) POWER REQUIREMENTS IDD V Ω typ Ω max Ω typ Ω max Ω typ Ω max Test Conditions/Comments V min V max Propagation Delay Skew, tSKEW Charge Injection Off Isolation Channel-to-Channel Crosstalk Unit 1.3 0.8 18 30 4 6 0.04 tOFF B Version 1 RL = 50 Ω, CL = 35 pF VS1 = VS2 = 1.5 V; see Figure 32 VD = 1.25 V, RS = 0 Ω, CL = 1 nF; see Figure 33 RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 34 S1A to S2A/S1B to S2B; RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 37 S1A to S1B/S2A to S2B; RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 35 RL = 32 Ω, f = 20 Hz to 20 kHz, VS = 1.5 V p-p RL = 50 Ω, CL = 5 pF; see Figure 36 RL = 50 Ω, CL = 5 pF; see Figure 36 VDD = 3.6 V Digital inputs = 0 V or 3.6 V Temperature range: B version: −40°C to +85°C for the MSOP and LFCSP packages, and −25°C to +85°C for the WLCSP package. Guaranteed by design, not production tested. Rev. A | Page 4 of 16 ADG787 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VDD to GND Analog Inputs 1 , Digital Inputs Peak Current, S or D 5 V Operation 3.3 V Operation Continuous Current, S or D 5 V Operation 3.3 V Operation Operating Temperature Range Extended Industrial (B Version) MSOP and LFCSP packages Industrial (B version) WLCSP package Storage Temperature Range Junction Temperature WLCSP Package (4-Layer Board) θJA Thermal Impedance LFCSP Package (4-Layer Board) θJA Thermal Impedance MSOP Package (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance Lead-Free Temperature Soldering IR Reflow, Peak Temperature Peak Temperature Time at Peak Temperature 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rating −0.3 V to +6 V −0.3 V to VDD + 0.3 V or 30 mA (whichever occurs first) 300 mA 200 mA (pulsed at 1 ms, 10% duty cycle max) Only one absolute maximum rating may be applied at any one time. 100 mA 80 mA −40°C to +85°C −25°C to +85°C −65°C to +150°C 150°C 120°C/W 61°C/W 142°C/W 43.7°C/W 260(+0/−5)°C 10 sec to 40 sec Overvoltages at the IN, S, or D pins are clamped by internal diodes. Current should be limited to the maximum ratings given. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 16 ADG787 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS a b c 1 S1B GND S2B ADG787 S2A 9 D2 D1 3 8 IN2 TOP VIEW IN1 4 (Not to Scale) 7 S2B S1B 5 6 GND 2 IN1 IN2 D1 D2 3 4 S1A VDD S2A 05250-003 S1A 2 10 05250-002 VDD 1 TOP VIEW (BALLS AT THE BOTTOM) Figure 3. 10-Lead LFCSP and 10-lead MSOP Pin Configuration Figure 4. 10-Ball WLCSP Pin Configuration Table 4. 10-Lead LFCSP/MSOP Pin Function Descriptions Table 5. 10-Lead WLCSP Pin Function Descriptions Pin No. 1 2 Mnemonic VDD S1A Ball Location 1a Mnemonic S1B 3 D1 1b 1c GND S2B 4 5 IN1 S1B 2a IN1 6 7 GND S2B 2c 3a IN2 D1 3c D2 8 9 IN2 D2 10 S2A 4a 4b 4c S1A VDD S2A Description Most Positive Power Supply Potential. Source Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Source Terminal. May be an input or output. Ground (0 V) Reference. Source Terminal. May be an input or output. Logic Control Input. Drain Terminal. May be an input or output. Source Terminal. May be an input or output. Description Source Terminal. May be an input or output. Ground (0 V) Reference. Source Terminal. May be an input or output. Source Terminal. May be an input or output. Logic Control Input. Drain Terminal. May be an input or output. Drain Terminal. May be an input or output. Logic Control Input. Most Positive Power Supply Potential. Source Terminal. May be an input or output. TRUTH TABLE Table 6. Logic (IN1/IN2) 0 1 Switch 1A/2A Off On Rev. A | Page 6 of 16 Switch 1B/2B On Off ADG787 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 3.5 VDD = 4.2V IDS = 10mA TA = 25°C IDS = 10mA VDD = 4.5V 3.0 2.5 TA = +85°C ON RESISTANCE (W) 2.0 VDD = 5V VDD = 5.5V 1.5 1.0 0.5 0 1 2 3 SIGNAL RANGE 4 2.0 TA = +25°C 1.5 TA = –40°C 1.0 0.5 05250-004 0 2.5 05250-007 ON RESISTANCE (W) VDD = 4.2V 0 5 0 Figure 5. On Resistance vs. VD (VS), VDD = 4.2 V to 5.5 V 0.5 1.0 1.5 5.0 TA = 25°C 4.5 IDS = 10mA 4.5 4.0 TA = +85°C 4.0 VDD = 3V ON RESISTANCE (W) 3.0 2.5 VDD = 3.3V VDD = 3.6V 1.5 3.0 2.5 TA = +25°C TA = –40°C 2.0 1.5 1.0 05250-005 1.0 3.5 0.5 0 0 0.5 1.0 1.5 2.0 2.5 SIGNAL RANGE 3.0 3.5 05250-008 ON RESISTANCE (W) 3.5 VDD = 3V IDS = 10mA VDD = 2.7V 4.0 2.0 3.0 Figure 8. On Resistance vs. VD (VS) for Different Temperatures, VDD = 4.2 V 5.0 3.5 2.0 2.5 SIGNAL RANGE 0.5 0 4.0 0 Figure 6. On Resistance vs. VD (VS), VDD = 2.7 V to 3.6 V 0.5 1.0 1.5 2.0 SIGNAL RANGE 2.5 3.0 Figure 9. On Resistance vs. VD (VS) for Different Temperatures, VDD = 3 V 3.0 2.0 VDD = 5V IDS = 10mA 1.5 2.5 1.0 IS, ID (ON) 2.0 CURRENT (nA) ON RESISTANCE (W) TA = +85°C TA = +25°C 1.5 TA = –40°C 1.0 0.5 0 –0.5 IS (OFF) –1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 SIGNAL RANGE 3.5 4.0 4.5 05250-040 05250-006 –1.5 –2.0 5.0 0 Figure 7. On Resistance vs. VD (VS) for Different Temperatures, VDD = 5 V Rev. A | Page 7 of 16 10 20 30 40 50 60 TEMPERATURE (°C) 70 80 Figure 10. Leakage Current vs. Temperature, VDD = 5.5 V ADG787 2.0 30 TA = 25°C 1.5 25 1.0 VDD = 3V 20 TIME (ns) 0 TON 15 VDD = 5V –0.5 10 IS, ID (ON) –1.0 TOFF VDD = 3V 5 05250-041 –1.5 –2.0 0 10 20 30 40 50 60 TEMPERATURE (°C) VDD = 5V 0 –40 80 70 Figure 11. Leakage Current vs. Temperature, VDD = 3.3 V 0 20 40 TEMPERATURE (°C) 60 80 0 1.8 –1 1.6 LOGIC THRESHOLD POINT (V) –20 Figure 14. tON/tOFF Time vs. Temperature 2.0 –2 ATTENUATION (dB) 1.4 1.2 VIN RISING VIN FALLING 1.0 0.8 0.6 VDD = 3V/4.2V/5V TA = 25°C –3 –4 –5 –6 0.4 2.0 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE VDD (V) 5.0 –8 100 5.5 05250-014 0 1.5 –7 05250-011 0.2 1k Figure 12. Threshold Voltage vs. Supply 10k 100k 1M FREQUENCY (Hz) 10M 100M 1G 10M 100M 1G Figure 15. Bandwidth 25 0 TA = 25°C VDD = 3V/4.2V/5V TA = 25°C VDD = 5V –20 ATTENUATION (dB) 20 15 VDD = 3V 10 5 –40 –60 –80 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VD (V) 3.5 4.0 4.5 –120 100 5.0 05250-015 –100 05250-012 QINJ (pC) 05250-013 CURRENT (nA) IS (OFF) 0.5 1k 10k 100k 1M FREQUENCY (Hz) Figure 16. Off Isolation vs. Frequency Figure 13. Charge Injection vs. Source Voltage Rev. A | Page 8 of 16 ADG787 0 3.0 VDD = 3V/4.2V/5V TA = 25°C INPUT RISE/FALL TIME = 15ns TA = 25°C 2.5 –40 2.0 S1A TO S1B DELAY (ns) –60 S1A TO S2A –80 1.5 1.0 RISE DELAY –100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M FALL DELAY 0 2.7 1G Figure 17. Crosstalk vs. Frequency 0 3.7 4.2 4.7 SUPPLY VOLTAGE (V) 5.2 2.0 1.8 INPUT RISE/FALL TIME = 15ns VDD = 4.2V 1.6 1.4 DELAY (ns) –40 PSRR (dB) 3.2 Figure 20. Rise/Fall Time Delay vs. Supply Voltage VDD = 3V/4.2V/5V TA = 25°C NO SUPPLY DECOUPLING –20 05250-044 –120 100 05250-030 0.5 –60 –80 1.2 1.0 RISE DELAY 0.8 0.6 FALL DELAY 0.4 –120 100 05250-031 –100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M 05250-045 ATTENUATION (dB) –20 0.2 0 –40 1G Figure 18. AC Power Supply Rejection Ratio (PSRR) –15 10 35 TEMPERATURE (°C) 60 85 Figure 21. Rise/Fall Time Delay vs. Temperature 0.10 2.0 INPUT RISE/FALL TIME = 15ns TA = 25°C 0.09 0.08 MISMATCH (ns) 0.06 0.05 0.04 VDD = 5V, VS = 2V p-p 0.03 1.0 0.5 0.01 0 10 100 1k FREQUENCY (Hz) 10k 0 2.5 100k Figure 19. Total Harmonic Distortion + Noise 05250-046 0.02 05250-043 THD+N (%) 1.5 VDD = 3V, VS = 2V p-p 0.07 3.0 3.5 4.0 SUPPLY (V) 4.5 5.0 5.5 Figure 22. Rise-Time-to-Fall-Time Mismatch vs. Supply Voltage Rev. A | Page 9 of 16 ADG787 1.2 INPUT RISE/FALL TIME = 15ns VDD = 4.2V MASK: FS (12Mbps) MISMATCH (ns) 1.0 0.8 0.6 0.4 1 05250-047 0 –40 05250-033 0.2 –15 10 35 TEMPERATURE (°C) 60 20.0ns/DIV 2.5GS/s 400ps/pt 85 Figure 26. Eye Pattern, 12 Mbps, VDD = 4.2 V, TA = 85°C, PRBS 31 Figure 23. Rise-Time-to-Fall-Time Mismatch vs. Temperature 300 INPUT RISE/FALL TIME = 15ns TA = 25°C MASK: FS (12Mbps) TPROP SKEW (ps) 250 200 150 100 1 05250-048 0 2.5 05250-034 50 3.0 3.5 4.0 SUPPLY (V) 4.5 5.0 20.0ns/DIV 2.5GS/s 400ps/pt 5.5 Figure 27. Eye Pattern, 12 Mbps, VDD = 4.2 V, TA = −40°C, PRBS 31 Figure 24. Propagation Delay Skew (tSKEW) vs. Supply Voltage 200 INPUT RISE/FALL TIME = 15ns 180 VDD = 4.2V 160 120 100 80 60 40 05250-049 TSKEW (ps) 140 20 0 –40 –15 10 35 TEMPERATURE (°C) 60 85 Figure 25. Propagation Delay Skew (tSKEW) vs. Temperature Rev. A | Page 10 of 16 ADG787 TEST CIRCUITS IS (OFF) IDS ID (OFF) S A D A VS S 05250-017 V1 VD D RON = V1/IDS ID (ON) Figure 28. On Resistance S NC D A VD Figure 30. On Leakage VDD 0.1μF VDD S1B S1A VS VOUT D CL 35pF RL 50Ω IN 50% VIN 50% 90% 90% GND tON tOFF 05250-019 VOUT Figure 31. Switching Times, tON, tOFF VDD 0.1μF VIN S1B S1A VS 50% 50% 0V VDD VOUT D VOUT RL IN CL 35pF 80% tBBM tBBM 05250-020 50Ω 80% GND Figure 32. Break-Before-Make Time Delay, tBBM VDD SW ON S1B NC D S1A VOUT 1nF IN VOUT ΔVOUT QINJ = CL ⋅ ΔVOUT GND Figure 33. Charge Injection Rev. A | Page 11 of 16 05250-021 VS SW OFF VIN 05250-018 VS 05250-016 Figure 29. Off Leakage ADG787 VDD 0.1μF 0.1μF NETWORK ANALYZER VDD S1A 50Ω 50Ω NETWORK ANALYZER VDD S1B 50Ω S1A VS VS D D VOUT 05250-022 RL 50Ω GND OFF ISOLATION = 20 LOG RL 50Ω GND VOUT INSERTION LOSS = 20 LOG VS Figure 34. Off Isolation VOUT WITH SWITCH VOUT WITHOUT SWITCH Figure 36. Bandwidth VDD NETWORK ANALYZER 0.1μF VOUT 50Ω VDD S2A D2 NC S2B S1A RL 50Ω D S1B 50Ω 50Ω RL 50Ω VS S1A VS GND VOUT VS CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG 05250-023 CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG D1 S1B NC VOUT VS Figure 37. Channel-to-Channel Crosstalk (S1A to S2A) Figure 35. Channel-to-Channel Crosstalk (S1A to S1B) Rev. A | Page 12 of 16 50Ω 05250-025 VOUT VOUT 05250-024 S1B NC VDD ADG787 TERMINOLOGY IDD Positive supply current. tOFF Delay time between the 50% and the 90% points of the digital input and switch off condition. VD (VS) Analog voltage on Terminal D and Terminal S. tBBM On or off time measured between the 80% points of both switches when switching from one to another. RON Ohmic resistance between D and S. RFLAT (ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during on-off switching. Off Isolation A measure of unwanted signal coupling through an off switch. ΔRON On resistance match between any two channels. IS (OFF) Source leakage current with the switch off. Crosstalk A measure of unwanted signal that is coupled from one channel to another as a result of parasitic capacitance. ID (OFF) Drain leakage current with the switch off. −3 dB Bandwidth The frequency at which the output is attenuated by 3 dB. ID, IS (ON) Channel leakage current with the switch on. On Response The frequency response of the on switch. VINL Maximum input voltage for Logic 0. Insertion Loss The loss due to the on resistance of the switch. VINH Minimum input voltage for Logic 1. THD + N The ratio of the harmonic amplitudes plus noise of a signal, to the fundamental. IINL (IINH) Input current of the digital input. TSKEW The measure of the variation in propagation delay between each channel. CS (OFF) Off switch source capacitance. Measured with reference to ground. Rise Time Delay The rise time of a signal is a measure of the time for the signal to rise from 10% of the ON level to 90% of the ON level. Rise time delay is the difference between the rise time, measured at the input, and the rise time, measured at the output. CD (OFF) Off switch drain capacitance. Measured with reference to ground. CD, CS (ON) On switch capacitance. Measured with reference to ground. CIN Digital input capacitance. tON Delay time between the 50% and the 90% points of the digital input and switch on condition. Fall Time Delay The fall time of a signal is a measure of the time for the signal to fall from 90% of the ON level to 10% of the ON level. Fall time delay is the difference between the fall time, measured at the input, and the fall time, measured at the output. Rise-Time-to-Fall-Time Mismatch This is the absolute value between the variation in the fall time and the rise time, measured at the output. Rev. A | Page 13 of 16 ADG787 OUTLINE DIMENSIONS INDEX AREA PIN 1 INDICATOR 3.00 BSC SQ 10 1.50 BCS SQ 0.50 BSC 1 TOP VIEW (BOTTOM VIEW) 6 0.80 MAX 0.55 TYP 0.80 0.75 0.70 5 0.50 0.40 0.30 1.74 1.64 1.49 0.05 MAX 0.02 NOM SIDE VIEW SEATING PLANE 2.48 2.38 2.23 EXPOSED PAD 0.30 0.23 0.18 0.20 REF Figure 38. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD] 3 mm × 3 mm Body, Very, Very Thin, Dual Lead (CP-10-9) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5.15 4.90 4.65 5 PIN 1 0.50 BSC 0.95 0.85 0.75 0.15 0.05 1.10 MAX 0.33 0.17 SEATING PLANE 0.23 0.08 8° 0° COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 39. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Rev. A | Page 14 of 16 0.80 0.60 0.40 ADG787 0.63 0.57 0.51 SEATING PLANE 1.56 1.50 1.44 C B A 1 0.36 0.32 0.28 BALL 1 IDENTIFIER 2.06 2.00 1.94 2 0.50 BSC BALL PITCH 3 4 TOP VIEW (BALL SIDE DOWN) 0.11 0.09 0.07 BOTTOM VIEW (BALL SIDE UP) 111105-0 0.26 0.22 0.18 Figure 40. 10-Ball Wafer Level Chip Scale Package [WLCSP] (CB-10) Dimensions shown in millimeters ORDERING GUIDE Model ADG787BRMZ 2 ADG787BRMZ-500RL72 ADG787BRMZ-REEL2 ADG787BCBZ-500RL72 ADG787BCBZ-REEL2 ADG787BCPZ-500RL72 ADG787BCPZ-REEL2 1 2 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –25°C to +85°C –25°C to +85°C –40°C to +85°C –40°C to +85°C Package Description 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Lead Mini Small Outline Package (MSOP) 10-Ball Wafer Level Chip Scale Package (WLCSP) 10-Ball Wafer Level Chip Scale Package (WLCSP) 10-Lead Lead Frame Chip Scale Package (LFCSP_WD) 10-Lead Lead Frame Chip Scale Package (LFCSP_WD) Due to space constraints, branding on this package is limited to three characters. Z = Pb-free part. Rev. A | Page 15 of 16 Package Option RM-10 RM-10 RM-10 CB-10 CB-10 CP-10-9 CP-10-9 Branding 1 SM1 SM1 SM1 S04 S04 SM1 SM1 ADG787 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05250-0-5/06(A) Rev. A | Page 16 of 16