TI DS90LV048ATMTC Ds90lv048a 3v lvds quad cmos differential line receiver Datasheet

DS90LV048A
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SNLS045B – JULY 1999 – REVISED APRIL 2013
DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver
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FEATURES
DESCRIPTION
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The DS90LV048A is a quad CMOS flow-through
differential line receiver designed for applications
requiring ultra low power dissipation and high data
rates. The device is designed to support data rates in
excess of 400 Mbps (200 MHz) utilizing Low Voltage
Differential Signaling (LVDS) technology.
1
2
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>400 Mbps (200 MHz) Switching Rates
Flow-Through Pinout Simplifies PCB Layout
150 ps Channel-to-Channel Skew (Typical)
100 ps Differential Skew (Typical)
2.7 ns Maximum Propagation Delay
3.3V Power Supply Design
High Impedance LVDS Inputs on Power Down
Low Power Design (40mW @ 3.3V Static)
Interoperable with Existing 5V LVDS Drivers
Accepts Small Swing (350 mV Typical)
Differential Signal Levels
Supports Open, Short and Terminated Input
Fail-Safe
0V to −100mV Threshold Region
Conforms to ANSI/TIA/EIA-644 Standard
Industrial Temperature Operating Range (-40°C
to +85°C)
Available in SOIC and TSSOP Package
The DS90LV048A accepts low voltage (350 mV
typical) differential input signals and translates them
to 3V CMOS output levels. The receiver supports a
TRI-STATE function that may be used to multiplex
outputs. The receiver also supports open, shorted
and terminated (100Ω) input fail-safe. The receiver
output will be HIGH for all fail-safe conditions. The
DS90LV048A has a flow-through pinout for easy PCB
layout.
The EN and EN* inputs are ANDed together and
control the TRI-STATE outputs. The enables are
common to all four receivers. The DS90LV048A and
companion LVDS line driver (eg. DS90LV047A)
provide a new alternative to high power PECL/ECL
devices for high speed point-to-point interface
applications.
Connection Diagram
Order Number DS90LV048ATM, DS90LV048ATMTC
D0016A, PW0016A Packages
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated
DS90LV048A
SNLS045B – JULY 1999 – REVISED APRIL 2013
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Functional Diagram
TRUTH TABLE
ENABLES
EN
EN*
H
L or Open
All other combinations of ENABLE inputs
INPUTS
OUTPUT
RIN+ − RIN−
ROUT
VID ≥ 0V
H
VID ≤ −0.1V
L
Full Fail-safe
OPEN/SHORT or
Terminated
H
X
Z
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
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ABSOLUTE MAXIMUM RATINGS (1) (2)
Supply Voltage (VCC)
−0.3V to +4V
Input Voltage (RIN+, RIN−)
−0.3V to 3.9V
Enable Input Voltage (EN, EN*)
−0.3V to (VCC + 0.3V)
Output Voltage (ROUT)
−0.3V to (VCC + 0.3V)
Maximum Package Power Dissipation @ +25°C
D0016A Package
1025 mW
PW0016A Package
866 mW
Derate D0016A Package
8.2 mW/°C above +25°C
Derate PW0016A Package
6.9 mW/°C above +25°C
−65°C to +150°C
Storage Temperature Range
Lead Temperature Range Soldering
(4 sec.)
+260°C
(HBM, 1.5 kΩ, 100 pF)
≥ 10 kV
Maximum Junction Temperature
ESD Rating (3)
+150°C
(EIAJ, 0 Ω, 200 pF)
(1)
(2)
(3)
≥ 1200 V
“Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be specified. They are not meant to imply
that the devices should be operated at these limits. ELECTRICAL CHARACTERISTICS specifies conditions of device operation.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
ESD Rating:
HBM (1.5 kΩ, 100 pF) ≥ 10kV
EIAJ (0Ω, 200 pF) ≥ 1200V
RECOMMENDED OPERATING CONDITIONS
Min
Typ
Max
Units
Supply Voltage (VCC)
+3.0
+3.3
+3.6
V
Receiver Input Voltage
GND
Operating Free Air Temperature (TA)
−40
25
+3.0
V
+85
°C
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ELECTRICAL CHARACTERISTICS
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2)
Symbol
Parameter
Conditions
VCM = +1.2V, 0.05V, 2.95V
(3)
Pin
Min
RIN+,
RIN−
−100
VTH
Differential Input High Threshold
VTL
Differential Input Low Threshold
VCMR
Common-Mode Voltage Range
VID = 200mV pk to pk (4)
0.1
IIN
Input Current
VIN = +2.8V
−10
VOL
Output Low Voltage
Units
−35
0
mV
−35
V
+10
μA
−10
±1
+10
μA
-20
±1
+20
μA
2.7
3.3
V
IOH = −0.4 mA, Input terminated
2.7
3.3
V
IOH = −0.4 mA, Input shorted
2.7
3.3
VCC = 3.6V or 0V
VCC = 0V
IOH = −0.4 mA, VID = +200 mV
ROUT
IOL = 2 mA, VID = −200 mV
(5)
0.25
V
−15
−47
−100
mA
−10
±1
+10
μA
2.0
VCC
V
GND
0.8
V
+10
μA
9
15
mA
1
5
mA
Output Short Circuit Current
Enabled, VOUT = 0V
IOZ
Output TRI-STATE Current
Disabled, VOUT = 0V or VCC
VIH
Input High Voltage
VIL
Input Low Voltage
II
Input Current
VIN = 0V or VCC, Other Input = VCC or GND
−10
±5
VCL
Input Clamp Voltage
ICL = −18 mA
−1.5
−0.8
ICC
No Load Supply Current
Receivers Enabled
EN = VCC, Inputs Open
ICCZ
No Load Supply Current
Receivers Disabled
EN = GND, Inputs Open
(2)
(3)
(4)
(5)
4
EN,
EN*
VCC
V
0.05
IOS
(1)
mV
±5
VIN = +3.6V
Output High Voltage
Max
2.3
VIN = 0V
VOH
Typ
V
Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
unless otherwise specified.
All typicals are given for: VCC = +3.3V, TA = +25°C.
VCC is always higher than RIN+ and RIN− voltage. RIN− and RIN+ are allowed to have a voltage range −0.2V to VCC− VID/2. However, to
be compliant with AC specifications, the common voltage range is 0.1V to 2.3V
The VCMR range is reduced for larger VID. Example: if VID = 400mV, the VCMR is 0.2V to 2.2V. The fail-safe condition with inputs
shorted is not supported over the common-mode range of 0V to 2.4V, but is supported only with inputs shorted and no external
common-mode voltage applied. A VID up to VCC− 0V may be applied to the RIN+/ RIN− inputs with the Common-Mode voltage set to
VCC/2. Propagation delay and Differential Pulse skew decrease when VID is increased from 200mV to 400mV. Skew specifications
apply for 200mV ≤ VID ≤ 800mV over the common-mode range .
Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted
at a time, do not exceed maximum junction temperature specification.
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SWITCHING CHARACTERISTICS
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (1) (2) (3) (4)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
1.2
2.0
2.7
ns
1.2
1.9
2.7
ns
0
0.1
0.4
ns
0
0.15
0.5
ns
tSKD3
Differential Part to Part Skew
(4)
1.0
ns
tSKD4
Differential Part to Part Skew (6)
1.5
ns
tTLH
Rise Time
0.5
1.0
ns
tTHL
Fall Time
0.35
1.0
ns
tPHZ
Disable Time High to Z
8
14
ns
tPLZ
Disable Time Low to Z
8
14
ns
tPZH
Enable Time Z to High
9
14
ns
tPZL
Enable Time Z to Low
9
14
fMAX
Maximum Operating Frequency (7)
tPHLD
Differential Propagation Delay High to Low
tPLHD
Differential Propagation Delay Low to High
tSKD1
Differential Pulse Skew |tPHLD − tPLHD| (5)
tSKD2
Differential Channel-to-Channel Skew; same device (3)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
CL = 15 pF
VID = 200 mV
(Figure 1 and Figure 2)
RL = 2 kΩ
CL = 15 pF
(Figure 3 and Figure 4)
All Channels Switching
200
250
ns
MHz
All typicals are given for: VCC = +3.3V, TA = +25°C.
Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0% to 100%) ≤ 3 ns for RIN.
tSKD2, Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the
same chip with any event on the inputs.
tSKD3, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
at the same VCC, and within 5°C of each other within the operating temperature range.
tSKD1 is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of
the same channel
tSKD4, part to part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices
over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max−Min| differential
propagation delay.
fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, differential (1.05V to 1.35V peak to peak). Output criteria:
60/40% duty cycle, VOL (max 0.4V), VOH (min 2.7V), Load = 15 pF (stray plus probes).
PARAMETER MEASUREMENT INFORMATION
Figure 1. Receiver Propagation Delay and Transition Time Test Circuit
Figure 2. Receiver Propagation Delay and Transition Time Waveforms
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PARAMETER MEASUREMENT INFORMATION (continued)
CL includes load and test jig capacitance.
S1 = VCC for tPZL and tPLZ measurements.
S1 = GND for tPZH and tPHZ measurements.
Figure 3. Receiver TRI-STATE Delay Test Circuit
Figure 4. Receiver TRI-STATE Delay Waveforms
TYPICAL APPLICATION
Balanced System
Figure 5. Point-to-Point Application
6
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APPLICATION INFORMATION
General application guidelines and hints for LVDS drivers and receivers may be found in the following application
notes: LVDS Owner's Manual (lit #550062-002), AN-808 (SNLA028), AN-977 (SNLA166), AN-971 (SNLA165),
AN-916 (SNLA219), AN-805 (SNOA233), AN-903 (SNLA034). The latest applications material is available on the
web at: www.ti.com
LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as
is shown in Figure 5. This configuration provides a clean signaling environment for the fast edge rates of the
drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair
cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the
range of 100Ω. A termination resistor of 100Ω (selected to match the media), and is located as close to the
receiver input pins as possible. The termination resistor converts the driver output (current mode) into a voltage
that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the
effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground
shifting, noise margin limits, and total termination loading must be taken into account.
The DS90LV048A differential line receiver is capable of detecting signals as low as 100mV, over a ±1V commonmode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The
driven signal is centered around this voltage and may shift ±1V around this center point. The ±1V shifting may be
the result of a ground potential difference between the driver's ground reference and the receiver's ground
reference, the common-mode effects of coupled noise, or a combination of the two. The AC parameters of both
receiver input pins are optimized for a recommended operating input voltage range of 0V to +2.4V (measured
from each pin to ground). The device will operate for receiver input voltages up to VCC, but exceeding VCC will
turn on the ESD protection circuitry which will clamp the bus voltages.
The DS90LV048A has a flow-through pinout that allows for easy PCB layout. The LVDS signals on one side of
the device easily allows for matching electrical lengths of the differential pair trace lines between the driver and
the receiver as well as allowing the trace lines to be close together to couple noise as common-mode. Noise
isolation is achieved with the LVDS signals on one side of the device and the TTL signals on the other side.
Power Decoupling Recommendations
Bypass capacitors must be used on power pins. Use high frequency ceramic (surface mount is recommended)
0.1μF and 0.001μF capacitors in parallel at the power supply pin with the smallest value capacitor closest to the
device supply pin. Additional scattered capacitors over the printed circuit board will improve decoupling. Multiple
vias should be used to connect the decoupling capacitors to the power planes. A 10μF (35V) or greater solid
tantalum capacitor should be connected at the power entry point on the printed circuit board between the supply
and ground.
PC Board considerations
Use at least 4 PCB layers (top to bottom); LVDS signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a power/ground plane(s)
Keep drivers and receivers as close to the (LVDS port side) connectors as possible.
Differential Traces
Use controlled impedance traces which match the differential impedance of your transmission medium (ie. cable)
and termination resistor. Run the differential pair trace lines as close together as possible as soon as they leave
the IC (stubs should be < 10mm long). This will help eliminate reflections and ensure noise is coupled as
common-mode. In fact, we have seen that differential signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is much better with the closer traces. In addition, noise
induced on the differential lines is much more likely to appear as common-mode which is rejected by the
receiver.
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Match electrical lengths between traces to reduce skew. Skew between the signals of a pair means a phase
difference between signals which destroys the magnetic field cancellation benefits of differential signals and EMI
will result. (Note the velocity of propagation, v = c/Er where c (the speed of light) = 0.2997mm/ps or 0.0118
in/ps). Do not rely solely on the autoroute function for differential traces. Carefully review dimensions to match
differential impedance and provide isolation for the differential lines. Minimize the number or vias and other
discontinuities on the line.
Avoid 90° turns (these cause impedance discontinuities). Use arcs or 45° bevels.
Within a pair of traces, the distance between the two traces should be minimized to maintain common-mode
rejection of the receivers. On the printed circuit board, this distance should remain constant to avoid
discontinuities in differential impedance. Minor violations at connection points are allowable.
Termination
Use a termination resistor which best matches the differential impedance or your transmission line. The resistor
should be between 90Ω and 130Ω. Remember that the current mode outputs need the termination resistor to
generate the differential voltage. LVDS will not work without resistor termination. Typically, connecting a single
resistor across the pair at the receiver end will suffice.
Surface mount 1% to 2% resistors are best. PCB stubs, component lead, and the distance from the termination
to the receiver inputs should be minimized. The distance between the termination resistor and the receiver
should be < 10mm (12mm MAX)
Probing LVDS Transmission Lines
Always use high impedance (> 100kΩ), low capacitance (< 2 pF) scope probes with a wide bandwidth (1 GHz)
scope. Improper probing will give deceiving results.
Cables and Connectors, General Comments
When choosing cable and connectors for LVDS it is important to remember:
Use controlled impedance media. The cables and connectors you use should have a matched differential
impedance of about 100Ω. They should not introduce major impedance discontinuities.
Balanced cables (e.g. twisted pair) are usually better than unbalanced cables (ribbon cable, simple coax.) for
noise reduction and signal quality. Balanced cables tend to generate less EMI due to field canceling effects and
also tend to pick up electromagnetic radiation a common-mode (not differential mode) noise which is rejected by
the receiver.
For cable distances < 0.5M, most cables can be made to work effectively. For distances 0.5M ≤ d ≤ 10M, CAT 3
(category 3) twisted pair cable works well, is readily available and relatively inexpensive.
Threshold
The LVDS Standard (ANSI/TIA/EIA-644) specifies a maximum threshold of ±100mV for the LVDS receiver. The
DS90LV048A supports an enhanced threshold region of −100mV to 0V. This is useful for fail-safe biasing. The
threshold region is shown in the Voltage Transfer Curve (VTC) in Figure 6. The typical DS90LV048A LVDS
receiver switches at about −35mV. Note that with VID = 0V, the output will be in a HIGH state. With an external
fail-safe bias of +25mV applied, the typical differential noise margin is now the difference from the switch point to
the bias point. In the example below, this would be 60mV of Differential Noise Margin (+25mV − (−35mV)). With
the enhanced threshold region of −100mV to 0V, this small external fail-safe biasing of +25mV (with respect to
0V) gives a DNM of a comfortable 60mV. With the standard threshold region of ±100mV, the external fail-safe
biasing would need to be +25mV with respect to +100mV or +125mV, giving a DNM of 160mV which is stronger
fail-safe biasing than is necessary for the DS90LV048A. If more DNM is required, then a stronger fail-safe bias
point can be set by changing resistor values.
8
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Figure 6. VTC of the DS90LV048A LVDS Receiver
Fail-Safe Feature
The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS
logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from
appearing as a valid signal.
The receiver's internal fail-safe circuitry is designed to source/sink a small amount of current, providing fail-safe
protection (a stable known state of HIGH output voltage) for floating, terminated or shorted receiver inputs.
1. Open Input Pins. The DS90LV048A is a quad receiver device, and if an application requires only 1, 2 or 3
receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or
any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output
to a HIGH state. This internal circuitry will ensure a HIGH, stable output state for open inputs.
2. Terminated Input. If the driver is disconnected (cable unplugged), or if the driver is in a TRI-STATE or
power-off condition, the receiver output will again be in a HIGH state, even with the end of cable 100Ω
termination resistor across the input pins. The unplugged cable can become a floating antenna which can
pick up noise. If the cable picks up more than 10mV of differential noise, the receiver may see the noise as a
valid signal and switch. To insure that any noise is seen as common-mode and not differential, a balanced
interconnect should be used. Twisted pair cable will offer better balance than flat ribbon cable.
3. Shorted Inputs. If a fault condition occurs that shorts the receiver inputs together, thus resulting in a 0V
differential input voltage, the receiver output will remain in a HIGH state. Shorted input fail-safe is not
supported across the common-mode range of the device (GND to 2.4V). It is only supported with inputs
shorted and no external common-mode voltage applied.
External lower value pull up and pull down resistors (for a stronger bias) may be used to boost fail-safe in the
presence of higher noise levels. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to
minimize loading and waveform distortion to the driver. The common-mode bias point should be set to
approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry.
Additional information on fail-safe biasing of LVDS devices may be found in AN-1194.
PIN DESCRIPTIONS
Pin No.
Name
2, 3, 6, 7
RIN+
Non-inverting receiver input pin
Description
1, 4, 5, 8
RIN−
Inverting receiver input pin
10, 11, 14, 15
ROUT
Receiver output pin
16
EN
Receiver enable pin: When EN is low, the receiver is disabled. When EN is high and
EN* is low or open, the receiver is enabled. If both EN and EN* are open circuit,
then the receiver is disabled.
9
EN*
Receiver enable pin: When EN* is high, the receiver is disabled. When EN* is low or
open and EN is high, the receiver is enabled. If both EN and EN* are open circuit,
then the receiver is disabled.
13
VCC
Power supply pin, +3.3V ± 0.3V
12
GND
Ground pin
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TYPICAL PERFORMANCE CURVES
10
Output High Voltage vs
Power Supply Voltage
Output Low Voltage vs
Power Supply Voltage
Output Short Circuit Current vs
Power Supply Voltage
Output TRI-STATE Current vs
Power Supply Voltage
Differential Transition Voltage vs
Power Supply Voltage
Power Supply Current
vs Frequency
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TYPICAL PERFORMANCE CURVES (continued)
Power Supply Current vs
Ambient Temperature
Differential Propagation Delay vs
Power Supply Voltage
Differential Propagation Delay vs
Ambient Temperature
Differential Propagation Delay vs
Differential Input Voltage
Differential Propagation Delay
vs
Common-Mode Voltage
Differential Skew vs
Power Supply Voltage
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TYPICAL PERFORMANCE CURVES (continued)
Differential Skew vs
Ambient Temperature
Transition Time vs
Power Supply Voltage
Transition Time vs
Ambient Temperature
12
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REVISION HISTORY
Changes from Revision A (April 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 12
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PACKAGE OPTION ADDENDUM
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1-Nov-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DS90LV048ATM
NRND
SOIC
D
16
48
TBD
Call TI
Call TI
-40 to 85
DS90LV048A
TM
DS90LV048ATM/NOPB
ACTIVE
SOIC
D
16
48
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS90LV048A
TM
DS90LV048ATMTC
NRND
TSSOP
PW
16
92
TBD
Call TI
Call TI
-40 to 85
DS90LV
048AT
DS90LV048ATMTC/NOPB
ACTIVE
TSSOP
PW
16
92
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS90LV
048AT
DS90LV048ATMTCX
NRND
TSSOP
PW
16
2500
TBD
Call TI
Call TI
-40 to 85
DS90LV
048AT
DS90LV048ATMTCX/NOPB
ACTIVE
TSSOP
PW
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS90LV
048AT
DS90LV048ATMX/NOPB
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
DS90LV048A
TM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Nov-2013
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DS90LV048ATMTCX
TSSOP
PW
16
2500
330.0
12.4
6.95
8.3
1.6
8.0
12.0
Q1
DS90LV048ATMX/NOPB
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.3
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DS90LV048ATMTCX
TSSOP
PW
16
2500
367.0
367.0
35.0
DS90LV048ATMX/NOPB
SOIC
D
16
2500
367.0
367.0
35.0
Pack Materials-Page 2
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