LINER LTC2324-16 Quad, 16-bit, 5msps/ch simultaneous sampling adc Datasheet

LTC2325-16
Quad, 16-Bit, 5Msps/Ch
Simultaneous Sampling ADC
FEATURES
DESCRIPTION
5Msps/Ch Throughput Rate
nn Four Simultaneously Sampling Channels
nn Guaranteed 16-Bit, No Missing Codes
nn 8V
P-P Differential Inputs with Wide Input
Common Mode Range
nn 82dB SNR (Typ) at f = 2.2MHz
IN
nn –88dB THD (Typ) at f = 2.2MHz
IN
nn Guaranteed Operation to 125°C
nn Single 3.3V or 5V Supply
nn Low Drift (20ppm/°C Max) 2.048V or 4.096V
Internal Reference
nn 1.8V to 2.5V I/O Voltages
nn CMOS or LVDS SPI-Compatible Serial I/O
nn Power Dissipation 40mW/Ch (Typ)
nn Small 52-Pin (7mm × 8mm) QFN Package
The LTC®2325-16 is a low noise, high speed quad 16‑bit
successive approximation register (SAR) ADC with
differential inputs and wide input common mode range.
Operating from a single 3.3V or 5V supply, the LTC2325-16
has an 8VP-P differential input range, making it ideal for
applications which require a wide dynamic range with high
common mode rejection. The LTC2325-16 achieves ±2LSB
INL typical, no missing codes at 16 bits and 82dB SNR.
nn
The LTC2325-16 has an onboard low drift (20ppm/°C max)
2.048V or 4.096V temperature-compensated reference.
The LTC2325-16 also has a high speed SPI-compatible
serial interface that supports CMOS or LVDS. The fast
5Msps per channel throughput with one cycle latency
makes the LTC2325-16 ideally suited for a wide variety
of high speed applications. The LTC2325-16 dissipates
only 40mW per channel and offers nap and sleep modes
to reduce the power consumption to 90μW for further
power savings during inactive periods.
APPLICATIONS
High Speed Data Acquisition Systems
Communications
nn Optical Networking
nn Multiphase Motor Control
nn
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners.
nn
TYPICAL APPLICATION
TRUE DIFFERENTIAL INPUTS
NO CONFIGURATION REQUIRED
VDD
ARBITRARY
0V
3.3V OR 5V
1.8V TO 2.5V
0
+, IN –
VDD
VDD
DIFFERENTIAL
0V
GND
AIN1+
S/H
AIN1–
16-BIT
SAR ADC
AIN2+
S/H
AIN2–
16-BIT
SAR ADC
LTC2325-16
VDD
0V
BIPOLAR
32k Point FFT fSMPL = 5Msps,
fIN = 2.2MHz
1µF
VDD
UNIPOLAR
0V
AIN3+
S/H
AIN3–
16-BIT
SAR ADC
AIN4+
S/H
AIN4–
16-BIT
SAR ADC
REF
FOUR SIMULTANEOUS
SAMPLING CHANNELS
GND
OVDD
CMOS/LVDS
SDR/DDR
REFBUFEN
SDO1
SDO2
SDO3
SDO4
CLKOUT
SCK
CNV
SAMPLE
CLOCK
REFOUT1 REFOUT2 REFOUT3 REFOUT4
1µF
10µF
10µF
10µF
SNR = 82.1dB
THD = –88.1dB
SINAD = 81.5dB
SFDR = 90.2dB
–20
AMPLITUDE (dBFS)
IN
10µF
10µF
232516 TA01a
–40
–60
–80
–100
–120
–140
0
0.5
1
1.5
FREQUENCY (MHz)
2
2.5
232516 TA01b
232516fa
For more information www.linear.com/LTC2325-16
1
LTC2325-16
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
SCK/SCK+
DNC/SCK–
REFBUFEN
VDD
REFOUT4
GND
NC
NC
GND
NC
NC
VDD
TOP VIEW
52 51 50 49 48 47 46 45 44 43 42 41
AIN4– 1
40 DNC/SDOD–
AIN4+ 2
39 SDO4/SDOD+
GND 3
38 GND
AIN3– 4
37 OVDD
AIN3+ 5
36 DNC/SDOC–
35 SDO3/SDOC+
REFOUT3 6
GND 7
34 CLKOUTEN/CLKOUT –
53
GND
REF 8
33 CLKOUT/CLKOUT+
32 GND
REFOUT2 9
AIN2– 10
31 OVDD
AIN2+ 11
30 DNC/SDOB–
GND 12
29 SDO2/SDOB+
AIN1– 13
28 DNC/SDOA–
AIN1+ 14
27 SDO1/SDOA+
GND
CMOS/LVDS
CNV
SDR/DDR
REFOUT1
VDD
NC
NC
GND
NC
NC
15 16 17 18 19 20 21 22 23 24 25 26
VDD
Supply Voltage (VDD)...................................................6V
Supply Voltage (OVDD).................................................3V
Analog Input Voltage
AIN+, AIN – (Note 3).................... –0.3V to (VDD + 0.3V)
REFOUT1,2,3,4........................ .–0.3V to (VDD + 0.3V)
CNV........................................ –0.3V to (OVDD + 0.3V)
Digital Input Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Digital Output Voltage
(Note 3)........................... (GND – 0.3V) to (OVDD + 0.3V)
Operating Temperature Range
LTC2325C................................................. 0°C to 70°C
LTC2325I..............................................–40°C to 85°C
LTC2325H........................................... –40°C to 125°C
Storage Temperature Range................... –65°C to 150°C
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
TJMAX = 150°C, θJA = 29°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
http://www.linear.com/product/LTC2325-16#orderinfo
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC2325CUKG-16#PBF
LTC2325CUKG-16#TRPBF
2325UKG-16
52-Lead (7mm × 8mm) Plastic QFN
0°C to 70°C
LTC2325IUKG-16#PBF
LTC2325IUKG-16#TRPBF
2325UKG-16
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
LTC2325HUKG-16#PBF
LTC2325HUKG-16#TRPBF
2325UKG-16
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
2
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
VIN+
VIN–
VIN+ – VIN–
VCM
IIN
CIN
CMRR
VIHCNV
VILCNV
IINCNV
Absolute Input Range (AIN+ to AIN–)
Absolute Input Range (AIN+ to AIN–)
Input Differential Voltage Range
Common Mode Input Range
Analog Input DC Leakage Current
Analog Input Capacitance
Input Common Mode Rejection Ratio
CNV High Level Input Voltage
CNV Low Level Input Voltage
CNV Input Current
(Note 5)
(Note 5)
VIN = VIN+ – VIN–
VCM = (VIN+ – VIN–)/2
MIN
l
l
l
l
l
TYP
0
0
–REFOUT1,2,3,4
0
–1
MAX
UNITS
VDD
VDD
REFOUT1,2,3,4
VDD
1
V
V
V
V
μA
pF
dB
V
V
μA
10
102
fIN = 2.2MHz
l
1.5
0.5
10
l
l
–10
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
INL
DNL
BZE
FSE
Resolution
No Missing Codes
Transition Noise
Integral Linearity Error
Differential Linearity Error
Bipolar Zero-Scale Error
Bipolar Zero-Scale Error Drift
Bipolar Full-Scale Error
Bipolar Full-Scale Error Drift
CONDITIONS
MIN
l
l
(Note 6)
(Note 7)
l
VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded) (Note 7)
VREFOUT1,2,3,4 = 4.096V (REFBUFEN Grounded)
l
–30
l
MAX
UNITS
16
16
–9
–0.99
–12
l
TYP
Bits
Bits
1.5
±2
±0.4
0
0.01
9
0.99
12
30
15
LSBRMS
LSB
LSB
LSB
LSB/°C
LSB
ppm/°C
DYNAMIC ACCURACY
The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C and AIN = –1dBFS (Notes 4, 8).
SYMBOL PARAMETER
SINAD
SNR
THD
SFDR
CONDITIONS
Signal-to-(Noise + Distortion) Ratio fIN = 2.2MHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference
fIN = 2.2MHz, VREFOUT1,2,3,4 = 5V, External Reference
Signal-to-Noise Ratio
fIN = 2.2MHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference
fIN = 2.2MHz, VREFOUT1,2,3,4 = 5V, External Reference
Total Harmonic Distortion
fIN = 2.2MHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference
fIN = 2.2MHz, VREFOUT1,2,3,4 = 5V, External Reference
Spurious Free Dynamic Range
fIN = 2.2MHz, VREFOUT1,2,3,4 = 4.096V, Internal Reference
fIN = 2.2MHz, VREFOUT1,2,3,4 = 5V, External Reference
–3dB Input Bandwidth
Aperture Delay
Aperture Delay Matching
Aperture Jitter
Transient Response
Full-Scale Step
MIN
TYP
l
76
l
77.5
81
81
82
82.5
–90
–91
93
93
95
500
500
1
3
l
l
78
MAX
–80
UNITS
dB
dB
dB
dB
dB
dB
dB
dB
MHz
ps
ps
psRMS
ns
232516fa
For more information www.linear.com/LTC2325-16
3
LTC2325-16
INTERNAL REFERENCE CHARACTERISTICS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
VREFOUT1,2,3,4
Internal Reference Output Voltage
4.75V < VDD < 5.25V
3.13V < VDD < 3.47V
l
l
VREF Temperature Coefficient
(Note 14)
l
MIN
TYP
MAX
UNITS
4.078
2.034
4.096
2.048
4.115
2.064
V
V
3
20
REFOUT1,2,3,4 Output Impedance
IREFOUT1,2,3,4
ppm/°C
0.25
Ω
VREFOUT1,2,3,4 Line Regulation
4.75V < VDD < 5.25V
0.3
mV/V
External Reference Current
REFBUFEN = 0V
REFOUT1,2,3,4 = 4.096V
REFOUT1,2,3,4 = 2.048V
(Notes 9, 10)
385
204
μA
μA
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL PARAMETER
CMOS Digital Inputs and Outputs
CONDITIONS
MIN
TYP
MAX
UNITS
CMOS/LVDS = GND
VIH
High Level Input Voltage
l
VIL
Low Level Input Voltage
l
IIN
Digital Input Current
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
IO = –500μA
l
VOL
Low Level Output Voltage
IO = 500μA
l
IOZ
Hi-Z Output Leakage Current
VOUT = 0V to OVDD
l
ISOURCE
Output Source Current
VOUT = 0V
–10
mA
ISINK
Output Sink Current
VOUT = OVDD
10
mA
LVDS Digital Inputs and Outputs
VIN = 0V to OVDD
l
0.8 • OVDD
V
–10
0.2 • OVDD
V
10
μA
5
pF
OVDD – 0.2
V
–10
0.2
V
10
μA
CMOS/LVDS = OVDD
VID
LVDS Differential Input Voltage
100Ω Differential Termination
OVDD = 2.5V
l
240
600
mV
VIS
LVDS Common Mode Input Voltage
100Ω Differential Termination
OVDD = 2.5V
l
1
1.45
V
VOD
LVDS Differential Output Voltage
100Ω Differential Termination
OVDD = 2.5V
l
220
350
600
mV
VOS
LVDS Common Mode Output Voltage
100Ω Differential Termination
OVDD = 2.5V
l
0.85
1.2
1.4
V
VOD_LP
Low Power LVDS Differential Output
Voltage
100Ω Differential Termination
OVDD = 2.5V
l
100
200
350
mV
VOS_LP
Low Power LVDS Common Mode Output
Voltage
100Ω Differential Termination
OVDD = 2.5V
l
0.85
1.2
1.4
V
4
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
VDD
Supply Voltage
5V Operation
3.3V Operation
l
l
IVDD
Supply Current
5Msps Sample Rate (IN+ = IN– = 0V)
l
CMOS I/O Mode
MIN
4.75
3.13
31
MAX
UNITS
5.25
3.47
V
V
44.5
mA
2.63
V
CMOS/LVDS = GND
OVDD
Supply Voltage
IOVDD
Supply Current
5Msps Sample Rate (CL = 5pF)
INAP
Nap Mode Current
ISLEEP
Sleep Mode Current
PD_3.3V
PD_5V
LVDS I/O Mode
TYP
l
1.71
l
4.4
15.5
mA
Conversion Done (IVDD)
l
5.3
6.4
mA
Sleep Mode (IVDD+ IOVDD)
l
20
90
µA
Power Dissipation
VDD = 3.3V, 5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
102
18
20
181
21.1
28.8
mW
mW
µW
Power Dissipation
VDD = 5V, 5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
162
27
90
261
32
424
mW
mW
µW
2.63
V
CMOS/LVDS = OVDD, OVDD = 2.5V
OVDD
Supply Voltage
IOVDD
Supply Current
5Msps Sample Rate (CL = 5pF, RL = 100Ω)
l
26
31.5
mA
INAP
Nap Mode Current
Conversion Done (IVDD)
l
5.3
6.4
mA
ISLEEP
Sleep Mode Current
Sleep Mode (IVDD + IOVDD)
l
20
90
µA
PD_3.3V
Power Dissipation
VDD = 3.3V, 5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
151
52
80
218
58.6
288
mW
mW
µW
PD_5V
Power Dissipation
VDD = 5V, 5Msps Sample Rate
Nap Mode
Sleep Mode
l
l
l
214
91
90
301
69.2
424
mW
mW
µW
l
2.37
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
fSMPL
Maximum Sampling Frequency
CONDITIONS
MIN
TYP
tCYC
Time Between Conversions
tCONV
Conversion Time
l
tCNVH
CNV High Time
l
tACQUISITION
Sampling Aperture
(Note 11) tACQUISITION = tCYC – tCONV
28
ns
tWAKE
REFOUT1,2,3,4 Wake-Up Time
CREFOUT1,2,3,4 = 10µF
50
ms
l
(Note 11) tCYC = tCNVH + tCONV
l
0.2
MAX
UNITS
5
Msps
1000
µs
170
ns
30
ns
CMOS I/O Mode, SDR, CMOS/LVDS = GND, SDR/ DDR = GND
tSCK
SCK Period
tSCKH
SCK High Time
(Note 13)
tSCKL
SCK Low Time
tHSDO_SDR
SDO Data Remains Valid Delay from CLKOUT↓
CL = 5pF (Note 12)
tDSCKCLKOUT
SCK to CLKOUT Delay
(Note 12)
l
9.1
ns
l
4.1
ns
l
4.1
l
0
1.5
ns
l
2
4.5
ns
ns
232516fa
For more information www.linear.com/LTC2325-16
5
LTC2325-16
ADC TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 4).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tDCNVSDOZ
Bus Relinquish Time After CNV↑
(Note 11)
l
tDCNVSDOV
SDO Valid Delay from CNV↓
(Note 11)
l
3
ns
3
ns
tDSCKHCNVH
SCK Delay Time to CNV↑
(Note 11)
l
0
ns
CMOS I/O Mode, DDR, CMOS/LVDS = GND, SDR/ DDR = OVDD
tSCK
SCK Period
l
18.2
ns
tSCKH
SCK High Time
l
8.2
ns
tSCKL
SCK Low Time
l
8.2
ns
tHSDO_DDR
SDO Data Remains Valid Delay from CLKOUT↓
CL = 5pF (Note 12)
l
0
1.5
ns
tDSCKCLKOUT
SCK to CLKOUT Delay
(Note 12)
l
2
4.5
ns
tDCNVSDOZ
Bus Relinquish Time After CNV↑
(Note 11)
l
3
ns
tDCNVSDOV
SDO Valid Delay from CNV↓
(Note 11)
l
3
ns
tDSCKHCNVH
SCK Delay Time to CNV↑
(Note 11)
l
0
ns
LVDS I/O Mode, SDR, CMOS/LVDS = OVDD, SDR/DDR = GND
tSCK
SCK Period
l
9.1
ns
tSCKH
SCK High Time
l
4.1
ns
tSCKL
SCK Low Time
l
4.1
tHSDO_SDR
SDO Data Remains Valid Delay from CLKOUT↓
CL = 5pF OVDD = 2.5V
l
0
1.5
ns
tDSCKCLKOUT
SCK to CLKOUT Delay
OVDD = 2.5V
l
2
4
ns
tDSCKHCNVH
SCK Delay Time to CNV↑
(Note 11)
l
0
ns
ns
LVDS I/O Mode, DDR, CMOS/LVDS = OVDD, SDR/DDR = OVDD
tSCK
SCK Period
l
18.2
ns
tSCKH
SCK High Time
l
8.2
ns
tSCKL
SCK Low Time
l
8.2
ns
tHSDO_DDR
SDO Data Remains Valid Delay from CLKOUT↓
CL = 5pF OVDD = 2.5V
l
0
1.5
ns
tDSCKCLKOUT
SCK to CLKOUT Delay
OVDD = 2.5V
l
2
4
ns
tDSCKHCNVH
SCK Delay Time to CNV↑
(Note 11)
l
0
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When these pin voltages are taken below GND, or above VDD or
OVDD, they will be clamped by internal diodes. This product can handle input
currents up to 100mA below GND, or above VDD or OVDD, without latch-up.
Note 4: VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4 = 4.096V, fSMPL = 5MHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 0000 and 1111
1111 1111 1111. Full-scale bipolar error is the worst-case of –FS or +FS
6
ns
untrimmed deviation from ideal first and last code transitions and includes
the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±4.096V input
with REF = 4.096V.
Note 9: When REFOUT1,2,3,4 is overdriven, the internal reference buffer
must be turned off by setting REFBUFEN = 0V.
Note 10: fSMPL = 5MHz, IREFOUT1,2,3,4 varies proportionally with sample rate.
Note 11: Guaranteed by design, not subject to test.
Note 12: Parameter tested and guaranteed at OVDD = 1.71V and OVDD = 2.5V.
Note 13: tSCK of 9.1ns allows a shift clock frequency up to 105MHz for
rising edge capture.
Note 14: Temperature coefficient is calculated by dividing the maximum
change in output voltage by the specified temperature range.
Note 15: CNV is driven from a low jitter digital source, typically at OVDD
logic levels.
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
ADC TIMING CHARACTERISTICS
0.8 • OVDD
tWIDTH
0.2 • OVDD
tDELAY
tDELAY
0.8 • OVDD
0.8 • OVDD
0.2 • OVDD
0.2 • OVDD
50%
50%
232516 F01
Figure 1. Voltage Levels for Timing Specifications
232516fa
For more information www.linear.com/LTC2325-16
7
LTC2325-16
TYPICAL PERFORMANCE CHARACTERISTICS
= 4.096V, fSMPL = 5Msps, unless otherwise noted.
Integral Nonlinearity
vs Output Code
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4
Differential Nonlinearity
vs Output Code
8
DC Histogram
1.0
40000
32000
0.5
2
0
–2
–4
28000
COUNTS
DNL ERROR (LSB)
INL ERROR (LSB)
4
0
24000
20000
16000
12000
–0.5
8000
–6
4000
–8
–32768
–16384
0
16384
OUTPUT CODE
–1.0
–32768
32768
–16384
0
16384
OUTPUT CODE
232516 G01
–80
–100
–120
83.0
–80
82.8
–84
82.6
82.4
82.2
SNR
82.0
81.8
SINAD
81.6
81.4
81.2
0
0.5
1
1.5
FREQUENCY (MHz)
2
2.5
81.0
0
0.5
1
1.5
FREQUENCY (MHz)
2
–89
–92
HD3
–95
–98
–101
HD2
–104
–107
–110
1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3
INPUT COMMON MODE (V)
232516 G07
8
–96
HD3
–100
–104
HD2
–108
–112
–120
2.5
0
0.5
1
1.5
FREQUENCY (MHz)
2
84
f = 2.2MHz
83
82
81
80
79
78
77
76
75
74
73
72
71
70
0.5 1 1.5
2.5
232516 G06
32k Point FFT, IMD, fSMPL = 5Msps,
AIN+ = 1.2MHz, AIN– = 2.2MHz
0
SNR
THD = 86dB
VCM = 1MHz, 4Vpp
–20
SINAD
AMPLITUDE (dBFS)
THD
SNR, SINAD LEVEL (dBFS)
THD, HARMONICS LEVEL (dBFS)
–86
10
–92
SNR, SINAD vs Reference Voltage,
fIN = 2.2MHz
f = 2.2MHz
8
THD
–88
232516 G05
THD, Harmonics vs Input Common
Mode
–83
6
–116
232516 G04
–80
4
THD, Harmonics vs Input
Frequency (1kHz to 2.2MHz)
SNR, SINAD vs Input Frequency
(1kHz to 2.2MHz)
–60
0 2
CODE
232516 G03
THD, HARMONICS LEVEL (dBFS)
32k Point FFT, fSMPL = 5Msps,
fIN = 2.2MHz
SNR = 82.1dB
THD = –88.1dB
–20
SINAD = 81.5dB
SFDR = 90.2dB
–40
–140
0
–10 –8 –6 –4 –2
32768
232516 G02
SNR, SINAD LEVEL (dBFS)
AMPLITUDE (dBFS)
0
σ = 1.5
36000
6
–40
–60
–80
–100
–120
2
2.5
3 3.5
VREFOUT(V)
4
4.5
5
232516 G08
–140
0
0.5
1
1.5
FREQUENCY (MHz)
2
2.5
232516 G09
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
TYPICAL PERFORMANCE CHARACTERISTICS
= 4.096V, fSMPL = 5Msps, unless otherwise noted.
CMRR vs Input Frequency
120
Step Response
(Large Signal Settling)
Crosstalk vs Input Frequency
32768
–105
VCM = 4VP-P
–107
112
24576
–109
104
96
88
–111
OUTPUT CODE (LSB)
CROSSTALK (dB)
CMRR (dB)
TA = 25°C, VDD = 5V, OVDD = 2.5V, REFOUT1,2,3,4
–113
–115
–117
–119
16384
4.096V RANGE
8192
0
–121
IN+ = 5MHz SQUARE WAVE
IN– = 0V
–123
500
1000
1500
2000
FREQUENCY (kHz)
2500
–125
0
0.5
232516 G10
700
200
232516 G12
150
100
50
0
–50
–100
4.096V RANGE
IN+ = 5MHz
SQUARE WAVE
–200
IN– = 0V
–250
–20 –10 0 10 20 30 40 50 60 70 80 90
SETTLING TIME (ns)
–150
REF Output vs Temperature
1.00
REFBUFEN = 0V
(EXT REF BUF
OVERDRIVING REF BUF)
600
SUPPLY CURRENT (uA)
DEVIATION FROM FINAL VALUE (LSB)
–8192
–20 –10 0 10 20 30 40 50 60 70 80 90
SETTLING TIME (ns)
2.5
External Reference Supply
Current vs Sample Frequency
250
0.50
500
400
VREFOUT1,2,3,4 = 4.096V
300
200
VREFOUT1,2,3,4 = 2.048V
100
0
0
232516 G13
1
2
3
4
SAMPLE FREQUENCY (Msps)
VDD = 3.3V
0
–0.50
–1.00
VDD = 5V
–1.50
–2.00
–2.50
5
–3.00
–55 –35 –15
5 25 45 65 85 105 125
TEMPERATURE (°C)
232516 G14
232516 G15
Supply Current
vs Sample Frequency
Offset Error vs Temperature
3
8
40
OVDD Current vs SCK Frequency,
CLOAD = 10pF
SUPPLY CURRENT (mA)
1
0
–1
VDD = 5V
30
VDD = 3.3V
25
20
–2
5 25 45 65 85 105 125
TEMPERATURE (°C)
232516 G16
0
1
2
3
4
SAMPLE FREQUENCY (Msps)
5
232516 G17
28
6
26
5
24
CMOS(2.5V)
4
22
CMOS(1.8V)
3
20
18
2
16
1
15
30
LVDS
0
LOW POWER LVDS
0
22
44
66
88
SCK FREQUENCY (MHz)
OVDD CURRENT LVDS (mA)
35
32
FULL SCALE SINUSOIDAL INPUT
7
2
LSB
2
232516 G11
Step Response
(Fine Settling)
–3
–55 –35 –15
1
1.5
FREQUENCY (MHz)
REF OUTPUT ERROR (mV)
0
OVDD CURRENT CMOS (mA)
80
14
12
110
232516 G18
232516fa
For more information www.linear.com/LTC2325-16
9
LTC2325-16
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL I/O MODES
AIN4+, AIN4– (Pins 2, 1): Analog Differential Input Pins.
Full-scale range (AIN4+ – AIN4–) is ±REFOUT4 voltage.
These pins can be driven from VDD to GND.
GND (Pins 3, 7, 12, 18, 26, 32, 38, 46, 49): Ground.
These pins and exposed pad (Pin 53) must be tied directly
to a solid ground plane.
AIN3+, AIN3– (Pins 5, 4): Analog Differential Input Pins.
Full-scale range (AIN3+ – AIN3–) is ±REFOUT3 voltage.
These pins can be driven from VDD to GND.
REFOUT3 (Pin 6): Reference Buffer 3 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
REF (Pin 8): Common 4.096V reference output. Decouple
to GND with a 1μF low ESR ceramic capacitor. May be
overdriven with a single external reference to establish a
common reference for ADC cores 1 through 4.
REFOUT2 (Pin 9): Reference Buffer 2 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
AIN2+, AIN2– (Pins 11, 10): Analog Differential Input Pins.
Full-scale range (AIN2+ – AIN2–) is ±REFOUT2 voltage.
These pins can be driven from VDD to GND.
AIN1+, AIN1– (Pins 14, 13): Analog Differential Input Pins.
Full-scale range (AIN1+ – AIN1–) is ±REFOUT1 voltage.
These pins can be driven from VDD to GND.
VDD (Pins 15, 21, 44, 52): Power Supply. Bypass VDD to
GND with a 10µF ceramic capacitor and a 0.1µF ceramic
capacitor close to the part. The VDD pins should be shorted
together and driven from the same supply.
10
REFOUT1 (Pin 22): Reference Buffer 1 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
SDR/DDR (Pin 23): Double Data Rate Input. Controls the
frequency of SCK and CLKOUT. Tie to GND for the falling
edge of SCK to shift each serial data output (Single Data
Rate, SDR). Tie to OVDD to shift serial data output on each
edge of SCK (Double Data Rate, DDR). CLKOUT will be a
delayed version of SCK for both pin states.
CNV (Pin 24): Convert Input. This pin, when high, defines
the acquisition phase. When this pin is driven low, the
conversion phase is initiated and output data is clocked
out. This input must be driven at OVDD levels with a low
jitter pulse. This pin is unaffected by the CMOS/LVDS pin.
CMOS/LVDS (Pin 25): I/O Mode Select. Ground this pin
to enable CMOS mode, tie to OVDD to enable LVDS mode.
Float this pin to enable low power LVDS mode.
OVDD (Pins 31, 37): I/O Interface Digital Power. The range
of OVDD is 1.71V to 2.63V. This supply is nominally set
to the same supply as the host interface (CMOS: 1.8V or
2.5V, LVDS: 2.5V). Bypass OVDD to GND (Pins 32 and 38)
with 0.1µF capacitors.
REFBUFEN (Pin 43): Reference Buffer Output Enable. Tie
to VDD when using the internal reference. Tie to ground
to disable the internal REFOUT1–4 buffers for use with
external voltage references. This pin has a 500k internal
pull-up to VDD.
REFOUT4 (Pin 45): Reference Buffer 4 Output. An onboard
buffer nominally outputs 4.096V to this pin. This pin is
referred to GND and should be decoupled closely to the
pin with a 10µF (X5R, 0805 size) ceramic capacitor. The
internal buffer driving this pin may be disabled by grounding the REFBUFEN pin. If the buffer is disabled, an external
reference may drive this pin in the range of 1.25V to 5V.
Exposed Pad (Pin 53): Ground. Solder this pad to ground.
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
PIN FUNCTIONS
CMOS DATA OUTPUT OPTION (CMOS/LVDS = LOW)
SDO1 (Pin 27): CMOS Serial Data Output for ADC Channel
1. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 16-bit conversion
data to be read from SDO1 in SDR mode, 8 SCK edges
in DDR mode.
SDO2 (Pin 29): CMOS Serial Data Output for ADC Channel
2. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 16-bit conversion
data to be read from SDO2 in SDR mode, 8 SCK edges
in DDR mode.
SDO3 (Pin 35): CMOS Serial Data Output for ADC Channel
3. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 16-bit conversion
data to be read from SDO3 in SDR mode, 8 SCK edges
in DDR mode.
SDO4 (Pin 39): CMOS Serial Data Output for ADC Channel
4. The conversion result is shifted MSB first on each falling edge of SCK in SDR mode and each SCK edge in DDR
mode. 16 SCK edges are required for 16-bit conversion
data to be read from SDO4 in SDR mode, 8 SCK edges
in DDR mode.
CLKOUT (Pin 33): Serial Data Clock Output. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver (FPGA). The logic level is determined by
OVDD. This pin echoes the input at SCK with a small delay.
CLKOUTEN (Pin 34): CLKOUT can be disabled by tying
Pin 34 to OVDD for a small power savings. If CLKOUT is
used, ground this pin.
SCK (Pin 41): Serial Data Clock Input. The falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins in SDR mode (DDR = LOW). In DDR mode
(SDR/DDR = HIGH) each edge of this clock shifts the
conversion result MSB first onto the SDO pins. The logic
level is determined by OVDD.
DNC (Pin 28, 30, 36, 40, 42): In CMOS mode, do not
connect this pin.
LVDS DATA OUTPUT OPTION (CMOS/LVDS = HIGH OR
FLOAT)
SDOA+, SDOA– (Pins 27, 28): LVDS Serial Data Output
for ADC Channel 1. The conversion result is shifted CH1
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 16 SCK edges are required
for 16-bit conversion data to be read from SDOA in SDR
mode, 8 SCK edges in DDR mode. Terminate with a 100Ω
resistor at the receiver (FPGA).
SDOB+, SDOB– (Pins 29, 30): LVDS Serial Data Output
for ADC Channel 2. The conversion result is shifted CH2
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 16 SCK edges are required
for 16-bit conversion data to be read from SDOB in SDR
mode, 8 SCK edges in DDR mode. Terminate with a 100Ω
resistor at the receiver (FPGA).
CLKOUT+, CLKOUT– (Pins 33, 34): Serial Data Clock Output.
CLKOUT provides a skew-matched clock to latch the SDO
output at the receiver. These pins echo the input at SCK with
a small delay. These pins must be differentially terminated
by an external 100Ω resistor at the receiver (FPGA).
SDOC+, SDOC– (Pins 35, 36): LVDS Serial Data Output
for ADC channel 3. The conversion result is shifted CH3
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 16 SCK edges are required
for 16-bit conversion data to be read from SDOA in SDR
mode, 8 SCK edges in DDR mode. Terminate with a 100Ω
resistor at the receiver (FPGA).
SDOD+, SDOD– (Pins 39, 40): LVDS Serial Data Output
for ADC Channel 4. The conversion result is shifted CH4
MSB first on each falling edge of SCK in SDR mode and
each SCK edge in DDR mode. 16 SCK edges are required
for 16-bit conversion data to be read from SDOA in SDR
mode, 8 SCK edges in DDR mode. Terminate with a 100Ω
resistor at the receiver (FPGA).
SCK+, SCK– (Pins 41, 42): Serial Data Clock Input. The
falling edge of this clock shifts the conversion result MSB
first onto the SDO pins in SDR mode (SDR/DDR = LOW).
In DDR mode (SDR/DDR = HIGH) each edge of this clock
shifts the conversion result MSB first onto the SDO pins.
These pins must be differentially terminated by an external
100Ω resistor at the receiver (ADC).
232516fa
For more information www.linear.com/LTC2325-16
11
LTC2325-16
FUNCTIONAL BLOCK DIAGRAM
CMOS IO Mode
VDD
(15, 21, 44, 52)
24 CNV
14
13
AIN1+
+
S/H
–
AIN1–
16-BIT
SAR ADC
REF
11
10
AIN2+
42
SCK
DNC
SDO1
DNC
REFOUT1
SDO2
16-BIT
SAR ADC
REF
41
CMOS
I/O
×1
+
S/H
–
AIN2–
GND
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
CMOS
I/O
DNC
REFOUT2
×1
OUTPUT
CLOCK DRIVER
CMOS
RECEIVERS
CLKOUT
CLKOUTEN
SDR/DDR
5
4
AIN3+
+
S/H
–
AIN3–
16-BIT
SAR ADC
REF
2
1
AIN4+
16-BIT
SAR ADC
REF
8
REF
250μA
×1.7
×3.4
SDO3
DNC
REFOUT3
×1
+
S/H
–
AIN4–
CMOS
I/O
CMOS
I/O
×1
1.2V INT REF
SDO4
DNC
REFOUT4
27
28
22
29
30
9
33
34
23
35
36
6
39
40
45
OVDD (31, 37)
REFBUFEN 43
CMOS/LVDS 25
232516 BDa
12
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
FUNCTIONAL BLOCK DIAGRAM
LVDS IO Mode
VDD
(15, 21, 44, 52)
24 CNV
14
13
AIN1+
+
S/H
–
AIN1–
16-BIT
SAR ADC
REF
11
10
AIN2+
41
42
SCK+
SCK–
SDOA+
SDOA–
REFOUT1
16-BIT
SAR ADC
REF
LVDS
I/O
×1
+
S/H
–
AIN2–
GND
(3, 7, 12, 18, 26, 32, 38, 46, 49, 53)
LVDS
I/O
SDOB+
SDOB–
REFOUT2
×1
OUTPUT
CLOCK DRIVER
LVDS
RECEIVERS
CLKOUT+
CLKOUT–
27
28
22
29
30
9
33
34
SDR/DDR 23
5
4
AIN3+
+
S/H
–
AIN3–
16-BIT
SAR ADC
REF
2
1
AIN4+
16-BIT
SAR ADC
REF
8
REF
250μA
×1.7
×3.4
SDOC+
SDOC–
REFOUT3
×1
+
S/H
–
AIN4–
LVDS
I/O
LVDS
I/O
×1
1.2V INT REF
SDOD+
SDOD–
REFOUT4
35
36
6
39
40
45
OVDD (31, 37)
REFBUFEN 43
CMOS/LVDS 25
232516 BDb
232516fa
For more information www.linear.com/LTC2325-16
13
LTC2325-16
TIMING DIAGRAM
SDR Mode, CMOS
SAMPLE N
SAMPLE N+1
CNV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
CLKOUT
SDO1
Hi-Z
Hi-Z
Hi-Z
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
Hi-Z
D0
SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1
SDO4
Hi-Z
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
Hi-Z
D0
SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4
ACQUIRE
CONVERSION AND READOUT
232516 TD01
DDR Mode, CMOS
SAMPLE N
SAMPLE N+1
CNV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
CLKOUT
SDO1
Hi-Z
Hi-Z
Hi-Z
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1
SDO4
Hi-Z
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Hi-Z
SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4
ACQUIRE
14
CONVERSION AND READOUT
232516 TD02
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
TIMING DIAGRAM
SDR Mode, LVDS
SAMPLE N
SAMPLE N+1
CNV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCK
CLKOUT
SDOA
D15 D14 D13 D12 D11 D10 D9
SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1
SDOD
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4
ACQUIRE
CONVERSION AND READOUT
232516 TD03
DDR Mode, LVDS
SAMPLE N
SAMPLE N+1
CNV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK
CLKOUT
SDOA
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH1
SDOD
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SERIAL DATA BITS D[15:0] CORRESPOND TO PREVIOUS CONVERSION OF CH4
ACQUIRE
CONVERSION AND READOUT
232516 TD04
232516fa
For more information www.linear.com/LTC2325-16
15
LTC2325-16
APPLICATIONS INFORMATION
OVERVIEW
The LTC2325-16 is a low noise, high speed 16-bit successive approximation register (SAR) ADC with differential
inputs and a wide input common mode range. Operating
from a single 3.3V or 5V supply, the LTC2325-16 has a
4VP-P or 8VP-P differential input range, making it ideal for
applications which require a wide dynamic range. The
LTC2325-16 achieves ±2LSB INL typical, no missing codes
at 16 bits and 82dB SNR.
The LTC2325-16 has an onboard reference buffer and low
drift (20ppm/°C max) 4.096V temperature-compensated
reference. The LTC2325-16 also has a high speed SPIcompatible serial interface that supports CMOS or LVDS.
The fast 5Msps per channel throughput with one-cycle
latency makes the LTC2325-16 ideally suited for a wide
variety of high speed applications. The LTC2325-16 dissipates only 40mW per channel. Nap and sleep modes
are also provided to reduce the power consumption
of the LTC2325-16 during inactive periods for further
power savings.
CONVERTER OPERATION
The LTC2325-16 operates in two phases. During the acquisition phase, the sample capacitor is connected to the
analog input pins AIN+ and AIN – to sample the differential
analog input voltage, as shown in Figure 3. A falling edge on
the CNV pin initiates a conversion. During the conversion
phase, the 16-bit CDAC is sequenced through a successive
approximation algorithm effectively comparing the sampled
input with binary-weighted fractions of the reference voltage (e.g., VREFOUT/2, VREFOUT/4 … VREFOUT/32768) using
a differential comparator. At the end of conversion, a CDAC
output approximates the sampled analog input. The ADC
control logic then prepares the 16-bit digital output code
for serial transfer.
TRANSFER FUNCTION
The LTC2325-16 digitizes the full-scale voltage of 2 ×
REFOUT1,2,3,4 into 216 levels, resulting in an LSB size of
125µV with REF = 4.096V. The ideal transfer function is
shown in Figure 2. The output data is in 2’s complement
format.
Analog Input
The differential inputs of the LTC2325-16 provide great
flexibility to convert a wide variety of analog signals with
no configuration required. The LTC2325-16 digitizes the
difference voltage between the AIN+ and AIN – pins while
supporting a wide common mode input range. The analog
input signals can have an arbitrary relationship to each
other, provided that they remain between VDD and GND.
The LTC2325-16 can also digitize more limited classes of
analog input signals such as pseudo-differential unipolar/
bipolar and fully differential with no configuration required.
The analog inputs of the LTC2325-16 can be modeled
by the equivalent circuit shown in Figure 3. The backto-back diodes at the inputs form clamps that provide
ESD protection. In the acquisition phase, 10pF (CIN)
OUTPUT CODE (TWO’S COMPLEMENT)
VDD
011...111
RON
15Ω
011...110
AIN+
CIN
10pF
000...001
000...000
111...111
FSR = +FS – –FS
1LSB = FSR/65535
100...001
100...000
–FSR/2
–1 0 1
LSB
LSB
INPUT VOLTAGE (V)
AIN–
RON
15Ω
CIN
10pF
232516 F03
+FSR/2 – 1LSB
232516 F02
Figure 2. LTC2325-16 Transfer Function
16
BIAS
VOLTAGE
VDD
Figure 3. The Equivalent Circuit for the Differential
Analog Input of the LTC2325-16
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
APPLICATIONS INFORMATION
from the sampling capacitor in series with approximately
15Ω (RON) from the on-resistance of the sampling switch
is connected to the input. Any unwanted signal that is
common to both inputs will be reduced by the common
mode rejection of the ADC sampler. The inputs of the
ADC core draw a small current spike while charging the
CIN capacitors during acquisition.
mode input range relaxes the accuracy requirements of
any signal conditioning circuits prior to the analog inputs.
Pseudo-Differential Bipolar Input Range
The pseudo-differential bipolar configuration represents
driving one of the analog inputs at a fixed voltage, typically
VREF /2, and applying a signal to the other AIN pin. In this
case the analog input swings symmetrically around the
fixed input yielding bipolar two’s complement output codes
with an ADC span of half of full-scale. This configuration
is illustrated in Figure 4, and the corresponding transfer
function in Figure 5. The fixed analog input pin need not
be set at VREF /2, but at some point within the VDD rails
allowing the alternate input to swing symmetrically around
this voltage. If the input signal (AIN+ – AIN –) swings beyond
±REFOUT1,2,3,4/2, valid codes will be generated by the
ADC and must be clamped by the user, if necessary.
Single-Ended Signals
Single-ended signals can be directly digitized by the
LTC2325-16. These signals should be sensed pseudodifferentially for improved common mode rejection. By
connecting the reference signal (e.g., ground sense) of
the main analog signal to the other AIN pin, any noise or
disturbance common to the two signals will be rejected
by the high CMRR of the ADC. The LTC2325-16 flexibility
handles both pseudo-differential unipolar and bipolar
signals, with no configuration required. The wide common
VREF
VREF
LT1819
+
–
0V
LTC2325-16
25Ω
0V
AIN1+
REFOUT1
VREF
REF
220pF
10k
VREF /2
10k
1µF
+
–
25Ω
VREF /2
AIN1–
SDO1
CLKOUT
SCK
ONLY CHANNEL 1 SHOWN FOR CLARITY
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232516 F04
Figure 4. Pseudo-Differential Bipolar Application Circuit
ADC CODE
(2’s COMPLEMENT)
32767
16384
–VREF
–VREF /2
–16385
–32768
0
VREF /2
VREF
AIN
(AIN+ – AIN–)
DOTTED REGIONS AVAILABLE
232516 F05
Figure 5. Pseudo-Differential Bipolar Transfer Function
For more information www.linear.com/LTC2325-16
232516fa
17
LTC2325-16
APPLICATIONS INFORMATION
Pseudo-Differential Unipolar Input Range
The pseudo-differential unipolar configuration represents
driving one of the analog inputs at ground and applying a
signal to the other AIN pin. In this case, the analog input
swings between ground and VREF yielding unipolar two’s
VREF
0V
LT1818
VREF
+
–
0V
complement output codes with an ADC span of half of
full-scale. This configuration is illustrated in Figure 6, and
the corresponding transfer function in Figure 7. If the input
signal (AIN+ – AIN –) swings negative, valid codes will be
generated by the ADC and must be clamped by the user,
if necessary.
LTC2325-16
25Ω
AIN1+
REF
220pF
25Ω
REFOUT1
AIN1–
SDO1
CLKOUT
SCK
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232516 F06
Figure 6. Pseudo-Differential Unipolar Application Circuit
ADC CODE
(2’s COMPLEMENT)
32767
16384
–VREF
–VREF /2
–16385
–32768
0
VREF /2
VREF
AIN
(AIN+ – AIN–)
DOTTED REGIONS AVAILABLE
232516 F07
Figure 7. Pseudo-Differential Unipolar Transfer Function
18
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
APPLICATIONS INFORMATION
Single-Ended-to-Differential Conversion
While single-ended signals can be directly digitized as previously discussed, single-ended to differential conversion
circuits may also be used when higher dynamic range is
desired. By producing a differential signal at the inputs of
the LTC2325-16, the signal swing presented to the ADC is
maximized, thus increasing the achievable SNR.
The LT®1819 high speed dual operational amplifier is
recommended for performing single-ended-to-differential
conversions, as shown in Figure 8. In this case, the first
amplifier is configured as a unity-gain buffer and the
single-ended input signal directly drives the high impedance input of this amplifier.
Fully-Differential Inputs
To achieve the best distortion performance of the
LTC2325‑16, we recommend driving a fully-differential
signal through LT1819 amplifiers configured as two
unity-gain buffers, as shown in Figure 9. This circuit
achieves the full data sheet THD specification of –88dB at
input frequencies up to 500kHz. A fully-differential input
VREF
0V
200Ω
VREF /2
INPUT DRIVE CIRCUITS
A low impedance source can directly drive the high impedance inputs of the LTC2325-16 without gain error. A
high impedance source should be buffered to minimize
settling time during acquisition and to optimize the distortion performance of the ADC. Minimizing settling time
is important even for DC inputs, because the ADC inputs
draw a current spike when during acquisition.
For best performance, a buffer amplifier should be used to
drive the analog inputs of the LTC2325-16. The amplifier
provides low output impedance to minimize gain error
and allows for fast settling of the analog signal during
the acquisition phase. It also provides isolation between
the signal source and the ADC inputs, which draw a small
current spike during acquisition.
VREF
LT1819
+
–
VREF
+
–
VREF
200Ω
signal can span the maximum full-scale of the ADC, up to
±REFOUT1,2,3,4. The common mode input voltage can
span the entire supply range up to VDD, limited by the
input signal swing. The fully-differential configuration is
illustrated in Figure 10, with the corresponding transfer
function illustrated in Figure 11.
0V
0V
0V
VREF
0V
LT1819
+
–
VREF
+
–
VREF
0V
0V
232516 F09
232516 F08
Figure 8. Single-Ended to Differential Driver
Figure 9. LT1819 Buffering a Fully-Differential Signal Source
232516fa
For more information www.linear.com/LTC2325-16
19
LTC2325-16
APPLICATIONS INFORMATION
Input Filtering
the input bandwidth to the ADC core to 110MHz. A buffer
amplifier with a low noise density must be selected to
minimize the degradation of the SNR over this bandwidth.
The noise and distortion of the buffer amplifier and signal
source must be considered since they add to the ADC noise
and distortion. Noisy input signals should be filtered prior
to the buffer amplifier input with a low bandwidth filter
to minimize noise. The simple 1-pole RC lowpass filter
shown in Figure 12 is sufficient for many applications.
High quality capacitors and resistors should be used in the
RC filters since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal film surface mount resistors
are much less susceptible to both problems.
The sampling switch on-resistance (RON) and the sample
capacitor (CIN) form a second lowpass filter that limits
VREF
0V
LT1819
VREF
+
–
0V
LTC2325-16
25Ω
AIN1+
REF
220pF
VREF
0V
REFOUT1
VREF
+
–
0V
25Ω
AIN1–
SDO1
CLKOUT
SCK
ONLY CHANNEL 1 SHOWN FOR CLARITY
10µF
1µF
TO CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
232516 F10
Figure 10. Fully-Differential Application Circuit
ADC CODE
(2’s COMPLEMENT)
32767
16384
–VREF
–VREF /2
0
VREF /2
VREF
AIN
(AIN+ – AIN–)
–16385
–32768
232516 F11
Figure 11. Fully-Differential Transfer Function
20
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
APPLICATIONS INFORMATION
ADC REFERENCE
Internal Reference
The LTC2325-16 has an on-chip, low noise, low
drift (20ppm/°C max), temperature compensated bandgap reference. It is internally buffered and is available
at REF (Pin 8). The reference buffer gains the internal
reference voltage to 4.096V for supply voltages VDD = 5V
and to 2.048V for VDD = 3.3V. The REF pin also drives
SINGLE-ENDED
INPUT SIGNAL
the four internal reference buffers with a current limited
output (250μA) so it may be easily overdriven with an
external reference in the range of 1.25V to 5V. Bypass
REF to GND with a 1μF (X5R, 0805 size) ceramic capacitor
to compensate the reference buffer and minimize noise.
The 1μF capacitor should be as close as possible to the
LTC2325-16 package to minimize wiring inductance. The
voltage on the REF pin must be externally buffered if used
for external circuitry.
IN+
50Ω
IN–
3.3nF
BW = 1MHz
LTC2325
SINGLE-ENDED
TO DIFFERENTIAL
DRIVER
232516 F12
Figure 12. Input Signal Chain
Table 1. Reference Configurations and Ranges
REFERENCE CONFIGURATION
Internal Reference with Internal Buffers
Common External Reference with Internal Buffer (REF Pin
Externally Overdriven)
External Reference with REF Buffers Disabled
VDD
REFBUFEN
REF PIN
REFOUT1,2,3,4
PIN
DIFFERENTIAL
INPUT RANGE
5V
5V
4.096V
4.096V
±4.096V
3.3V
3.3V
2.048V
2.048V
±2.048V
5V
5V
1.25V to 5V
1.25V to 3.3V
±1.25V to ±5V
3.3V
3.3V
1.25V to 5V
1.25V to 3.3V
±1.25V to ±3.3V
5V
0V
4.096V
1.25V to 5V
±1.25V to ±5V
3.3V
0V
2.048V
1.25V to 3.3V
±1.25V to ±3.3V
232516fa
For more information www.linear.com/LTC2325-16
21
LTC2325-16
APPLICATIONS INFORMATION
External Reference
The internal REFOUT1,2,3,4 buffers can also be overdriven from 1.25V to 5V with an external reference at
REFOUT1,2,3,4 as shown in Figure 13 (c). To do so,
REFBUFEN must be grounded to disable the REF buffers.
A 55k internal resistance loads the REFOUT1,2,3,4 pins
when the REF buffers are disabled. To maximize the input
signal swing and corresponding SNR, the LTC6655-5 is
VDD
3.3V TO 5V
REF
LTC2325-16
LTC6655-4.096
REFBUFEN
VIN
SHDN
REF
VOUT_F
VOUT_S
10µF
REFOUT1
10µF
REFOUT2
10µF
LTC2325-16
10µF
0.1µF
REFOUT1
10µF
VDD
+5V
5V TO
13.2V
REFBUFEN
1µF
recommended when overdriving REFOUT. The LTC6655-5
offers the same small size, accuracy, drift and extended
temperature range as the LTC6655-4.096. By using a 5V
reference, a higher SNR can be achieved. We recommend
bypassing the LTC6655-5 with a 10μF ceramic capacitor
(X5R, 0805 size) close to each of the REFOUT1,2,3,4
pins. If the REF pin voltage is used as a REFOUT reference when REFBUFEN is connected to GND, it should be
buffered externally.
REFOUT2
10µF
REFOUT3
REFOUT3
10µF
REFOUT4
10µF
GND
10µF
232516 F13a
REFOUT4
GND
232516 F13b
(13a) LTC2325-16 Internal Reference Circuit
(13b) LTC2325-16 with a Shared External Reference Circuit
+5V
VDD
REFBUFEN
REF
1µF
5V TO 13.2V
LTC6655-4.096
VIN
VOUT_F
SHDN VOUT_S
REFOUT1
10µF
0.1µF
5V TO 13.2V
LTC2325-16
LTC6655-2.048
VIN
VOUT_F
SHDN VOUT_S
REFOUT2
10µF
0.1µF
5V TO 13.2V
LTC6655-2.5
VIN
VOUT_F
SHDN VOUT_S
REFOUT3
10µF
0.1µF
5V TO 13.2V
LTC6655-3
VIN
VOUT_F
SHDN VOUT_S
REFOUT4
10µF
0.1µF
GND
232516 F13c
(13c) LTC2325-16 with Different External Reference Voltages
Figure 13. Reference Connections
22
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
APPLICATIONS INFORMATION
Internal Reference Buffer Transient Response
DYNAMIC PERFORMANCE
The REFOUT1,2,3,4 pins of the LTC2325-16 draw charge
(QCONV) from the external bypass capacitors during
each conversion cycle. If the internal reference buffer is
overdriven, the external reference must provide all of this
charge with a DC current equivalent to IREF = QCONV/tCYC.
Thus, the DC current draw of IREFOUT1,2,3,4 depends
on the sampling rate and output code. In applications
where a burst of samples is taken after idling for long
periods, as shown in Figure 14 , IREFBUF quickly goes
from approximately ~75µA to a maximum of 500µA for
REFOUT = 5V at 5Msps. This step in DC current draw
triggers a transient response in the external reference that
must be considered since any deviation in the voltage at
REFOUT will affect the accuracy of the output code. Due
to the one-cycle conversion latency, the first conversion
result at the beginning of a burst sampling period will
be invalid. If an external reference is used to overdrive
REFOUT1,2,3,4, the fast settling LTC6655 reference is
recommended.
Fast Fourier transform (FFT) techniques are used to test
the ADC’s frequency response, distortion and noise at the
rated throughput. By applying a low distortion sine wave
and analyzing the digital output using an FFT algorithm,
the ADC’s spectral content can be examined for frequencies outside the fundamental. The LTC2325-16 provides
guaranteed tested limits for both AC distortion and noise
measurements.
CNV
IDLE
PERIOD
232516 F14
Figure 14. CNV Waveform Showing Burst Sampling
Signal-to-Noise and Distortion Ratio (SINAD)
The signal-to-noise and distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the A/D output. The output is bandlimited
to frequencies from above DC and below half the sampling
frequency. Figure 16 shows that the LTC2325-16 achieves
a typical SINAD of 81dB at a 5MHz sampling rate with a
2.2MHz input.
Signal-to-Noise Ratio (SNR)
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC. Figure 16 shows
that the LTC2325-16 achieves a typical SNR of 82dB at a
5MHz sampling rate with a 2.2MHz input.
0
32768
AMPLITUDE (dBFS)
OUTPUT CODE (LSB)
24576
16384
4.096V RANGE
8192
0
SNR = 82.1dB
THD = –88.1dB
–20 SINAD = 81.5dB
SFDR = 90.2dB
–40
–60
–80
–100
–120
IN+ = 5MHz SQUARE WAVE
IN– = 0V
–8192
–20 –10 0 10 20 30 40 50 60 70 80 90
SETTLING TIME (ns)
–140
0
1
1.5
FREQUENCY (MHz)
2
2.5
232516 F16
232516 F15
Figure 15. Transient Response of the LTC2325-16
0.5
Figure 16. 32k Point FFT of the LTC2325-16
232516fa
For more information www.linear.com/LTC2325-16
23
LTC2325-16
APPLICATIONS INFORMATION
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the RMS sum
of all harmonics of the input signal to the fundamental itself.
The out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency (fSMPL /2).
THD is expressed as:
THD=20log
V22 + V32 + V42 +…+ VN2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through VN are the amplitudes of the
second through Nth harmonics.
POWER CONSIDERATIONS
The LTC2325-16 requires two power supplies: the 3.3V
to 5V power supply (VDD), and the digital input/output
interface power supply (OVDD). The flexible OVDD supply
allows the LTC2325-16 to communicate with any digital
logic operating between 1.8V and 2.5V. When using LVDS
I/O, the OVDD supply must be set to 2.5V.
Power Supply Sequencing
The LTC2325-16 does not have any specific power supply
sequencing requirements. Care should be taken to adhere
to the maximum voltage relationships described in the
Absolute Maximum Ratings section. The LTC2325‑16
has a power-on-reset (POR) circuit that will reset the
LTC2325-16 at initial power-up or whenever the power
supply voltage drops below 2V. Once the supply voltage
re-enters the nominal supply voltage range, the POR will
reinitialize the ADC. No conversions should be initiated
until 10ms after a POR event to ensure the reinitialization
period has ended. Any conversions initiated before this
time will produce invalid results.
40
SUPPLY CURRENT (mA)
35
VDD = 5V
30
VDD = 3.3V
25
20
15
0
1
2
3
4
SAMPLE FREQUENCY (Msps)
5
232516 F17
Figure 17. Power Supply Current of the LTC2325-16 Versus Sampling Rate
24
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
APPLICATIONS INFORMATION
TIMING AND CONTROL
capture the SDO output eases timing requirements at the
receiver. For low throughput speed applications, CLKOUT
can be disabled by tying Pin 34 to OVDD.
CNV Timing
The LTC2325-16 sampling and conversion is controlled
by CNV. A rising edge on CNV will start sampling and the
falling edge starts the conversion and readout process. The
conversion process is timed by the SCK input clock. For
optimum performance, CNV should be driven by a clean
low jitter signal. The Typical Application at the back of the
data sheet illustrates a recommended implementation to
reduce the relatively large jitter from an FPGA CNV pulse
source. Note the low jitter input clock times the falling
edge of the CNV signal. The rising edge jitter of CNV is
much less critical to performance. The typical pulse width
of the CNV signal is 30ns with < 1.5ns rise and fall times
at a 5Msps conversion rate.
SCK Serial Data Clock Input
In SDR mode (SDR/DDR Pin 23 = GND), the falling edge
of this clock shifts the conversion result MSB first onto
the SDO pins. A 100MHz external clock must be applied
at the SCK pin to achieve 5Msps throughput using all four
SDO outputs. In DDR mode (SDR/DDR Pin 23 = OVDD),
each input edge of SCK shifts the conversion result MSB
first onto the SDO pins. A 50MHz external clock must be
applied at the SCK pin to achieve 5Msps throughput using
all five SDO1 through SDO4 outputs.
CLKOUT Serial Data Clock Output
The CLKOUT output provides a skew-matched clock to
latch the SDO output at the receiver. The timing skew
of the CLKOUT and SDO outputs are matched. For high
throughput applications, using CLKOUT instead of SCK to
CNV
1
Nap/Sleep Modes
Nap mode is a method to save power without sacrificing
power-up delays for subsequent conversions. Sleep mode
has substantial power savings, but a power-up delay is
incurred to allow the reference and power systems to
become valid. To enter nap mode on the LTC2325-16,
the SCK signal must be held high or low and a series of
two CNV pulses must be applied. This is the case for both
CMOS and LVDS modes. The second rising edge of CNV
initiates the nap state. The nap state will persist until either
a single rising edge of SCK is applied, or further CNV pulses
are applied. The SCK rising edge will put the LTC2325-16
back into the operational (full-power) state. When in nap
mode, two additional pulses will put the LTC2325-16 in
sleep mode. When configured for CMOS I/O operation, a
single rising edge of SCK can return the LTC2325-16 into
operational mode. A 10ms delay is necessary after exiting
sleep mode to allow the reference buffer to recharge the
external filter capacitor. In LVDS mode, exit sleep mode
by supplying a fifth CNV pulse. The fifth pulse will return
the LTC2325-16 to operational mode, and further SCK
pulses will keep the part from re-entering nap and sleep
modes. The fifth SCK pulse also works in CMOS mode
as a method to exit sleep. In the absence of SCK pulses,
repetitive CNV pulses will cycle the LTC2325-16 between
operational, nap and sleep modes indefinitely.
Refer to the timing diagrams in Figure 18, Figure 19, Figure 20
and Figure 21 for more detailed timing information about
sleep and nap modes.
2
NAP MODE
SCK
FULL POWER MODE
HOLD STATIC HIGH OR LOW
WAKE ON 1ST SCK EDGE
SDO1 – 4
Z
Z
232516 F18
Figure 18. CMOS and LVDS Mode NAP and WAKE Using SCK
232516fa
For more information www.linear.com/LTC2325-16
25
LTC2325-16
APPLICATIONS INFORMATION
REFOUT1 – 4
REFOUT
RECOVERY
4.096V
4.096V
tWAKE
CNV
1
2
3
4
NAP MODE
SCK
SLEEP MODE
FULL POWER MODE
HOLD STATIC HIGH OR LOW
WAKE ON 1ST SCK EDGE
SDO1 – 4
Z
Z
Z
Z
232516 F19
Figure 19. CMOS Mode SLEEP and WAKE Using SCK
REFOUT1 – 4
REFOUT
RECOVERY
4.096V
4.096V
tWAKE
CNV
1
2
3
4
NAP MODE
SCK
WAKE ON 5TH
CNV EDGE
5
SLEEP MODE
FULL POWER MODE
HOLD STATIC HIGH OR LOW
SDO1 – 4
Z
Z
Z
Z
Z
232516 F20
Figure 20. LVDS and CMOS Mode SLEEP and WAKE Using CNV
SDR MODE TIMING
DDR MODE TIMING
tCYC
tCNVH
tCYC
tCONV
tREADOUT
tCNVH
tDSCKCNVH
CNV
1
2
3
tREADOUT
tDSCKCNVH
tSCKH
tSCK
SCK
tCONV
CNV
tSCKH
tSCK
14
15
SCK
16
1
2
3
1
2
3
14
15
CLKOUT
16
1
tDSCKCLKOUT
SDO
HI-Z
D15
D14
D13
D2
D1
D0
D15
2
3
14
tDSCKCLKOUT
tDCNVSDOZ
tHSDO
tDCNVSDOV
15
16
tSCKL
tSCKL
CLKOUT
14
tDCNVSDOV
HI-Z
SDO
HI-Z
D14
D13
D2
16
tDCNVSDOZ
tHSDO
D15
15
D1
D0
D15
HI-Z
232516 F21
Figure 21. LTC2325-16 Timing Diagram
26
232516fa
For more information www.linear.com/LTC2325-16
LTC2325-16
APPLICATIONS INFORMATION
DIGITAL INTERFACE
SDR/DDR Modes
The LTC2325-16 features a serial digital interface that
is simple and straightforward to use. The flexible OVDD
supply allows the LTC2325-16 to communicate with any
digital logic operating between 1.8V and 2.5V. In addition to a standard CMOS SPI interface, the LTC2325-16
provides an optional LVDS SPI interface to support low
noise digital design. The CMOS /LVDS pin is used to select
the digital interface mode. The SCK input clock shifts the
conversion result MSB first on the SDO pins. CLKOUT
provides a skew-matched clock to latch the SDO output
at the receiver. The timing skew of the CLKOUT and SDO
outputs are matched. For high throughput applications,
using CLKOUT instead of SCK to capture the SDO output
eases timing requirements at the receiver. In CMOS mode,
use the SDO1 – SDO4, and CLKOUT pins as outputs. Use
the SCK pin as an input. In LVDS mode, use the SDOA+/
SDOA– through SDOD+/SDOD– and CLKOUT+/CLKOUT–
pins as differential outputs. Each LVDS lane yields one
channel worth of data: SDOA yields CH1 data, SDOB
yields CH2 data, SDOC yields CH3 data and SDOD yields
CH4 data. These pins must be differentially terminated
by an external 100Ω resistor at the receiver (FPGA).
The SCK+/SCK– pins are differential inputs and must be
terminated differentially by an external 100Ω resistor at
the receiver(ADC).
The LTC2325-16 has an SDR (single data rate) and DDR
(double data rate) mode for reading conversion data from
the SDO pins. In both modes, CLKOUT is a delayed version
of SCK. In SDR mode, each negative edge of SCK shifts the
conversion data out the SDO pins. In DDR mode, each edge
of the SCK input shifts the conversion data out. In DDR
mode, the required SCK frequency is half of what is required
in SDR mode. Tie SDR/DDR to ground to configure for SDR
mode and to OVDD for DDR mode. The CLKOUT signal is
a delayed version of the SCK input and is phase aligned
with the SDO data. In SDR mode, the SDO transitions on
the falling edge of CLKOUT as illustrated in Figure 21.
We recommend using the rising edge of CLKOUT to latch
the SDO data into the FPGA register in SDR mode. In
DDR mode, the SDO transitions on each input edge of
SCK. We recommend using the CLKOUT rising and falling edges to latch the SDO data into the FPGA registers
in DDR mode. Since the CLKOUT and SDO data is phase
aligned, the SDO signals will need to be digitally delayed
in the FPGA to provide adequate setup and hold timing
margins in DDR mode.
LTC2325-16
2.5V
SCK+
SCK–
2.5V
CMOS/LVDS
FPGA OR DSP
OVDD
+
–
100Ω
BOARD LAYOUT
To obtain the best performance from the LTC2325-16,
a printed circuit board is recommended. Layout for the
printed circuit board (PCB) should ensure the digital and
analog signal lines are separated as much as possible.
In particular, care should be taken not to run any digital
clocks or signals adjacent to analog signals or underneath
the ADC.
SDOD+
SDOD–
100Ω
+
–
SDOC+
SDOC–
100Ω
+
–
CLKOUT+
CLKOUT –
100Ω
+
–
SDOB+
SDOB–
100Ω
+
–
Supply bypass capacitors should be placed as close as
possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low
noise operation of the ADC. A single solid ground plane
is recommended for this purpose. When possible, screen
the analog input traces using ground.
SDOA+
SDOA–
100Ω
+
–
Recommended Layout
CNV
RETIMING
FLIP-FLOP
232516 F22
Figure 22. LTC2325-16 Using the LVDS Interface
For a detailed look at the reference design for this converter, including schematics and PCB layout, please refer
to DC2395A, the evaluation kit for the LTC2325-16.
232516fa
For more information www.linear.com/LTC2325-16
27
LTC2325-16
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2325-16#packaging for the most recent package drawings.
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
Package
(Reference LTCUKG
DWG
# 05-08-1729 Rev Ø)
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 ±0.05
6.10 ±0.05
5.50 REF
(2 SIDES)
0.70 ±0.05
6.45 ±0.05
6.50 REF 7.10 ±0.05 8.50 ±0.05
(2 SIDES)
5.41 ±0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
7.00 ±0.10
(2 SIDES)
0.75 ±0.05
R = 0.115
TYP
0.00 – 0.05
5.50 REF
(2 SIDES)
51
52
0.40 ±0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
8.00 ±0.10
(2 SIDES)
6.50 REF
(2 SIDES)
6.45 ±0.10
5.41 ±0.10
R = 0.10
TYP
TOP VIEW
0.200 REF
0.00 – 0.05
0.75 ±0.05
(UKG52) QFN REV Ø 0306
0.25 ±0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
SIDE VIEW
28
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
For more information www.linear.com/LTC2325-16
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LTC2325-16
REVISION HISTORY
REV
DATE
DESCRIPTION
A
02/17
Corrected latency to one cycle
PAGE NUMBER
1
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection
of its
circuits as described
herein will not infringe on existing patent rights.
For more
information
www.linear.com/LTC2325-16
29
LTC2325-16
TYPICAL APPLICATION
Low Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Retiming Flip-Flop
VCC
0.1µF
50Ω
1k
NC7SVUO4P5X
MASTER_CLOCK
VCC
1k
D
PRE
NC7SV74K8X Q
CLR
CONV
CONV ENABLE
CNV
LTC2325-16
SCK
CLKOUT
GND
CMOS/LVDS
GND
SDR/DDR
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
SDO1 – 4
10Ω
10Ω
NC7SVU04P5X (× 5)
232516 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
ADCs
LTC2311-16/LTC2311-14/ 16-/14-/12-Bit, 5Msps Simultaneous Sampling ADC 3.3V Supply, 1-Channel 40mW, 20ppm/°C Internal Reference, Flexible
LTC2311-12
Inputs, 16-Lead MSOP Package
LTC2314-14
16-14-/12-Bit 5Msps Dual Simultaneous Sampling
ADC
3V/5V Supply, 40mW/Ch, 20ppm/°C Max Internal Reference, Flexible
Inputs, 4mm × 5mm QFN-28 Package
LTC2321-16/LTC2321-14/ 16-/14-/12-Bit, Dual 2Msps, Simultaneous
LTC2321-12
Sampling ADCs
3.3V/5V Supply, 33mW/Ch, 20ppm°C Max Internal Reference,
Flexible Inputs, 4mm × 5mm QFN-28 Package
LTC2320-16/LTC2320-14/ 16-/14-/12-Bit, Octal, 1.5Msps/Channel
LTC2320-12
Simultaneous Sampling ADC
3.3V/5V Supply, 20mW/Channel, 20ppm/°C Internal Reference, Flexible
Inputs, 7mm × 8mm QFN-52 Package
LTC2324-16/LTC2324-14/ 16-/14-/12-Bit, Quad, 2Msps/Channel Simultaneous 3.3V/5V Supply, 40mW/Channel, 20ppm/°C Internal Reference, Flexible
LTC2324-12
Sampling ADC
Inputs, 7mm × 8mm QFN-52 Package
DACs
LTC2632
Dual 12-/10-/8-Bit, SPI VOUT DACs with Internal
Reference
2.7V to 5.5V Supply Range, 10ppm/°C Reference, External REF Mode,
Rail-to-Rail Output, 8-Pin ThinSOT™ Package
LTC2602/LTC2612/
LTC2622
Dual 16-/14-/12-Bit SPI VOUT DACs with External
Reference
300μA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output, 8-Lead
MSOP Package
LTC6655
Precision Low Drift, Low Noise Buffered Reference
5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 2ppm/°C, 0.25ppm
Peak-to-Peak Noise, MSOP-8 Package
LTC6652
Precision Low Drift, Low Noise Buffered Reference
5V/4.096V/3.3V/3V/2.5V/2.048V/1.25V, 5ppm/°C, 2.1ppm
Peak-to-Peak Noise, MSOP-8 Package
LT1818/LT1819
400MHz, 2500V/µs, 9mA Single/Dual Operational
Amplifiers
–85dBc Distortion at 5MHz, 6nV/√Hz Input Noise Voltage, 9mA Supply
Current, Unity-Gain Stable
LT1806
325MHz, Single, Rail-to-Rail Input and Output, Low –80dBc Distortion at 5MHz, 3.5nV/√Hz Input Noise Voltage,
Distortion, Low Noise Precision Op Amps
9mA Supply Current, Unity-Gain Stable
LT6200
165MHz, Rail-to-Rail Input and Output, 0.95nV/√Hz Low Noise, Low Distortion, Unity-Gain Stable
Low Noise, Op Amp Family
References
Amplifiers
30 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
For more information www.linear.com/LTC2325-16
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC2325-16
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LT 0217 REV A • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2017