240pin DDR3 SDRAM VLP Registered DIMM DDR3 SDRAM VLP Registered DIMM Based on 1Gb A version HMT112V7AFP8C HMT125V7AFP8C HMT125V7AFP4C HMT351V7AMP4C ** Contents may be changed at any time without any notice. Rev. 0.2 / December 2008 1 Revision History Revision No. History Draft Date 0.1 Initial Release 2008-8 0.2 Added IDD, corrected typos 2008-12 Rev. 0.2 / December 2008 Remark 2 Table of Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 1GB, 128Mx72 Module(1Rank 3.2 2GB, 256Mx72 Module(2Rank 3.3 2GB, 256Mx72 Module(1Rank 3.4 4GB, 512Mx72 Module(2Rank of of of of x8) x8) x4) x4) 4. Input/Output Capacitance & AC Parametrics 5. IDD Specifications 6. DIMM Outline Diagram 6.1 1GB, 128Mx72 Module(1Rank 6.2 2GB, 256Mx72 Module(2Rank 6.3 2GB, 256Mx72 Module(1Rank 6.4 4GB, 512Mx72 Module(2Rank Rev. 0.2 / December 2008 of of of of x8) x8) x4) x4) 3 1. Description This Hynix DDR3 VLP (Very Low Profile) registered Dual In-Line Memory Module (DIMM) series consists of 1Gb A generation. These are intended for use as main memory in server and workstation systems, providing a high performance 8 byte interface in 133.35mm width form factor of industry standard. It is suitable for easy interchange and addition. 1.1 Device Features & Ordering Information 1.1.1 Features • VDD=VDDQ=1.5V • BL switch on the fly • VDDSPD=3.3V to 3.6V • 8banks • Fully differential clock inputs (CK, CK) operation • 8K refresh cycles /64ms • Differential Data Strobe (DQS, DQS) • DDR3 SDRAM Package: JEDEC standard 78ball FBGA(x4/x8), 96ball FBGA(x16) with support balls • On chip DLL align DQ, DQS and /DQS transition with CK transition • Driver strength selected by EMRS • DM masks write data-in at the both rising and falling edges of the data strobe • Dynamic On Die Termination supported • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • ZQ calibration supported • Asynchronous RESET pin supported • TDQS (Termination Data Strobe) supported (x8 only) • Programmable CAS latency 5, 6, 7, 8, 9, 10, and (11) supported • Write Levelization supported • Programmable additive latency 0, CL-1, and CL-2 sup ported • 8 bit pre-fetch • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • Auto Self Refresh supported • Heat Spreader installed for 4GB • SPD with Integrated TS of Class B 1.1.2 Ordering Information Density Organization # of DRAMs # of ranks Materials FDHS HMT112V7AFP8C-G7/H9 1GB 128Mx72 9 1 Lead free X HMT125V7AFP8C-G7/H9 2GB 256Mx72 18 2 Lead free X HMT125V7AFP4C-G7/H9 2GB 256Mx72 18 1 Lead free X HMT351V7AMP4C-G7/H9 4GB 512Mx72 36 2 Lead free O Part Name *Please Contact local sales administrator for more details of part number Rev. 0.2 / December 2008 4 1.2 Speed Grade & Key Parameters MT/S DDR3-1066 DDR3-1333 Grade -G7 -H9 tCK (min) 1.875 1.5 ns CAS Latency 7 9 tCK tRCD (min) 13.125 13.5 ns tRP (min) 13.125 13.5 ns tRAS (min) 37.5 36 ns tRC (min) 50.625 49.5 ns CL-tRCD-tRP 7-7-7 9-9-9 tCK Unit 1.3 Address Table 1GB(1Rx8) 2GB(2Rx8) 2GB(1Rx4) 4GB(2Rx4) Organization 128M x 72 256M x 72 256M x 72 512M x 72 Refresh Method 8K/64ms 8K/64ms 8K/64ms 8K/64ms Row Address A0-A13 A0-A13 A0-A13 A0-A13 Column Address A0-A9 A0-A9 A0-A9,A11 A0-A9,A11 Bank Address BA0-BA2 BA0-BA2 BA0-BA2 BA0-BA2 Page Size 1KB 1KB 1KB 1KB # of Rank 1 2 1 2 # of Device 9 18 18 36 Rev. 0.2 / December 2008 5 2. Pin Architecture 2.1 Pin Definition Num -ber Pin Name Address Inputs 14 A10/AP Address Input/Autoprecharge 1 SDRAM Bank Addresses 3 A12/BC Address Input/Autoprecharge 1 RAS Row Address Strobe 1 SCL Serial Presence Detect (SPD) Clock Input 1 CAS Column Address Strobe 1 SDA SPD Data Input/Output 1 WE Write Enable 1 SA0–SA2 Pin Name A0–A9,A11 A13-A15 BA0–BA2 Description Description Num -ber SPD Address Inputs 3 1 Chip Selects 4 Par_in Parity Bit For The Address and Control Bus CKE0–CKE1 Clock Enables 2 ERR_OUT Parity Error Found on the Address and Control Bus 1 ODT0–ODT1 On-die termination Inputs 2 EVENT Reserved for Optional Hardware temperature Sensing 1 Data Input/Output 64 TEST Memory Bus Test Tool (Not Connected and Not Usable on DIMMs) 1 Data Check Bits Input/Output 8 RESET Register and SDRAM control pin 1 DQS0–DQS8 Data Strobes 9 VDD Power Supply 22 DQS0–DQS8 Data Strobes, Negative Line 9 VSS Ground 59 VREFDQ Reference Voltage for DQ 1 VREFCA Reference Voltage for CA 1 Termination Voltage 4 SPD Power 1 CK1 Clock Input, positive line 1 CK1 Clock Input, negative line 1 S0–S3 DQ0–DQ63 CB0–CB7 Data Masks DM0–DM8 DQS9-DQS17 Data Strobes TDQS9-TDQS17 Termination Data Strobes DQS9–DQS17 Data Strobes, Negative Line TDQS9–TDQS17 Termination Data Strobes 9 VTT 9 CK0 Clock Input, positive line 1 CK0 Clock Input, positive Line 1 Rev. 0.2 / December 2008 VDDSPD 6 2.2 Input/Output Functional Description Symbol Type Polarity Function CK0 IN Positive Line Positive line of the differential pair of system clock inputs that drives input to the on-DIMM Clock Driver. CK0 IN Negative Line Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver. CK1 IN Positive Line Terminated but not used on RDIMMs CK1 IN Negative Line Terminated but not used on RDIMMs CKE0–CKE1 IN Active High CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank) S0–S3 IN Active Low Enables the command decoders for the associated rank of SDRAM when low and disables decoders.When decoders are disabled, new commands are ignored and previous operations continue.Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s).For modules with two registers,S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words. RAS, CAS, WE IN Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. ODT0–ODT1 IN Active High On-Die Termination control signals VREFDQ Supply Reference voltage for DQ0-DQ63 and CB0-CB7 VREFCA Supply Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In, ODT0 and ODT1. VDDQ Supply Power supply for the DDR3 SDRAM output buffers to provide improved noise immunity. For all current DDR3 unbuffered DIMM designs, VDDQ shares the same power plane as VDD pins. Selects which SDRAM bank of eight is activated. BA0–BA2 IN — BA0-BA2 define to which bank an Active, Read, Write or Precharge command is being applied.Bank address also determines mode register is to be accessed during an MRS cycle. A0-A9 A10/AP A11 A12/BC A13-A15 IN — Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank.A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH).If only one bank is to be precharged, the bank is selected by BA.A12 is also utilized for BL 4/8 identification for “BL on the fly” during CAS command. The address inputs also provide the op-code during Mode Register Set commands. DQ0–DQ63, CB0–CB7 I/O — Data and Check Bit Input/Output pins. Rev. 0.2 / December 2008 7 Symbol Type Polarity DM0–DM8 IN Active High VDD, VSS Supply Power and ground for the DDR3 SDRAM input buffers, and core logic. VTT Supply Termination Voltage for Address/Command/Control/Clock nets. DQS0-DQS17 I/O Positive Edge Positive line of the differential data strobe for input and output data. DQS0–DQS17 I/O Negative Edge Negative line of the differential data strobe for input and output data. TDQS9-TDQS17 TDQS9-TDQS17 Masks write data when high, issued concurrently with input data. TDQS/TDQS is applicable for x8 DRAMs only. WHen enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used.x4/x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. OUT SA0–SA2 Function — These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range. SDA I/O — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. An external resistor may be connected from the SDA bus line to VDDSPD to act as a pullup on the system board. SCL IN — This signal is used to clock data into and out of the SPD EEPROM. An external resistor may be connected from the SCL bus time to VDDSPD to act as a pull up. VDDSPD Supply EVENT OUT (open drain) Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation. Active Low This signal indicates that a thermal event has been detected in the thermal sensing device. The system should guarantee the electrical level requirement is met for the EVENT pin on TS/SPD part. RESET IN The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM. When low, all register outputs will be driven low and the Clock Driver clocks to the DRAMs and register(s) will be set to low level (the Clock Driver will remain synchronized with the input clock) Par_In IN Parity bit for the Address and Control bus.(“1”:Odd, “0”:Even) Err_Out OUT (open drain) TEST Rev. 0.2 / December 2008 Parity error detected on the Address and Control bus.A resistor may be connected from Err_Out bus line to VDD on the system planar to act as a pull up. Used by memory bus analysis tools (unused (NC) on memory DIMMs) 8 2.3 Pin Assignment Pin # Front Side (left 1–60) Pin # Back Side (right 121–180) Pin # Front Side (left 61–120) Pin # Back Side (right 181–240) 1 VREFDQ 121 VSS 61 A2 181 A1 2 VSS 122 DQ4 62 VDD 182 VDD 3 DQ0 123 DQ5 63 NC, CK1 183 VDD 4 DQ1 124 VSS 64 NC, CK1 184 CK0 5 VSS 125 DM0,DQS9,TDQS9 65 VDD 185 CK0 6 DQS0 126 NC, DQS9,TDQS9 66 VDD 186 VDD 7 DQS0 127 VSS 67 VREFCA 187 EVENT, NC 8 VSS 128 DQ6 68 Par_in, NC 188 A0 9 DQ2 129 DQ7 69 VDD 189 VDD 10 DQ3 130 VSS 70 A10 / AP 190 BA1 11 VSS 131 DQ12 71 BA0 191 VDD 12 DQ8 132 DQ13 72 VDD 192 RAS 13 DQ9 133 VSS 73 WE 193 S0 14 VSS 134 DM1,DQS10,TDQS10 74 CAS 194 VDD 15 DQS1 135 NC,DQS10,TDQS10 75 VDD 195 ODT0 16 DQS1 136 VSS 76 S1, NC 196 A13 17 VSS 137 DQ14 77 ODT1, NC 197 VDD 18 DQ10 138 DQ15 78 VDD 198 S3, NC 19 DQ11 139 VSS 79 S2, NC 199 VSS 20 VSS 140 DQ20 80 VSS 200 DQ36 21 DQ16 141 DQ21 81 DQ32 201 DQ37 22 DQ17 142 VSS 82 DQ33 202 VSS 23 VSS 143 DM2,DQS11,TDQS11 83 VSS 203 DM4,DQS13,TDQS13 24 DQS2 144 NC,DQS11,TDQS11 84 DQS4 204 NC, DQS13,TDQS13 25 DQS2 145 VSS 85 DQS4 205 VSS 26 VSS 146 DQ22 86 VSS 206 DQ38 27 DQ18 147 DQ23 87 DQ34 207 DQ39 28 DQ19 148 VSS 88 DQ35 208 VSS 29 VSS 149 DQ28 89 VSS 209 DQ44 30 DQ24 150 DQ29 90 DQ40 210 DQ45 31 DQ25 151 VSS 91 DQ41 211 VSS 32 VSS 152 DM3,DQS12,TDQS12 92 VSS 212 DM5,DQS14,TDQS14 33 DQS3 153 NC, DQS12,TDQS12 93 DQS5 213 NC, DQS14,TDQS14 NC = No Connect; RFU = Reserved Future Use Rev. 0.2 / December 2008 9 Pin # Front Side (left 1–60) Pin # Back Side (right 121–180) Pin # Front Side (left 61–120) Pin # Back Side (right 181–240) 34 DQS3 154 VSS 94 DQS5 214 VSS 35 VSS 155 DQ30 95 VSS 215 DQ46 36 DQ26 156 DQ31 96 DQ42 216 DQ47 37 DQ27 157 VSS 97 DQ43 217 VSS 38 VSS 158 CB4, NC 98 VSS 218 DQ52 39 CB0, NC 159 CB5, NC 99 DQ48 219 DQ53 40 CB1, NC 160 VSS 100 DQ49 220 VSS 41 VSS 161 DM8,DQS17,TDQS17 NC 101 VSS 221 DM6,DQS15,TDQS15 42 DQS8 162 NC,DQS17,TDQS17 102 DQS6 222 NC, DQS15,TDQS15 43 DQS8 163 VSS 103 DQS6 223 VSS 44 VSS 164 CB6, NC 104 VSS 224 DQ54 45 CB2, NC 165 CB7, NC 105 DQ50 225 DQ55 46 CB3, NC 166 VSS 106 DQ51 226 VSS 47 VSS 167 NC(TEST) 107 VSS 227 DQ60 48 VTT, NC 168 RESET 108 DQ56 228 DQ61 109 DQ57 229 VSS KEY KEY 49 VTT, NC 169 CKE1, NC 110 VSS 230 DM7,DQS16,TDQS16 50 CKE0 170 VDD 111 DQS7 231 NC, DQS16,TDQS16 51 VDD 171 A15 112 DQS7 232 VSS 52 BA2 172 A14 113 VSS 233 DQ62 53 Err_Out, NC 173 VDD 114 DQ58 234 DQ63 54 VDD 174 A12 / BC 115 DQ59 235 VSS 55 A11 175 A9 116 VSS 236 VDDSPD 56 A7 176 VDD 117 SA0 237 SA1 57 VDD 177 A8 118 SCL 238 SDA 58 A5 178 A6 119 SA2 239 VSS 59 A4 179 VDD 120 VTT 240 VTT 60 VDD 180 A3 NC = No Connect; RFU = Reserved Future Use Rev. 0.2 / December 2008 10 3. Functional Block Diagram S0_n S1_n BA[N:0] A[N:0] RAS_n CAS_n WE_n CKE0 ODT0 CK0_t CK0_c CK1_t CK1_c PAR_IN 120Ω ± 1% 1: 2 R E G I S T E R / P L L 120Ω ± 1% RESET_n OERR_n RST_n RS0A_n → CS0_n: SDRAMs D[3:0], D8 RS0BCK_n → CS0_n: SDRAMs D[7:4] RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8 RA[N:0]B → A[N:0]: SDRAMs D[7:4] RRASA_n → RAS_n: SDRAMs D[3:0], D8 RRASB_n → RAS_n: SDRAMs D[7:4] RCASA_n → CAS_n: SDRAMs D[3:0], D8 RCASB_n → CAS_n: SDRAMs D[7:4] RWEA_n → WE_n: SDRAMs D[3:0], D8 RWEB_n → WE_n: SDRAMs D[7:4] RCKE0A → CKE0: SDRAMs D[3:0], D8 RCKE0B → CKE0: SDRAMs D[7:4] RODT0A → ODT0: SDRAMs D[3:0], D8 RODT0B → ODT0: SDRAMs D[7:4] PCK0A_t → CK_t: SDRAMs D[3:0], D8 PCK0B_t → CK_t: SDRAMs D[7:4] PCK0A_c → CK_c: SDRAMs D[3:0], D8 PCK0B_c → CK_c: SDRAMs D[7:4] A[N:O]B /BA[N:O]B RODT0B PCK0B_c RCKE0B RWEB_n PCK0B_t A[O:N]/BA[O:N] ODT CK_n CKE CK_t CAS_n WE_n ODT CK_n CKE CK_t WE_n CAS_n D5 ODT CK_n CKE CK_t WE_n CAS_n D6 A[O:N]/BA[N:O] ZQ ODT CK_n CKE CK_t D7 A[N:O]/BA[N:O] ZQ WE_n RAS_n CS_n A[N:O]/BA[N:O] ODT CK_n CKE CK_t Vtt ZQ A[O:N]/BA[N:O] DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D0 RCASB_n DQS7_t DQS7_c DM7/DQS16_t DQS16_c DQ[63:56] RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] CS_n DQS6_t DQS6_c DM6/DQS15-t DQS15_c DQ[55:48] D4 CAS_n ODT A[O:N]/BA[N:O] A[N:O]/BA[N:O] ODT DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n ODT ODT CK_n CKE CK_n CKE CK_n CKE CK_t RS0B_n RRASB_n A[N:O]A /BA[N:O]A RODT0A PCK0A_c RCKE0A CK_n CKE CK_t D1 WE_n CAS_n RAS_n CK_t WE_n ZQ DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] CS_n CK_t CAS_n WE_n WE_n CAS_n CAS_n CAS_n D2 WE_n RAS_n CS_n CS_n RAS_n RAS_n ZQ DQS5_t DQS5_c DM5/DQS14_t DQS14_c DQ[47:40] CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] D3 DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n DQS1_t DQS1_c DM1/DQS10_t DQS10_c DQ[15:8] ZQ ZQ DQS4_t DQS4_c DM4/DQS13_t DQS13_c DQ[39:32] CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] A[N:O]/BA[N:O] DQS2_t DQS2_c DM2/DQS11_t DQS11_c DQ[23:16] D8 A[O:N]/BA[N:O] DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] RAS_n DQS3_t DQS3_c DM3/DQS12_t DQS12_c DQ[31:24] CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] CS_n RWEA_n ZQ DQS8_t DQS8_c DM8/DQS17_t DQS17_c CB[7:0] DQS0_t DQS0_c DM0/DQS9_t DQS9_c DQ[7:0] PCK0A_t RS0A_n RRASA_n RCASA_n 3.1 1GB, 128Mx72 Module(1Rank of x8) Vtt VDDSPD SPD VDD D0–D8 VTT VREFCA D0–D8 VREFDQ D0–D8 VSS D0–D8 Note: 1.DQ-to-I/O wiring may be changed within byte. 2.ZQ resistors are 240Ω ± 1%.For all other resistor values refer to the appropriate wiring diagram. VDDSPD EVENT SCL SDA SA0 SA0 EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA SA1 VDDSPD SA2 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative Err_Out_n RST_n: SDRAMs D[8:0] S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 120...330Ω resistor to ground Rev. 0.2 / December 2008 11 RODT1B D16 CK_c CKE A[N:O]/BA[N:O] ODT A[N:O]/BA[N:O] A[O:N]/BA[N:O] ODT ODT ODT CK_c CKE CK_t WE_n CAS_n D15 CK_t A[N:O]/BA[N:O] PCK1B CK_t WE_n CAS_n CK_c CKE CK_c CKE CK_t WE_n CAS_n D14 WE_n CS_n RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D13 CAS_n CS_n RAS_n RAS_n CS_n CS_n RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ PCK1B RCKE1B RS1B A[N:O]B /BA[N:O]B RODT0B ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT ODT DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ A[N:O]/BA[N:O] CK_c CKE CK_c CKE CK_c CKE DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ A[N:O]/BA[N:O] RWEB PCK0B RCASB PCK0B RCKE0B CK_c CKE CK_t WE_n WE_n CK_t CK_t RAS_n CS_n CS_n RAS_n RAS_n CS_n D7 ODT CK_c CKE CK_t WE_n D9 A[N:O]/BA[N:O] Vtt VDDSPD EVENT_n SCL Vtt SDA Note: 1. DQ-to-I/O wiring may be changed within a byte. 2. Unless otherwise noted, resistor values are 15Ω ± 5%. 3. ZQ resistors are 240Ω ± 1%. For all other resistor values refer to the appropriate wiring diagram. 4. See the wiring diagrams for all resistors associated with the command, address and control bus. Rev. 0.2 / December 2008 WE_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D6 CK_t DQS7_t DQS7_c DM7/DQS16_t DQS16_c DQ[63:56] D5 WE_n RS0B RRASB DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CAS_n DQS6_t DQS6_c DM6/DQS15_t DQS15_c DQ55:48] RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CS_n DQS5_t DQS5_c DM5/DQS14_t DQS14_ DQ[47:40] D4 CAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CAS_n DQS4_t DQS4_c DM4/DQS13-t DQS13_c DQ[39:32] CAS_n RODT1A A[N:O]/BA[N:O] ODT ODT ODT A[N:O]/BA[N:O] ODT CK_c CKE WE_n CK_t CK_t WE_n CK_c CKE CK_c CKE CK_t WE_n A[N:O]/BA[N:O] CK_c CKE CK_t WE_n CAS_n D10 A[O:N]/BA[N:O] PCK1A_t PCK1A_c RCKE1A RS1A_c RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CAS_n RAS_n RAS_n CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D11 CAS_n RAS_n CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D12 CAS_n RAS_n CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D17 CAS_n CS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CS_n RODT0A A[N:O]A /BA[N:O]A A[N:O]/BA[N:O] ODT ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT ODT ODT CK_c CKE D0 A[O:N]/BA[N:O] CK_c CKE CK_c CKE CK_c CKE D1 A[N:O]/BA[N:O] RWEA_n PCK0A_t RCASA_n PCK0A_c RCKE0A CK_c CKE WE_n CAS_n CK_t CK_t WE_n CAS_n CS_n RAS_n RAS_n CS_n CS_n RAS_n RAS_n CS_n CK_t DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ WE_n DQS0_t DQS0_c DM0/DQS9_t DQS9_c DQ[7:0] CAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CK_t DQS1_t DQS1_c DM1/DQS10_t DQS10_c DQ[15:8] D2 WE_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CAS_n DQS2_t DQS2_c DM2/DQS11_t DQS11_c DQ[23:16] D3 CK_t DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ D8 WE_n DQS3_t DQS3_c DM3/DQS12_t DQS12_c DQ[31:24] RAS_n DQS_t DQS_c TDQS_t TDQS_c DQ [7:0] ZQ CS_n DQS8_t DQS8_c DM8/DQS17_t DQS17_c CB[7:0] CAS_n RS0A_n RRASA_n 3.2 2GB, 256Mx72 Module(2Rank of x8) VDDSPD SA0 SA0 EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA SA1 SA2 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative VDDSPD Serial PD VDD D0–D17 VTT VREFCA D0–D17 VREFDQ D0–D17 VSS D0–D17 D0–D17 12 S0_n 1:2 S1_n S[3:2] NC R E G I S T E R / P L L BA[N:0] A[N:0] RAS_n CAS_n WE_n CKE0 ODT0 RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17 RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13] RA[N:0]A → A[N:0]: SDRAMs D[3:0], D[12:8], D17 RA[N:0]B → A[N:0]: SDRAMs D[7:4], D[16:13] RRASA_n → RAS_n: SDRAMs D[3:0], D[12:8], D17 RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13] RCASA_n → CAS_n: SDRAMs D[3:0], D[12:8], D17 RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13] RWEA_n → WE_n: SDRAMs D[3:0], D[12:8], D17 RWEB_n → WE_n: SDRAMs D[7:4], D[16:13] RCKE0A → CKE0: SDRAMs D[3:0], D8 RCKE0B → CKE0: SDRAMs D[7:4] RODT0A → ODT0: SDRAMs D[3:0], D8 RODT0B → ODT0: SDRAMs D[7:4] PCK0A_t → CK-t: SDRAMs D[3:0], D8 PCK0B_t → CK_t: SDRAMs D[7:4] CK0_t 120Ω PCK0A_c → CK_c: SDRAMs D[3:0], D8 PCK0B_c → CK_c: SDRAMs D[7:4] CK0_c CK1_t RS0A_n → CS0_n: SDRAMs D[3:0], D8 RS0B_n → CS0_n: SDRAMs D[7:4] 120Ω CK1_c PAR_IN Err_Out_n RESET_n RST_n Rev. 0.2 / December 2008 RST_n: SDRAMs D[17:0] 13 ODT CK_c CKE CK_t WE_n VSS A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n VSS A[N:O]/BA[N:O] ODT CK_c CKE CK_t VSS A[N:O]/BA[N:O] ODT CK_t CK_c CKE D15 ODT CK_c CKE VSS D16 A[N:O]/BA[N:O] ZQ CK_t RAS_n CS_n CAS_n ZQ CAS_n RAS_n CS_n D14 CAS_n ODT A[N:O]/BA[N:O] A[N:O]/BA[N:O] ODT CK_c CKE D7 RAS_n DQS_t DQS_c DM DQ [3:0] ZQ WE_n DQS16_t DQS16_c VSS DQ[63:60] ZQ RAS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_c CKE D6 D13 WE_n DQS_t DQS_c DM DQ [3:0] ZQ ZQ WE_n DQS15_t DQS15_c VSS DQ[55;52] CS_n VSS VSS A[N:O]/BA[N:O] DQS_t DQS_c DM DQ [3:0] VSS ODT VSS DQS14_t DQS14_c VSS DQ[47:44] CS_n RODT0B A[O:N]B /BA[O:N]B RWEB_n PCK0B_t RCASB_n PCK0B_c RCKE0B CK_c CKE CK_t WE_n CK_t WE_n CAS_n CAS_n CAS_n CAS_n RAS_n DQS_t DQS_c DM DQ [3:0] Vtt VSS D9 A[N:O]/BA[N:O] ZQ RAS_n CS_n CS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D10 D5 CK_t DQS_t DQS_c DM DQ [3:0] ZQ DQS13_t DQS13_c VSS DQ[39:36] ZQ WE_n DQS7_t DQS7_c VSS DQ[59:56] CS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D11 D4 CK_t DQS_t DQS_c DM DQ [3:0] ZQ WE_n RS0B_n RRASB_n DQS6_t DQS6_c VSS DQ[51:48] ZQ RAS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D12 RAS_n DQS_t DQS_c DM DQ [3:0] CS_n VSS VSS DQS5_t DQS5_c VSS DQ[43:40] VSS A[N:O]/BA[N:O] DQS_t DQS_c DM DQ [3:0] VSS ODT DQS4_t DQS4_c VSS DQ[35:32] ZQ CAS_n RAS_n RAS_n CS_n CS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n D0 CK_c CKE DQS_t DQS_c DM DQ [3:0] ZQ D17 CK_t DQS9_t DQS9_c VSS DQ[7:4] CS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D1 ZQ WE_n DQS_t DQS_c DM DQ [3:0] ZQ CAS_n DQS10_t DQS10_c VSS DQ[15:12] CS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D2 RAS_n DQS_t DQS_c DM DQ [3:0] CS_n DQS11_t DQS11_c VSS DQ23:20] ZQ RAS_n A[N:O]/BA[N:O] ODT CK_c CKE CK_t WE_n CAS_n D3 RAS_n PCK0A_c RCKE0A RODT0A RWEA_n PCK0A_t A[N:O]A /BA[N:O]A VSS CAS_n DQS_t DQS_c DM DQ [3:0] ZQ CAS_n CS_n RAS_n RAS_n CS_n CS_n RAS_n RAS_n CS_n A[N:O]/BA[N:O] DQS_t DQS_c DM DQ [3:0] VSS DQS0_t DQS0_c VSS DQ[3:0] DQS12_t DQS12_c VSS DQ[31:28] VSS DQS_t DQS_c DM DQ [3:0] DQS_t DQS_c DM DQ [3:0] VSS DQS1_t DQS1_c VSS DQ[11;8] DQS17_t DQS17_c VSS CB[7:4] VSS DQS_t DQS_c DM DQ [3:0] ODT DQS2_t DQS2_c VSS DQ[19:16] D8 CK_c CKE DQS_t DQS_c DM DQ [3:0] ZQ CK_t DQS3_t DQS3_c VSS DQ[27:24] RAS_n DQS_t DQS_c DM DQ [3:0] CS_n DQS8_t DQS8_c VSS CB[3:0] WE_n RS0A_n RRASA_n RCASA_n 3.3 2GB, 256Mx72 Module(1Rank of x4) Vtt VDDSPD EVENT SA0 SA0 SPD with SA1 Integrated SA2 TS VSS SA1 VDDSPD EVENT SCL SCL SDA SDA SA2 VSS Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative Note: 1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistor values are 15 Ω ± 5%. 3. See the wiring diagrams for all resistors associated with the command, address and control bus. 4. ZQ resistors are 240Ω ± 1 %. For all other resistor values refer to the appropriate wiring diagram. Rev. 0.2 / December 2008 VDDSPD SPD VDD D0–D17 VTT VREFCA D0–D17 VREFDQ D0–D17 VSS D0–D17 14 S0_n 1:2 S1_n R E G I S T E R / P L L BA[2:0] A[15:0] RAS_n CAS_n WE_n CKE[1:0] ODT[1:0] RBA[2:0]A → BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RBA[2:0]B → BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[15:0]A → A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RA[15:0]B → A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RRASA_n → RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCASA_n → CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RWEA_n → WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A → CKE[1:0]A_n: SDRAMs D[3:0], D8. D[12:9], D17 RCKE0B → CKE[1:0]B_n: SDRAMs D[21:18], D26, D[30:27], D35 RODT[1:0]A → ODT0: SDRAMs D[3:0], D8. D[12:9], D17 RODT[1:0]B → ODT0: SDRAMs D[21:18], D26, D[30:27], D35 CK0A_t_R0 → CK-t: SDRAMs D[3:0], D8, D[21:18], D26 CK0B_t_R0 → CK_t: SDRAMs D[7:4], D[25:22] CK0A_t_R1 → CK-t: SDRAMs D[12:9], D17, D[30:27], D35 CK0B_t_R1 → CK_t: SDRAMs D[16:13], D[34:31] CK0A_c_R0 → CK_c: SDRAMs D[3:0], D8, D[21:18], D26 CK0B_c_R0 → CK_c: SDRAMs D[7:4], D[25:22] CK0A_c_R1 → CK_c: SDRAMs D[12:9], D17, D[30:27], D35 CK0B_c_R1 → CK_c: SDRAMs D[16:13], D[34:31] CK0_t 120Ω CK0_c CK1_t RS0A_n → CS0A_n: SDRAMs D[3:0], D8, D[12:9], D17 RS1A_n → CS1A_n: SDRAMs D[21:18], D26, D[30:27], D35 RS0B_n → CS0B_n: SDRAMs D[7:4], D[16:13] RS1B_n → CS1B_n: SDRAMs D[25:22], D[34:31] 120Ω CK1_c PAR_IN Err_Out_n RESET_n * S[3:2]_n are NC RST_n RST_n: All SDRAMs (Note: Otherwise stated differently all resistors values on this base are 22Ω+-5%) Rev. 0.2 / December 2008 15 3.4 4GB, 512Mx72 Module(2Rank of x4) VSS RS0_n RS1_n DM CS_n ZQ DQS0_t DQS0_c DQ[3:0] DQS_t DQS_c DQ [3:0] DQS1_t DQS1_c DQ[11:8] DQS_t DQS_c DQ [3:0] DQS2_t DQS2_c DQ[16:19] DQS_t DQS_c DQ [3:0] DQS3_t DQS3_c DQ[24:27] DQS_t DQS_c DQ [3:0] DQS4_t DQS4_c DQ[32:35] DQS_t DQS_c DQ [3:0] DQS5_t DQS5_c DQ[40:43] DQS_t DQS_c DQ [3:0] DQS6_t DQS6_c DQ[48:51] DQS_t DQS_c DQ [3:0] DQS7_t DQS7_c DQ[56:59] DQS_t DQS_c DQ [3:0] DQS8_t DQS8_c CB[3:0] DQS_t DQS_c DQ [3:0] VSS DM CS_n ZQ VSS VSS DM CS_n ZQ VSS DM CS_n ZQ VSS DM CS_n ZQ VSS DM CS_n ZQ VSS D6 DM CS_n ZQ VSS DM CS_n ZQ D8 VSS DQS12_t DQS12_c DQ[28:31] DQS_t DQS_c DQ [3:0] DQS13_t DQS13_c DQ[36:39] DQS_t DQS_c DQ [3:0] DQS14_t DQS14_c DQ[44:47] DQS_t DQS_c DQ [3:0] DQS15_t DQS15_c DQ[52:55] DQS_t DQS_c DQ [3:0] DQS16_t DQS16_c DQ[60:63] DQS_t DQS_c DQ [3:0] DQS17_t DQS17_c CB[7:4] DQS_t DQS_c DQ [3:0] DM CS_n ZQ DM CS_n ZQ DM CS_n ZQ EVENT SCL SDA VDDSPD VSS VSS DM CS_n ZQ VSS DM CS_n ZQ VSS D15 DM CS_n ZQ VSS DM CS_n ZQ D17 VSS SPD SA0 VDD D0–D17 EVENT SPD with SA1 Integrated SA2 SCL TS VSS SDA SA1 VTT VREFCA D0–D17 VREFDQ D0–D17 VSS D0–D17 SA2 Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative VSS D35 SA0 VSS VSS D34 DM CS_n ZQ DQS_t DQS_c DQ [3:0] VSS D33 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D16 VSS D32 DM CS_n ZQ DQS_t DQS_c DQ [3:0] VSS D31 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D14 VSS D30 DM CS_n ZQ DQS_t DQS_c DQ [3:0] VSS D29 DM CS_n ZQ DQS_t DQS_c DQ [3:0] VSS D28 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D13 VDDSPD VDDSPD VSS VSS D27 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D12 VSS D26 VSS D11 VSS D25 DM CS_n ZQ DQS_t DQS_c DQ [3:0] DQS_t DQS_c DQ [3:0] DM CS_n ZQ DQS_t DQS_c DQ [3:0] D10 VSS D24 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D7 DQS11_t DQS11_c DQ[20:23] DM CS_n ZQ VSS D23 DM CS_n ZQ DQS_t DQS_c DQ [3:0] DQS_t DQS_c DQ [3:0] VSS D22 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D5 DQS10_t DQS10_c DQ[12:15] VSS D9 VSS D21 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D4 DQS_t DQS_c DQ [3:0] VSS D20 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D3 DM CS_n ZQ DQS9_t DQS9_c DQ[7:4] VSS D19 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D2 VSS D18 DM CS_n ZQ DQS_t DQS_c DQ [3:0] D1 DM CS_n ZQ DM CS_n ZQ DQS_t DQS_c DQ [3:0] D0 Note: 1. DQ-to-I/O wiring may be changed within a nibble. 2. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms. Rev. 0.2 / December 2008 16 S0_n 1:2 S1_n R E G I S T E R / P L L BA[2:0] A[15:0] RAS_n CAS_n WE_n CKE[1:0] ODT[1:0] RBA[2:0]A → BA[2:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RBA[2:0]B → BA[2:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RA[15:0]A → A[15:0]: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RA[15:0]B → A[15:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RRASA_n → RAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RRASB_n → RAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCASA_n → CAS_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RCASB_n → CAS_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RWEA_n → WE_n: SDRAMs D[3:0], D8, D[12:9], D17, D[21:18], D26, D[30:27], D35 RWEB_n → WE_n: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31] RCKE0A → CKE[1:0]A_n: SDRAMs D[3:0], D8. D[12:9], D17 RCKE0B → CKE[1:0]B_n: SDRAMs D[21:18], D26, D[30:27], D35 RODT[1:0]A → ODT0: SDRAMs D[3:0], D8. D[12:9], D17 RODT[1:0]B → ODT0: SDRAMs D[21:18], D26, D[30:27], D35 CK0A_t_R0 → CK_t: SDRAMs D[3:0], D8, D[21:18], D26 CK0B_t_R0 → CK_t: SDRAMs D[7:4], D[25:22] CK0A_t_R1 → CK_t: SDRAMs D[12:9], D17, D[30:27], D35 CK0B_t_R1 → CK_t: SDRAMs D[16:13], D[34:31] CK0_t 120Ω CK0A_c_R0 → CK_c: SDRAMs D[3:0], D8, D[21:18], D26 CK0B_c_R0 → CK_c: SDRAMs D[7:4], D[25:22] CK0A_c_R1 → CK_c: SDRAMs D[12:9], D17, D[30:27], D35 CK0B_c_R1 → CK_c: SDRAMs D[16:13], D[34:31] CK0_c CK1_t RS0A_n → CS0A_n: SDRAMs D[3:0], D8, D[12:9], D17 RS1A_n → CS1A_n: SDRAMs D[21:18], D26, D[30:27], D35 RS0B_n → CS0B_n: SDRAMs D[7:4], D[16:13] RS1B_n → CS1B_n: SDRAMs D[25:22], D[34:31] 120Ω CK1_c PAR_IN Err_Out_n RESET_n * S[3:2]_n are NC RST_n RST_n: All SDRAMs (Note: Otherwise stated differently all resistors values on this base are 22Ω+-5%) Rev. 0.2 / December 2008 17 4. Pin Capacitance (VDD=1.5V, VDDQ=1.5V) 1GB: HMT112V7AFP8C Pin Symbol Min Max Unit CK0, CK0 CCK TBD TBD pF CKE, ODT CI1 TBD TBD pF CS CI2 TBD TBD pF CI3 TBD TBD pF CIO TBD TBD pF Symbol Min Max Unit CK0, CK0 CCK TBD TBD pF CKE, ODT CI1 TBD TBD pF CS CI2 TBD TBD pF Address, RAS, CAS, WE CI3 TBD TBD pF DQ, DM, DQS, DQS CIO TBD TBD pF Symbol Min Max Unit CK0, CK0 CCK TBD TBD pF CKE, ODT CI1 TBD TBD pF CS CI2 TBD TBD pF Address, RAS, CAS, WE CI3 TBD TBD pF DQ, DM, DQS, DQS CIO TBD TBD pF Symbol Min Max Unit CK0, CK0 CCK TBD TBD pF CKE, ODT CI1 TBD TBD pF CS CI2 TBD TBD pF Address, RAS, CAS, WE CI3 TBD TBD pF DQ, DM, DQS, DQS CIO TBD TBD pF Address, RAS, CAS, WE DQ, DM, DQS, DQS 2GB: HMT125V7AFP8C Pin 2GB: HMT125V7AFP4C Pin 4GB: HMT351V7AMP4C Pin Note: 1. Pins not under test are tied to GND. 2. These value are guaranteed by design and tested on a sample basis only. Rev. 0.2 / December 2008 18 5. IDD Specifications (Tcase: 0 to 95oC) 1GB, 128M x 72 R-DIMM: HMT112V7AFP8C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 DDR3 800 1484 1664 1259 1304 1502 318 462 1259 1349 498 2024 1304 2204 2474 318 336 336 2654 DDR3 1066 1592 1799 1349 1394 1502 318 480 1349 1439 588 2294 1304 2564 2564 318 336 336 3014 DDR3 1333 1664 1889 1439 1484 1502 318 498 1439 1529 633 2654 1304 2834 2654 318 336 336 3464 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note note 2GB, 256M x 72 R-DIMM: HMT125V7AFP8C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P DDR3 800 1979 2159 1754 1844 2240 408 696 1754 1934 798 DDR3 1066 2177 2384 1934 2024 2240 408 732 1934 2114 948 DDR3 1333 2399 2564 2114 2204 2240 408 768 2114 2294 1038 Unit mA mA mA mA mA mA mA mA mA mA IDD4R IDDQ4R IDD4W IDD5B IDD6 IDD6ET IDD6TC IDD7 2519 1799 2699 2969 408 444 444 3149 2879 1889 3149 3149 408 444 444 3599 3329 1979 3509 3329 408 444 444 4139 mA mA mA mA mA mA mA mA Rev. 0.2 / December 2008 19 2GB, 256M x 72 R-DIMM: HMT125V7AFP4C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 DDR3 800 2204 2564 1754 1844 2240 408 696 1754 1934 768 3284 1844 3644 4184 408 444 444 4544 DDR3 1066 2420 2834 1934 2024 2240 408 732 1934 2114 948 3824 1844 4364 4364 408 444 444 5264 DDR3 1333 2564 3014 2114 2204 2240 408 768 2114 2294 1038 4544 1844 4904 4544 408 444 444 6164 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note DDR3 1066 3590 4004 3104 3284 3716 588 1236 3104 3464 1668 4994 3014 5534 5534 588 660 660 6434 DDR3 1333 3914 4364 3464 3644 3716 588 1308 3464 3824 1848 5894 3194 6254 5894 588 660 660 7514 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA note 4GB, 512M x 72 R-DIMM: HMT351V7AMP4C Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT IDD2P0 IDD2P1 IDD2Q IDD3N IDD3P IDD4R IDDQ4R IDD4W IDD5B IDD6 IDDET IDD6TC IDD7 Rev. 0.2 / December 2008 DDR3 800 3194 3554 2744 2924 3716 588 1164 2744 3104 1308 4274 2834 4634 5174 588 660 660 5534 20 6. Dimm Outline Diagram 6.1 128Mx72 - HMT112V7AFP8C 6.1 128Mx72 - HMT112R7AFP8C Front 14.90 2.10 ± 0.15 Detail C 13.60 18.75 ± 0.15 Registering Clock Driver 3 ± 0.1 3 ± 0.1 15.80 ± 0.1 1 8.00 ± 0.1 120 2X3.0 ± 0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 SPD/TS Back 240 121 Side Detail of Contacts B Detail of Contacts A 0.80 ± 0.05 Detail of Contacts C 2.50 3.65mm max 14.90 2.50 ± 0.20 0.3 ± 0.15 3.80 0.20 2.50 ± 0.20 0.4 13.60 0.3~0.1 1.00 1.50 ± 0.10 5.00 1.27 ± 010mm max Rev. 0.2 / December 2008 21 6.2 256Mx72 - HMT125V7AFP8C Front 14.90 2.10 ± 0.15 Detail C 13.60 18.75 ± 0.15 Registering Clock Driver 3 ± 0.1 3 ± 0.1 15.80 ± 0.1 1 8.00 ± 0.1 120 2X3.0 ± 0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 SPD/TS Back 240 121 Side Detail of Contacts B Detail of Contacts A 0.80 ± 0.05 Detail of Contacts C 2.50 3.65mm max 14.90 2.50 ± 0.20 0.3 ± 0.15 3.80 0.20 2.50 ± 0.20 0.4 13.60 0.3~0.1 1.00 1.50 ± 0.10 5.00 1.27 ± 010mm max Rev. 0.2 / December 2008 22 6.3 256Mx72 - HMT125V7AFP4C Front 14.90 2.10 ± 0.15 Detail C 13.60 18.75 ± 0.15 Registering Clock Driver 3 ± 0.1 3 ± 0.1 15.80 ± 0.1 1 8.00 ± 0.1 120 2X3.0 ± 0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 SPD/TS Back 240 121 Side Detail of Contacts B Detail of Contacts A 0.80 ± 0.05 Detail of Contacts C 2.50 3.65mm max 14.90 2.50 ± 0.20 0.3 ± 0.15 3.80 0.20 2.50 ± 0.20 0.4 13.60 0.3~0.1 1.00 1.50 ± 0.10 5.00 1.27 ± 010mm max Rev. 0.2 / December 2008 23 6.4 512Mx72 - HMT351V7AMP4C Front 14.90 2.10 ± 0.15 Detail C 13.60 18.75 ± 0.15 1 15.80 ± 0.1 DDP DDP DDP DDP Registering Clock Driver DDP DDP DDP 3 ± 0.1 DDP DDP 3 ± 0.1 8.00 ± 0.1 120 2X3.0 ± 0.10 47.00 5.175 71.00 Detail B Detail A 128.95 133.35 240 DDP DDP DDP DDP DDP SPD/TS DDP DDP DDP DDP Back 121 Detail of Contacts B Detail of Contacts A Detail of Contacts C Side 3.95mm max 0.80 ± 0.05 2.50 14.90 2.50 ± 0.20 0.3 ± 0.15 3.80 0.20 2.50 ± 0.20 0.4 13.60 0.3~0.1 1.00 1.50 ± 0.10 5.00 Rev. 0.2 / December 2008 1.27 ± 010mm max 24 6.4 512Mx72 - HMT351V7AMP4C Front 36.58 36.58 18.75 ± 0.15 DDP DDP DDP DDP DDP DDP DDP DDP DDP SPD/TS 12.3 13.3 1 120 126.8 DDP DDP DDP DDP DDP SPD/TS DDP DDP DDP DDP Back 240 121 Detail of Contacts B Detail of Contacts A 0.80 ± 0.05 Detail of Contacts C Side 9.35mm max 2.50 14.90 2.50 ± 0.20 0.3 ± 0.15 3.80 0.20 2.50 ± 0.20 0.4 13.60 0.3~0.1 1.00 1.50 ± 0.10 5.00 Rev. 0.2 / December 2008 2.15mm 1.27 ± 010mm max 25