MC100LVEL11 3.3V ECL 1:2 Differential Fanout Buffer Description The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the LVEL11 is ideally suited for those applications which require the ultimate in AC performance. The differential inputs of the LVEL11 employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open (pulled to VEE) the Q outputs will go LOW. Features • • • • • • • • • www.onsemi.com MARKING DIAGRAMS* 8 8 1 KVL11 ALYW G SOIC−8 D SUFFIX CASE 751 330 ps Propagation Delay 5 ps Skew Between Outputs High Bandwidth Output Transitions The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −3.8 V Internal Input Pulldown Resistors on D, Pullup and Pulldown Resistors on D Q Output will Default LOW with Inputs Open or at VEE These Devices are Pb−Free and are RoHS Compliant 1 8 8 1 KV11 ALYWG G TSSOP−8 DT SUFFIX CASE 948R 1 1 3ZMG G 1 DFN8 MN SUFFIX CASE 506AA Q0 1 8 VCC Q0 2 7 D Q1 3 6 D A L Y W M G = Assembly Location = Wafer Lot = Year = Work Week = Date Code = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Q1 4 5 VEE ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Figure 1. Logic Diagram and Pinout Assignment © Semiconductor Components Industries, LLC, 2015 January, 2015 − Rev. 13 1 Publication Order Number: MC100LVEL11/D MC100LVEL11 Table 1. PIN DESCRIPTION ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin Function Q0, Q0; Q1, Q1 ECL Data Outputs D, D ECL Data Inputs VCC Positive Supply VEE Negative Supply EP (DFN8 only) Thermal exposed pad must be connected to a sufficient thermal conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open. Table 2. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 kW Internal Input Pullup Resistor 75 kW ESD Protection Human Body Model Machine Model Charge Device Model > 4 KV > 400 V > 2 kV Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) SOIC−8 TSSOP−8 DFN8 Level 1 Level 3 Level 1 Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in Transistor Count 63 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Rating Units VCC Symbol PECL Mode Power Supply Parameter VEE = 0 V Condition 1 8 to 0 V VEE NECL Mode Power Supply VCC = 0 V −8 to 0 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 to 0 −6 to 0 V Iout Output Current Continuous Surge 50 100 mA mA TA Operating Temperature Range −40 to +95 °C Tstg Storage Temperature Range −65 to +150 °C qJA Thermal Resistance (Junction−to−Ambient) 0 lpfm 500 lpfm SOIC−8 SOIC−8 190 130 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board SOIC−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lpfm 500 lpfm TSSOP−8 TSSOP−8 185 140 °C/W °C/W qJC Thermal Resistance (Junction−to−Case) Standard Board TSSOP−8 41 to 44 ± 5% °C/W qJA Thermal Resistance (Junction−to−Ambient) 0 lfpm 500 lfpm DFN8 DFN8 129 84 °C/W °C/W Tsol Wave Solder <2 to 3 sec @ 260°C 265 °C qJC Thermal Resistance (Junction−to−Case) 35 to 40 °C/W Pb−Free (Note 2) Condition 2 VI VCC VI VEE DFN8 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) www.onsemi.com 2 MC100LVEL11 Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 3) −40°C Symbol Characteristic Min 25°C Typ Max 24 28 Min 95°C Typ Max 24 28 Min Typ Max Unit 25 30 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 4) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV VOL Output LOW Voltage (Note 4) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV VIH Input HIGH Voltage (Single−Ended) 2135 2420 2135 2420 2135 2420 mV VIL Input LOW Voltage (Single−Ended) 1490 1825 1490 1825 1490 1825 mV VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 8) Vpp < 500 mV Vpp y 500 mV 1.2 3.1 1.1 3.1 1.1 3.1 V 1.4 3.1 1.3 3.1 1.3 3.1 V 150 mA IIH Input HIGH Current IIL Input LOW Current 150 D D 150 0.5 −600 0.5 −600 mA mA 0.5 −600 NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 3. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 5. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V. Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 6) −40°C Symbol Characteristic Min 25°C Typ Max 24 28 Min 95°C Typ Max 24 28 Min Typ Max Unit 25 30 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 7) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV VOL Output LOW Voltage (Note 7) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −880 −1165 −880 −1165 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV −2.1 −0.2 −2.2 −0.2 −2.2 −0.2 V −1.9 −0.2 −2.0 −0.2 −2.0 −0.2 V 150 mA VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 8) Vpp < 500 mV Vpp y 500 mV IIH Input HIGH Current IIL Input LOW Current 150 D D 0.5 −600 150 0.5 −600 0.5 −600 mA mA NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 6. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V. 7. Outputs are terminated through a 50 W resistor to VCC − 2.0 V. 8. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between VPPmin and 1.0 V. www.onsemi.com 3 MC100LVEL11 Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 9) −40°C Symbol Characteristic Min Typ 25°C Max Min fmax Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output tSKEW Within-Device Skew (Note 10) Device−to−Device (Note 11) Duty Cycle Skew (Note 12) tJITTER Random Clock Jitter (RMS) VPP Input Swing (Note 13) 200 1000 200 tr tf Output Rise/Fall Times Q (20% − 80%) 120 320 120 Typ 95°C Max Min Typ Max 1.0 235 385 5 10 255 20 150 20 GHz 330 405 5 10 20 150 20 285 5 10 435 ps 20 150 20 ps 0.6 220 Unit ps 1000 200 1000 mV 320 120 320 ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 9. VEE can vary ±0.3 V. 10. Within-device skew defined as identical transitions on similar paths through a device. 11. Device−to−device skew for identical transitions at identical VCC levels. 12. Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device. 13. VPP(min) is the minimum input swing for which AC parameters guaranteed. The device will function properly with input swings below 200 mV, however, AC delays may move outside of the specified range. The device has a DC gain of ≈40. 800 VOUT(PP)(mV) 600 400 200 0 0 200 400 600 800 1000 1200 1400 f (MHz) Figure 2. Output Swing versus Frequency www.onsemi.com 4 1600 1800 2000 MC100LVEL11 ORDERING INFORMATION Package Shipping† MC100LVEL11DG SOIC−8 (Pb−Free) 98 Units / Rail MC100LVEL11DR2G SOIC−8 (Pb−Free) 2500 / Tape & Reel MC100LVEL11DTG TSSOP−8 (Pb−Free) 100 Units / Rail MC100LVEL11DTR2G TSSOP−8 (Pb−Free) 2500 / Tape & Reel MC100LVEL11MNR4G DFN8 (Pb−Free) 1000 / Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices www.onsemi.com 5 MC100LVEL11 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. −X− A 8 5 S B 0.25 (0.010) M Y M 1 4 K −Y− G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. www.onsemi.com 6 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 MC100LVEL11 PACKAGE DIMENSIONS TSSOP−8 DT SUFFIX CASE 948R−02 ISSUE A 8x 0.15 (0.006) T U K REF 0.10 (0.004) S 2X L/2 8 1 PIN 1 IDENT S T U S V NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. S 5 0.25 (0.010) B −U− L 0.15 (0.006) T U M M 4 A −V− F DETAIL E C 0.10 (0.004) −T− SEATING PLANE D −W− G DETAIL E www.onsemi.com 7 DIM A B C D F G K L M MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ MC100LVEL11 PACKAGE DIMENSIONS DFN8 2x2, 0.5P CASE 506AA ISSUE E D 0.10 C 0.10 C DETAIL A E OPTIONAL CONSTRUCTIONS TOP VIEW A DETAIL B DIM A A1 A3 b D D2 E E2 e K L L1 ÉÉ ÉÉ EXPOSED Cu 0.10 C 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 ÇÇ ÇÇ PIN ONE REFERENCE 2X A B MOLD CMPD DETAIL B OPTIONAL CONSTRUCTION 0.08 C (A3) NOTE 4 A1 C SIDE VIEW SEATING PLANE MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.20 0.30 2.00 BSC 1.10 1.30 2.00 BSC 0.70 0.90 0.50 BSC 0.30 REF 0.25 0.35 −−− 0.10 RECOMMENDED SOLDERING FOOTPRINT* DETAIL A 8X D2 1 8X 1.30 L PACKAGE OUTLINE 4 E2 K 8 5 8X e/2 e 0.50 0.90 b 2.30 1 0.10 C A B 0.05 C 8X 0.30 NOTE 3 BOTTOM VIEW 0.50 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ECLinPS Plus is a trademark of Semiconductor Components Industries, LLC. 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