LINER LTC1559 36v, low loss dual powerpath controllers for large pfet Datasheet

LTC4416/LTC4416-1
36V, Low Loss Dual
PowerPath Controllers for
Large PFETs
DESCRIPTIO
FEATURES
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Designed Specifically to Drive Large and Small QG
PFETs
Very Low Loss Replacement for Power Supply
OR’ing Diodes
Wide Operating Voltage Range: 3.6V to 36V
–40°C to 125°C Operating Temperature Range
Reverse Battery Protection
Automatic Switching Between DC Sources
Low Quiescent Current: 35µA per Channel
Load Current Sharing
MOSFET Gate Protection Clamp
Precision Input Control Comparators for Setting
Switchover Threshold Points
Open-Drain Feedback Points for Customer Specified
Hysteresis Control
Minimal External Components
Space Saving 10-Lead MSOP Package
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APPLICATIO S
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High Current PowerPath Switch
Industrial and Automotive Applications
Uninterruptible Power Supplies
Logic Controlled Power Switch
Battery Backup System
Emergency Systems with Battery Backups
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V1
8.0
SUP75P03_07
cURRENT (A)
LTC4416
GND
24.9k
VIN
221k
3.6
LTc4416
VTH2 WITH
HYSTERESIS
VTH1 WITH
HYSTERESIS
75k
182k
LTC4416-1
H1
G1
E1
V1
GND
G1
E2
VS
H2
G2
E2
V2
H1
V2
H2
G2
V2
BACKUP SUPPLY SUP75P03_07
cONSTANT
VOLTAGE
VS
4416 TA01
V2 = 10.8V
Under and Overvoltage Shutdown Operation
cONSTANT
RON
221k
187k
The LTC4416/LTC4416-1 are available in low profile 10-lead
MSOP packages.
LTC4416 vs Schottky Diode
Forward Voltage Drop
Automatic PowerPath Switchover
V1 = 12V (FAIL)
V1 = 13.5V (RESTORE) PRIMARY SUPPLY
The LTC4416 integrates two interconnected PowerPathTM
controllers with soft switchover control. The “soft-off”
switchover permits the users to transfer between two dissimilar voltages without excessive voltage undershoot (or
VDROOP) in the output supply. The LTC4416/LTC4416-1 also
contain a “fast-on” feature that dramatically increases gate
drive current when the forward input voltage exceeds 25mV.
The LTC4416 “fast off” feature is engaged when the sense
voltage exceeds the input voltage by 25mV. The LTC4416-1
enables the fast off under the same conditions and when
the other external P-channel device is selected using the
enable pins.
The wide operating supply range supports operation from one
to eight Li-Ion cells in series. The low quiescent current (35µA
per channel) is independent of the load current. The gate driver
includes an internal voltage clamp for MOSFET protection.
, LT, LTc and LTM are registered trademarks of Linear Technology corporation.
PowerPath is a trademark of Linear Technology corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATIO
The LTC ®4416/LTC4416-1 control two sets of external
P-channel MOSFETs to create two near ideal diode functions
for power switchover circuits. This permits highly efficient
OR’ing of multiple power sources for extended battery life
and low self heating. When conducting, the voltage drop
across the MOSFET is typically 25mV. For applications with
a wall adapter or other auxiliary power source, the load is
automatically disconnected from the battery when the auxiliary source is connected.
0
24.9k
ScHOTTKY
DIODE
0.02
FORWARD VOLTAGE (V)
GND
0.5
4416 TA01b
187k 24.3k
E1
V1
GND
VS
VOUT
TO
LOAD
4416 TA01c
UV ENABLED AT 5V, VIN RESTORED TO LOAD WHEN VIN RISES TO 5.5V
OV ENABLED AT 13.5V, VIN RESTORED TO LOAD WHEN VIN FALLS TO 12V
4416fa
LTC4416/LTC4416-1
W W
W
(Note 1)
AXI U RATI GS
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ABSOLUTE
Supply Voltage (V1, V2)............................... –14V to 40V
Voltage from V1 or V2 to VS........................ –40V to 40V
Input Voltage
E1, E2..................................................... –0.3V to 40V
VS............................................................ –14V to 40V
Output Voltage
G1........ –0.3V to the Higher of V1 + 0.3V or VS + 0.3V
G2........ –0.3V to the Higher of V2 + 0.3V or VS + 0.3V
H1, H2...................................................... –0.3V to 7V
Operating Ambient Temperature Range (Note 2)
LTC4416E............................................. –40°C to 85°C
LTC4416I............................................ –40°C to 125°C
Operating Junction
Temperature Range................................. –40°C to 125°C
Storage Temperature Range.................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec)................... 300°C
U
W
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
H1
E1
GND
E2
H2
10
9
8
7
6
1
2
3
4
5
G1
V1
VS
V2
G2
MS PACKAGE
10-LEAD PLASTIC MSOP
TJMAX = 130°C, θJA = 120°C/W
Order part number
MS part marking*
LTC4416EMS
LTC4416IMS
LTC4416EMS-1
LTC4416IMS-1
ltcfc
LTCFC
LTCPS
LTCPS
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = V2 = 12V, E1 = 2V, E2 = GND, GND = 0V. Current into a pin is
positive and current out of a pin is negative. All voltages are referenced to GND, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
VV1, VV2,
VVS
IQFL
Operating Supply Range
IQFH
Quiescent Supply Current at High Supply
While in Forward Regulation
IQRL
Quiescent Supply Current at Low Supply
While in Reverse Turn-Off
Quiescent Supply Current at High Supply
While in Reverse Turn-Off
Quiescent Supply Current at Low Supply
with E1 and E2 Active
Quiescent Supply Current at High Supply
with E1 and E2 Active
V1, V2 and VS Pin Leakage Currents
When Other Pin Supplies Power (Note 4)
V1, V2 and/or VS Must be in This Range for Proper
Operation
VV1 = 3.6V, VV2 = 3.6V. Measure Combined Current
at V1, V2 and VS Pins Averaged with VVS = 3.560V
and VVS = 3.6V (Note 3)
VV1 = 36V, VV2 = 36V. Measure Combined Current
at V1, V2 and VS Pins Averaged with VVS = 35.960V
and VVS = 36V (Note 3)
VV1 = 3.6V, VV2 = 3.6V. Measure Combined Current
at V1, V2 and VS Pins with VVS = 3.7V
VV1 = 35.9V, VV2 = 35.9V. Measure Combined
Current at V1, V2 and VS Pins with VVS = 36V
VV1 = 3.6V, VV2 = 3.6V, VV1 – VVS = 0.9V,
VE1 = 0V, VE2 = 2V, V1 and V2 Measured Separately
VV1 = 36V, VV2 = 36V, VV1 – VVS = 0.9V,
VE1 = 0V, VE2 = 2V, V1 and V2 Measured Separately
VV1 = VV2 = 28V, VVS = 0V. Measure IVS
IQRH
IQCL
IQCH
ILEAK
Quiescent Supply Current at Low Supply
While in Forward Regulation
MIN
TYP
UNITS
36
V
●
70
µA
●
130
µA
●
70
µA
●
130
µA
●
30
µA
l
65
µA
●
3.6
MAX
–10
–1
1
µA
VV1 = VV2 = 14V, VVS = –14V. Measure IVS
–10
–1
1
µA
VV1 = VV2 = 36V, VVS = 8V. Measure IVS
–10
–1
1
µA
PowerPath Controller
VFR
VRTO
VFO
PowerPath Switch Forward Regulation
Voltage
PowerPath Switch Reverse Turn-Off
Threshold Voltage
PowerPath Switch Forward Fast-On
Voltage Comparator Threshold
VV1, VV2 – VVS, 3.6V ≤ VV1, VV2 ≤ 36V,
CG1 = CG2 = 3nF
VV1, VV2 – VVS, 3.6V ≤ VV1, VV2 ≤ 36V,
CG1 = CG2 = 3nF
VV1, VV2 – VVS, 6V ≤ VV1, VV2 ≤ 36V,
CG1 = CG2 = 3nF, IG1, IG2 > 500µA
l
10
40
mV
l
–40
–10
mV
l
50
125
mV
4416fa
LTC4416/LTC4416-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V1 = V2 = 12V, E1 = 2V, E2 = GND, GND = 0V. Current into a pin is
positive and current out of a pin is negative. All voltages are referenced to GND, unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
–9
15
500
l
TYP
MAX
UNITS
–2
200
G1, G2 Controller
IG(SRC)
IG(SNK)
IG(FO)
IG(OFF)
VG(ON)
GATE Active Forward Regulation
Source Current
Sink Current
Sink Current During Fast-On
Source Current During Fast-Off
G1 and G2 Clamp Voltage
VG(OFF)
G1 and G2 Off Voltage
tG(ON)
G1 and G2 Turn-On Time
(Note 5)
(Note 6)
(Note 7)
(Note 12)
Apply IG1 = IG2 = 2µA, VV1 = VV2 = 12V,
VVS = 11.8V, Measure VV1 – VG1 or VV2 – VG2
Apply IG1 = IG2 = –30µA, VV1 = VV2 = 12V,
VVS = 12.2V, Measure VV1 – VG1 or VV2 – VG2
VGS < –6V, CG = 17nF (Note 8)
tG(OFF)
G1 and G2 Turn-Off Time
tE(OFF)
Enable Comparator Turn-Off Delay
8.25
–500
9.1
µA
µA
µA
µA
V
0.350
0.920
V
l
60
µs
VGS > –1.5V, CG = 17nF (Note 9)
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30
µs
(Note 14) LTC4416-1 Only
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6
µs
1
µA
100
mV
7.4
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H1 and H2 Open-Drain Drivers
IH(OFF)
H1 and H2 Off Current
3.6V ≤ VV1, VV2 ≤ 36V (Note 10)
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–1
VH(ON)
H1 and H2 On Voltage
3.6V ≤ VV1, VV2 ≤ 36V (Note 10)
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tH(ON)
H1 and H2 Turn-On Time
(Note 11)
5
µs
tH(OFF)
H1 and H2 Turn-Off Time
(Note 11)
10
µs
1.240
1.240
100
V
V
nA
E1 and E2 Enable Input Comparators
VREF
E1 and E2 Input Threshold Voltage
IE
E1 and E2 Input Leakage Current
IG(ENOFF)
Source Current When Other Channel
Enabled (Note 13)
LTC4416
LTC4416-1
3.6V ≤ VV1, VV2 ≤ 36V, –40°C to 85°C
4V ≤ VV1, VV2 ≤ 36V, –40°C to 125°C
0V ≤ VE1, VE2 ≤ 1.5V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC4416E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC4416I is guaranteed and tested
over the –40°C to 125°C operating temperature range.
Note 3: This results in the same supply current as would be observed with
an external P-channel MOSFET connected to the LTC4416 and operating in
forward regulation.
Note 4: Only 3 of 9 permutations illustrated. This specification is the same
when power is provided through VS or V2. This specification is only valid
when V1, V2 and VS are within 28V of each other.
Note 5: V1 and V2 are held at 12V and G1 and G2 are forced to 9V. VS is
set at 12V to measure the source current at either G1 or G2.
Note 6: V1 and V2 are held at 12V and G1 and G2 are forced to 9V. VS is
set at 11.96V to measure the sink current at either G1 or G2.
Note 7: V1 and V2 are held at 12V and G1 and G2 are forced to 9V. VS is
set at 11.875V to measure the sink current at either G1 or G2.
l
1.180
1.180
–100
1.215
1.215
–9
–500
–3
µA
µA
Note 8: V1 and V2 are held at 12V and VS is stepped from 12.2V to 11.8V
to trigger the event. G1 and G2 voltages are initially VG(OFF).
Note 9: V1 and V2 are held at 12V and VS is stepped from 11.8V to 12.2V
to trigger the event. G1 and G2 voltages are initially VG(ON).
Note 10: H1 and H2 are forced to 2V. E1 and E2 are forced to 1.5V to
measure the off current of H1 and H2. H1 and H2 are forced with 1mA to
measure the on voltage of H1 and H2.
Note 11: H1 and H2 are forced to 2V. E1 and E2 are stepped from 1.3V
to 1.1V to measure tS(ON). E1 and E2 are stepped from 1.1V to 1.3V to
measure tS(OFF).
Note 12: V1 and V2 are held at 12V and G1 and G2 are forced to 9V. VS is
set to 12.05V to measure the source current at either G1 or G2.
Note 13: V1 and V2 are held at 12V and G1 and G2 are forced to 9V. VS
is set to 12V to measure the source current at either G1 or G2 when the
channel is deselected.
Note 14: V1 and V2 are held at 12V, VS = 11.96V and G1 and G2 have a 4k
resistor each to 9V. Measure the delay after the channel is disabled until
the gate signal begins to pull high.
4416fa
LTC4416/LTC4416-1
TYPICAL PERFOR A CE CHARACTERISTICS
U W
VFR vs Temperature and Supply
Voltage
VRTO vs Temperature and Supply
Voltage
–20
40
30
125°C
–22
CURRENT (A)
VRTO (mV)
27°C
27°C
–23
125°C
25
5
10 15 20 25 30
SUPPLY VOLTAGE (V)
35
–25
40
0
25 30
10 15 20
SUPPLY VOLTAGE (V)
5
4416 G01
VGn(OFF) vs Temperature and IGn
0.50
0.40
IVS: VV1, VV2 – VVS = 28V
8.65
VIN = 36V
8.55
100
TEMPERATURE (°C)
150
8.25
–50
0
50
50
100
TEMPERATURE (°C)
150
4416 G06
tG(OFF) vs Temperature
55
CGn = 15nF
VVS = VVIN – 200mV
10V ≤ VV1
VV2 ≤ 36V
50
45
tG(OFF) (µs)
tG(ON) (µs)
0
4416 G05
tG(ON) vs Temperature
tG(ON) (µs) AT 10V
50
tG(ON) (µs) AT 36V
25
tG(OFF) (µs) AT 36V
40
35
tG(OFF) (µs) AT 10V
30
25
CGn = 15nF
VVS = VVIN + 200mV
10V ≤ VV1
VV2 ≤ 36V
20
0
IGn = 0µA
0
–50
150
100
TEMPERATURE (°C)
4416 G04
0
–50
IGn = –10µA
0.20
0.10
8.35
75
0.30
8.45
–1.25
100
3.6V ≤ VV1
VV2 ≤ 36V
VVS = VVIN + 200mV
IGn = –20µA
VIN = 10V
VGn(OFF) (V)
IV2: VV1, VVS – VV2 = 28V
50
25 50 75 100 125 150
TEMPERATURE (°C)
8.75
VGn(ON) (V)
CURRENT (µA)
IV1: VV2, VVS – VV1 = 28V
0
0
4416 G03
IGn = 2µA
VV1 = VV2 = VVIN
VVS = VVIN – 200mV
8.85
–1.00
–1.50
–50
0.80
–50 –25
40
VGn(ON) vs Temperature and VIN
8.95
–0.25
–0.75
35
NORMALIZED AT
VIN = 3.6V
VIN = 20V
VIN = 36V
4416 G02
V1, V2 and VS Pin Leakage vs
Temperature
–0.50
1.00
0.90
–24
0
VV1 = VV2 = VVS = VVIN
3.6V ≤ VVIN ≤ 36V
1.10
–40°C
–40°C
VFR (mV)
1.20
–21
35
20
Normalized Quiescent Supply
Current vs Temperature
50
100
TEMPERATURE (°C)
150
4416 G07
15
–50
0
50
100
TEMPERATURE (°C)
150
4416 G08
4416fa
LTC4416/LTC4416-1
PI FU CTIO S
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U
U
H1 (Pin 1): Open-Drain Comparator Output of the E1 Pin.
If E1 > VREF, the H1 pin will go high impedance, otherwise
the pin will be grounded. The maximum voltage permitted
on this pin is 7V. This pin provides support for setting up
hysterisis to an external resistor network.
E1 (Pin 2): LTC4416 Comparator Enable Input. A high
signal greater than VREF will enable the V1 path. The ideal
diode action will then determine if the V1 path should turn
on by controlling any PFET(s) connected to the G1 pin.
If the E1 signal is driven low, the V1 path will perform a
“soft-off” provided the PFET(s) are properly configured
for blocking DC current. An internal current sink will pull
the E1 pin down when the E1 input exceeds 1.5V.
E1 (Pin 2): LTC4416-1 Comparator Enable Input. A high
signal greater than VREF will enable the V1 path. The ideal
diode action will then determine if the V1 path should turn
on by controlling any PFET(s) connected to the G1 pin.
If the E1 signal is driven low, the V1 path will be quickly
disabled by enabling the “fast-off” feature, pulling the G1
gate high. An internal current sink will pull the E1 pin down
when the E1 input exceeds 1.5V.
GND (Pin 3): Ground. This pin provides a power return
path for all the internal circuits.
E2 (Pin 4): LTC4416 Comparator Enable Input. A low
signal less than VREF will enable the V2 path. The ideal
diode action will then determine if the V2 path should turn
on by controlling any PFET(s) connected to the G2 pin.
If the E2 signal is driven high, the V2 path will perform a
“soft-off” provided the PFET(s) are properly configured
for blocking DC current. An internal current sink will pull
the E2 pin down when the E2 input exceeds 1.5V.
E2 (Pin 4): LTC4416-1 Comparator Enable Input. A low
signal less than VREF will enable the V2 path. The ideal
diode action will then determine if the V2 path should turn
on by controlling any PFET(s) connected to the G2 pin.
If the E2 signal is driven high, the V2 path will be quickly
disabled by enabling the “fast-off” feature, pulling the G2
gate high. An internal current sink will pull the E2 pin down
when the E2 input exceeds 1.5V.
H2 (Pin 5): Open-Drain Comparator Output of the E2 Pin.
If E2 > VREF, the H2 pin will go high impedance, otherwise
the pin will be grounded. The maximum voltage permitted
on this pin is 7V. This pin provides support for setting up
hysterisis to an external resistor network.
G2 (Pin 6): Second P-Channel MOSFET Power Switch
Gate Drive Pin. This pin is directed by the second power
controller to maintain a forward regulation voltage (VFR)
of 25mV between the V2 and VS pins when V2 is greater
than VS. When V2 is less than VS, the G2 pin will pull up
to the VS pin voltage, turning off the second P-channel
power switch.
V2 (Pin 7): Second Input Supply Voltage. Supplies power
to the second power controller and the band-gap reference. V2 is one of the two voltage sense inputs to the
second internal power controller (the other input to the
second internal power controller is the VS pin). This input
is usually supplied power from the second, or backup,
power source. This pin can be bypassed to ground with
a capacitor in the range of 0.1µF to 10µF if needed to
suppress load transients.
VS (Pin 8): Power Sense Input Pin. Supplies power to
the internal circuitry of both the first and second power
controller and the band-gap reference. This pin is also a
voltage sense input to both internal analog controllers
(the other input to the first controller is the V1 pin and
the other input to the second controller is the V2 pin.)
This input may also be supplied power from an auxiliary
source which also supplies current to the load.
V1 (Pin 9): First Input Supply Voltage. Supplies power to
the first power controller and the band-gap reference. V1
is one of the two voltage sense inputs to the first internal
power controller (the other input to the first internal power
controller is the VS pin). This input is usually supplied
power from the first, or primary, power source. This pin
can be bypassed to ground with a capacitor in the range
of 0.1µF to 10µF if needed to suppress load transients.
G1 (Pin 10): First P-Channel MOSFET Power Switch Gate
Drive Pin. This pin is directed by the first power controller
to maintain a forward regulation voltage (VFR) of 25mV
between the V1 and VS pins when V1 is greater than VS.
When V1 is less than VS, the G1 pin will pull up to the VS pin
voltage, turning off the first P-channel power switch.
4416fa
LTC4416/LTC4416-1
BLOCK DIAGRA
W
RAIL1
9
8
V1
VS
IG(SRC)
FIRST
ANALOG
CONTROLLER
A1
IG(OFF)
8.5V
G1
EN2
IG(SNK)
IGFON(SNK)
10
IG1
EN1
2
E1
H1
+
C1
VREF
EN1
1
–
3 GND
RAILBG
BAND-GAP
REFERENCE
VREF
RAIL2
7
V2
SECOND
ANALOG
CONTROLLER
A2
EN2
4
E2
EN1
EN2
IG(SRC)
IG(OFF)
8.5V
G2
IG(SNK)
IGFON(SNK)
H2
+
6
IG2
5
C2
VREF
–
4416 BD
U
OPERATIO
Operation can best be understood by referring to the
Block Diagram which illustrates the internal circuit blocks.
The LTC4416/LTC4416-1 are divided into three sections,
namely:
1. The channel 1 controller consisting of A1, C1, the “first
analog contoller,” the G1 drivers and the H1 output
driver.
2. The band-gap reference
3. The channel 2 controller consisting of A2, C2, the
“second analog controller,” the G2 drivers and the H2
output driver.
Each of the three sections has its own derived internal
power supply referred to as a rail. RAIL1 provides power
to the channel 1 controller. RAIL2 provides power to the
channel 2 controller. The internal RAILBG provides power
to the band-gap reference. The internal rail1 derives its
power from the higher voltage of V1 and VS. The internal
rail2 derives its power from the higher voltage of V2 and
VS. RAILBG derives its power from the highest voltage of
V1, V2, and VS. All three sections share a common ground
connected to the GND pin.
4416fa
LTC4416/LTC4416-1
U
OPERATIO
The band-gap reference provides internal bias currents
used by the channel 1 and channel 2 controllers. It also
provides a precision voltage reference, VREF, used by comparators C1 and C2. The band-gap reference is powered
as long as a minimum operational voltage is present on
either V1, V2, or VS.
approaches the forward regulation voltage, VFR, the IG(SNK)
current will be proportional to VV1 – VVS. When VV1 – VVS
> VFON, the A1 activates the fast-on condition, tG(ON), and
the IG1 current is set to IGFON(SNK).
The C1 and C2 comparators provide a fixed comparison
between the E1 and E2 inputs, respectively, and the internal VREF signal. The comparator outputs are directly
represented by the H1 and H2 open-drain outputs. The
output states of H1 and H2 are not dependent upon
the relative voltage difference between VV1 – VVS and
VV2 – VVS, respectively. If VE1 is less than VREF, the H1
open-drain output will be low impedance to GND. If VE2
is less than VREF, the H2 open-drain output will be low
impedance to GND.
The interaction of the LTC4416 analog controllers distinguish the operation of the LTC4416 from a simple circuit
using two PowerPath controllers. Table 1 explains the
different operation modes of the analog controllers.
The A1 and A2 circuits act both as a high side
transconductance amplifiers and as comparators. Both
A1 and A2 act identically when the analog controllers
are fully enabled. The relationship of the G1 current is
represented by Figure 1.
When VV1 – VVS < VRTO, the A1 activates the reverse turnoff condition and the IG1 current is IG(OFF). When VRTO <
VV1 – VVS < VFR, the A1 acts as a class A output and the
IG1 current is fixed at IG(SRC). As the VV1 – VVS voltage
IGFON(SNK)
VRTO
IG(OFF)
E1
E2
Operation Mode
IG(OFF)1
IG(OFF)2
1
0
Load Sharing
Enabled
Enabled
1
Sense V1 is Less Than V2
Sense
0
V1 is Greater Than V2
0
X
Channel 1 Disabled.
Do Not Use
X
1
Channel 2 Disabled.
Do Not Use
0
1
Both Channels Disabled
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
The LTC4416 has six modes of operation. Each mode of
operation is dependent upon the configuration of the E1
and E2 input pins.
Load Sharing Operation
V1 is Less Than V2 Operation
IG(SNK)
VFR
Table 1. LTC4416 Operational Modes
The load sharing mode configures the LTC4416 into two
independent PowerPath controllers. This is accomplished
by fully enabling both the first analog controller and the
second analog controller. Both channels will implement
the gate drive outlined in Figure 1.
IG1
IG(SRC)
LTC4416 Operation
VFON
NOT DRAWN TO SCALE
Figure 1. IG1 vs VV1 – VVS
VV1 – VVS
Channel 1 is fully enabled. If VV1 – VVS < VRTO, channel 1
will implement all of the IG1 currents listed in Figure 1.
When VE2 is above the VREF threshold, channel 2 is in a
“soft-off mode”. This means that G2 will only provide an
IG(SRC) current instead of either an IG(SRC) or an IG(OFF)
current.
4416 F01
When VE2 is below the VREF threshold, channel 2 is fully
enabled, and G2 will become active implementing the IG
output current listed in Figure 1.
4416fa
LTC4416/LTC4416-1
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OPERATIO
V1 is Greater Than V2 Operation
Both Channels Disabled
When VE1 is below the VREF threshold, channel 1 is in
a “soft-off mode”. This means that G1 will only provide
an IG(SRC) current instead of an IG(SNK) or an IGFON(SNK)
current.
When both channels of the LTC4416 are disabled, both
G1 and G2 currents are set to IG(SRC).
When VE1 is above the VREF threshold, channel 1 is immediately fully enabled, and G1 will become active implementing the output current listed in Figure 1.
Channel 2 is fully enabled. If VV1 – VVS < VRTO, channel 2
will implement all of the IG2 currents listed in Figure 1.
Channel 1 is Disabled
The LTC4416 is not designed to have channel 1 disabled
by grounding E1 and leaving E2 in an indeterminate state.
If this happens, the channel 2 PowerPath controller will
not have reverse turn-off capability. No electrical harm to
the LTC4416 will occur.
Channel 2 is Disabled
The LTC4416 is not designed to have channel 2 disabled
by connecting E2 high and leaving E1 in an indeterminate
state. If this happens, the channel 1 PowerPath controller
will not have reverse turn-off capability. No electrical harm
to the LTC4416 will occur.
LTC4416-1 Operation
The LTC4416-1 is designed for overvoltage/undervoltage
protection or when either voltage path must be turned off
rapidly, regardless of the status of the other voltage input.
The LTC4416-1 does not implement the soft-off feature
implemented in the LTC4416. The E1 and E2 inactive will
force the IG current of their respective channel to IG(OFF).
Table 2 explains the operation of the E1 and E2 inputs.
The term “active” implies that IG(OFF) current is forced on
the Gn pins regardless of the VVn – VVS value. The term
“enabled” implies that IG(OFF) current is provide on the Gn
pins if and only if VVn – VVS < VRTO.
Table.2 LTC4416-1 Operational Modes
E1
E2
Operation Mode
IG(OFF)1
Active
0
X
Undervoltage Protection
X
1
Overvoltage Protection
1
X
Channel 1 PowerPath
X
0
Channel 2 PowerPath
IG(OFF)2
Active
Enabled
Enabled
APPLICATIO S I FOR ATIO
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LTC4416
The LTC4416 is designed to support three major applications. The first two applications assume that V1 is
the primary power source and V2 is the backup power
source. The first application is where the V1 power supply
is normally less than V2. The second application is where
the V1 power supply is normally greater than V2. The third
application addresses the load sharing case where both
V1 and V2 are relatively equal in value.
V1 is Less Than V2
Figure 2 illustrates the external resistor configuration for
this case.
V1
V1 = 9V (FAIL)
V1 = 10.8V (RESTORE)
PRIMARY SUPPLY
Q1
SUP75P03_07
R2A
158k
LTC4416
R2E
105k
GND
R2C
24.9k
E1
V1
H1
G1
GND
VS
E2
G2
H2
V2
V2
VS
4416 F02
V2 = 14.4V
BACKUP SUPPLY
Q2
Q3
SUP75P03_07
Figure 2
4416fa
LTC4416/LTC4416-1
APPLICATIO S I FOR ATIO
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This configuration would be used where V1 is a 12V power
supply and the V2 power supply is a 4-cell Li-Ion battery
pack. When V1 is 12V, E2 disables the V2 source from
being connected to VS through Q2A and Q2B by forcing
G2 to V2, H2 is open circuit. E1 is connected to a voltage
greater than the VREF to keep the V1 to VS path active. The
VS output can be shut completely off by grounding the E1
input. The LTC4416 takes its power from the higher of V1,
V2 and VS. This configuration will provide power from V1
to VS until the V1 supply drops below 9V.
When V1 drops below 9V, the H2 pin closes to GND, G2
drops to a VCLAMP below V2 and G1 rises to the VS voltage level. V2 will supply current to VS until V1 rises above
10.8V. The H1 output will be open until the E1 input drops
below the VREF voltage level.
The V1 VFAIL is determined by:
VFAIL = VETH •
R2A + R2c
R2c
= 1.222V •
(R2A + (R2c R2E))
•
= 1.222V •
24.9k 105k
R1D
187k
LTC4416
R1C
24.9k
GND
E1
V1
GND
G1
E2
VS
H2
G2
H1
V2
VS
V2
4416 F03
V2 = 10.8V
BACKUP SUPPLY
Q3
SUP75P03_07
Figure 3
When V1 drops below 12V, the H1 pin closes to GND,
G2 drops to a VCLAMP below V2 and G1 rises to the V1
voltage level. V2 will supply current to VS until V1 rises
above 13.5V. The H2 output will be shorted to GND until
the E2 input goes above the VREF voltage level.
R1A + R1c
R1c
= 1.222V •
R2c R2E
(
R1A
221k
VFAIL = VETH •
The V1 VRESTORE is determined by:
1558k + 24.9k 105k
SUP75P03_07
Q1
Q2
PRIMARY SUPPLY
The V1 VFAIL is determined by:
158k + 24.9k
= 8.98 V
24.9kk
VRESTORE = VETH
V1
V1 = 12V (FAIL)
V1 = 13.5V (RESTORE)
) = 10.81V
V1 is Greater Than V2
Figure 3 illustrates the external resistor configuration for
this case.
This configuration would be used where V1 is a 12V power
supply and the V2 power supply is a 3-cell Li-Ion battery
pack. When V1 is 16V, E1 enables the V1 source as being the
primary supply, thus disabling the V2 supply since V1 > V2.
When E1 > VREF, the H1 output is open. The VS output can be
shut completely off by grounding the H1 input and forcing
E2 > VREF. The LTC4416 takes its power from the higher of
V1, V2 and VS. This configuration will provide power from
V1 to VS until the V1 supply drops below 12V.
221k + 24.9k
= 12.07 V
24.9kk
The V1 VRESTORE is determined by:
VRESTORE = VETH •
(R1A + (R1c R1D))
= 1.222V •
R1c R1D
(
2221k + 24.9k 187k
24.9k 187k
) = 13.51V
Load Sharing
Figure 4 illustrates the configuration for this case.
This configuration would be used where V1 and V2 are
relatively the same voltage. In this case the LTC4416 acts
as two interconnected ideal diode controllers. VS will be
supplied by the higher of the two supplies, V1 and V2. If
V1 and V2 are exactly the same, then 50% of the current
for VS will be supplied by each supply. As the two supplies
4416fa
LTC4416/LTC4416-1
APPLICATIO S I FOR ATIO
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differ by more than 100mV, 100% of the load will come
from the higher of V1 or V2.
The user has the option of using E1 and E2 to disable
one of the two supplies by connecting them to a digital
controller. If E1 is brought low, V1 will no longer supply
current to VS. If E2 is brought high, V2 will no longer supply current to VS. If E1 is brought low and E2 is brought
high, VS will be disabled.
Figure 5 shows the same application without the shutdown option. It has one-half the losses of Figure 4 and is
configured for 5V rails.
V1
Si7483ADP
Q1
Q2
V1 = 12V
LTC4416
E1
TO HOST
CONTROLLER
GND
E2
E1
V1
H1
G1
GND
VS
E2
G2
H2
V2
V2
VS
4416 F04
Q3
Q4
Si7483ADP
V2 = 12V
Figure 4
Q1
Si7495DP
SUPPLY 1
V1
5V
disabled. This rapid turn-off feature is desirable when the
supply cannot tolerate certain voltage excursions under
load, or when the load is being protected from a rapidly
changing input supply.
Under and Overvoltage Shutdown
Refer to Figure 6 for an application circuit which disables
the power to the load when the input voltage gets too low
or too high. When VIN starts from zero volts, the load to
the output is disabled until VIN reaches 5.5V. The V1 path is
enabled and the load remains on the input until the supply
exceeds 13.5V. At that voltage, the V2 path is disabled. As
the input falls, the voltage source will be reconnected to
the load when the input drops to 12V and the V2 path is
enabled. Finally, the load will be removed from the input
supply when the voltage drops below 5V.
VIN
R1A
75k
R2A
221k
VTH2 WITH
HYSTERESIS
R2C
24.9k
GND
VTH1 WITH
HYSTERESIS
R1D
182k
R2E R1C
187k 24.3k
V2
5V
V1
E1
G1
GND
VS
E2
G2
H2
V2
V1
GND
VS
E2
V2
H2
G2
VOUT
TO
LOAD
4416 F06
Figure 6
VS
5V
Undervoltage
VFAIL = VETH •
4416 F05
SUPPLY 2
E1
UV ENABLED AT 5V, VIN RESTORED TO LOAD WHEN VIN RISES TO 5.5V
OV ENABLED AT 13.5V, VIN RESTORED TO LOAD WHEN VIN FALLS TO 12V
LTC4416
H1
LTC4416-1
H1
G1
Q2
Si7495DP
Figure 5. Dual PowerPath for Current Sharing
LTC4416-1
The LTC4416-1 will support all three of the LTC4416
applications without the “soft-off” feature. The only difference in the two designs is the LTC4416-1 will rapidly
switch off the load from a supply whenever a channel is
R1A + R1c
R1c
= 1.222V •
75k + 24.3k
= 4.99 V
24.3k
VRESTORE = VETH •
(R1A + (R1c R1D))
= 1.222V •
R1c R1D
(
755k + 24.3k 182k
24.3k 182k
) = 5.497V
4416fa
10
LTC4416/LTC4416-1
APPLICATIO S I FOR ATIO
U
Figure 9 contains a rapidly changing input voltage on a
much smaller time scale in comparison to Figure 8. The
LTC4416 will require the tE(OFF) time prior to the rapid pullup current being applied. The gate voltage will be pulled
high with IG(OFF) which has a minimum current of 500µA.
The discharge time of the gate will be dependent on the
capacitance of the external FET and the initial gate-source
voltage of the circuit. The total time delay will equal:
U
VFAIL = VETH •
R2A + R2c|| R2E
R2c|| R2E
= 1.222V •
221k + 24.9k || 187k
= 13.51V
24.9k || 187k
VRESTORE = VETH •
R2A + R2c
R2c
221k + 24.9k
= 1.222V •
= 12.07 V
244.9k
The over and undervoltage lockout circuits are shown here
working in tandem. It is possible to configure the circuit
for either over or undervoltage lockout by using only one
of the voltage paths and eliminating the components from
the other. Refer to Figure 7 for an LTC4416-1 configured
for overvotlage protection. If the input does not go below
ground, transistor Q1 can be eliminated.
The LTC4416-1 should be used in this configuration rather
than the LTC4416 because the LTC4416-1 will turn-off
rapidly if an over or undervoltage condition is detected.
Refer to Figure 8 for a comparison of the transient response
of the two ICs using the circuit configuration of Figure 6.
The LTC4416 will not turn-off quickly in an overvoltage
or undervoltage condition because the “fast-off” feature
is not enabled. This will cause the output to travel beyond
the desired range.
VTH2 WITH
HYSTERESIS
R2C
24.9k
GND
Q1
R2A
221k
cGS • ∆V
IG(OFF)
20
VOUT
LTC4416
15
VOUT
LTC4416-1
10
5
VIN
VOUT
LTC4416
0
20
40
TIME (ms)
V1
GND
VS
E2
V2
H2
G2
VOUT
TO
LOAD
4416 F07
Figure 7. LTC4416-1 Configured for Overvoltage Protection
80
4416 F08
VIN
LTC4416
13.55
E1
60
Figure 8. Transient Response of the LTC4416 vs the LTC4416-1
Light Load with a Large Capacitor on VOUT
13.60
R1A
100k
VOUT
LTC4416-1
0
Q2
LTC4416-1
H1
G1
R2E
187k
= tE(OFF ) +
VOLTAGE (V)
VIN
tDELAY = tE(OFF ) + tDIScHARGE
VOLTAGE (V)
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Overvoltage
LTC4416-1
GATE DISCHARGE TIME
∆V
=C I
G(OFF)
13.50
13.45
tE(OFF)
13.40
0
0
5
10
15 20 25
TIME (µs)
30
35
40
4416 F09
Figure 9. Close Up of the Transient Response of the LTC4416-1
to a Rapidly Rising Input
4416fa
Information furnished by Linear Technology corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
11
LTC4416/LTC4416-1
PACKAGE DESCRIPTIO
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MS Package
10-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1661)
0.254
(.010)
0.889 ± 0.127
(.035 ± .005)
DETAIL “A”
0° – 6° TYP
GAUGE PLANE
5.23
(.206)
MIN
0.53 ± 0.152
(.021 ± .006)
3.20 – 3.45
(.126 – .136)
DETAIL “A”
0.50
0.305 ± 0.038
(.0197)
(.0120 ± .0015)
BSc
TYP
REcOMMENDED SOLDER PAD LAYOUT
0.18
(.007)
SEATING
PLANE
NOTE:
1. DIMENSIONS IN MILLIMETER/(INcH)
2. DRAWING NOT TO ScALE
3. DIMENSION DOES NOT INcLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXcEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INcLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXcEED 0.152mm (.006") PER SIDE
5. LEAD cOPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.17 – 0.27
(.007 – .011)
TYP
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.86
(.034)
REF
1.10
(.043)
MAX
0.50
(.0197)
BSc
0.127 ± 0.076
(.005 ± .003)
10 9 8 7 6
0.497 ± 0.076
(.0196 ± .003)
REF
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
MSOP (MS) 0603
1 2 3 4 5
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ThinSOT is a trademark of Linear Technology Corporation.
4416fa
12 Linear Technology Corporation
LT 0507 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
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