ATMEL AT49BV6416C-70CI 64-megabit (4m x 16) page mode 2.7-volt flash memory Datasheet

Features
• 64-megabit (4M x 16) Flash Memory
• 2.7V - 3.6V Read/Write
• High Performance
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– Asynchronous Access Time – 70 ns
– Page Mode Read Time – 20 ns
Sector Erase Architecture
– Eight 4K Word Sectors with Individual Write Lockout
– One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
Typical Sector Erase Time: 32K Word Sectors – 700 ms; 4K Word Sectors – 200 ms
Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not
Being Programmed/Erased
– Memory Plane A: 16M Memory Including Eight 4K Word Sectors
– Memory Plane B: 16M Memory Consisting of 32K Word Sectors
– Memory Plane C: 16M Memory Consisting of 32K Word Sectors
– Memory Plane D: 16M Memory Consisting of 32K Word Sectors
Suspend/Resume Feature for Erase and Program
– Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector
– Supports Reading Any Word by Suspending Programming of Any Other Word
Low-power Operation
– 30 mA Active
– 35 µA Standby
2.2V I/O Option Reduces Overall System Power
VPP Pin for Write Protection and Accelerated Program/Erase Operations
Reset Input for Device Initialization
CBGA Package
Top or Bottom Boot Block Configuration Available
128-bit Protection Register
Common Flash Interface (CFI)
64-megabit
(4M x 16)
Page Mode
2.7-volt Flash
Memory
AT49BV6416C
AT49BV6416CT
1. Description
The AT49BV6416C(T) is a 2.7-volt 64-megabit Flash memory. The memory is divided
into multiple sectors and planes for erase operations. The device can be read or
reprogrammed off a single 2.7V power supply, making it ideally suited for In-System
programming. The device can operate in the asynchronous or page read mode.
The AT49BV6416C(T) is divided into four memory planes. A read operation can occur
in any of the three planes which is not being programmed or erased. This concurrent
operation allows improved system performance by not requiring the system to wait for
a program or erase operation to complete before a read is performed. To further
increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time
and let the user read data from or program data to any of the remaining sectors. There
is no reason to suspend the erase or program operation if the data to be read is in
another memory plane.
The VPP pin provides data protection and faster programming times. When the VPP
input is below 0.7V, the program and erase functions are inhibited. When VPP is at
1.65V or above, normal program and erase operations can be performed. With VPP at
10.0V, the program (Dual-word Program command) operation is accelerated.
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2. Pin Configurations
2.1
Pin Name
Pin Function
I/O0 - I/O15
Data Inputs/Outputs
A0 - A21
Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
Reset
Reset
WP
Write Protect
VPP
Write Protection and Power Supply for Accelerated Program/Erase Operations
VCCQ
Output Power Supply
48-ball CBGA – Top View
1
2
3
4
5
6
7
8
A13
A11
A8
VPP
WP
A19
A7
A4
A14
A10
WE
RST
A18
A17
A5
A2
A15
A12
A9
A21
A20
A6
A3
A1
A16 I/O14 I/O5 I/O11 I/O2
I/O8
CE
A0
VCCQ I/O15 I/O6 I/O12 I/O3
I/O9
I/O0
GND
A
B
C
D
E
F
GND
2
I/O7 I/O13 I/O4
VCC I/O10 I/O1
OE
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AT49BV6416C(T)
3. Device Operation
3.1
Command Sequences
When the device is first powered on, it will be in the read mode. Command sequences are used
to place the device in other operating modes such as program and erase. The command
sequences are written by applying a low pulse on the WE input with CE low and OE high or by
applying a low-going pulse on the CE input with WE low and OE high. The address is latched on
the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE
pulse, whichever occurs first. The addresses used in the command sequences are not affected
by entering the command sequences.
3.2
Asynchronous Read
The AT49BV6416C(T) is accessed like an EPROM. When CE and OE are low and WE is high,
the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention.
3.3
Page Read
The page read operation of the device is controlled by CE and OE inputs. The page size is four
words. The first word access of the page read is the same as the asynchronous read. The first
word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1
will result in subsequent reads within the page being output at a speed of 20 ns. See the “Page
Read Cycle Waveform” on page 24.
3.4
Reset
A Reset input pin is provided to ease some system applications. When Reset is at a logic high
level, the device is in its standard operating mode. A low level on the Reset pin halts the present
device operation and puts the outputs of the device in a high-impedance state. When a high
level is reasserted on the Reset pin, the device returns to read mode.
3.5
Erase
Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a
logical “1”. The entire memory can be erased by using the Chip Erase command or individual
planes can be erased by using the Plane Erase command or individual sectors can be erased by
using the Sector Erase command.
3.5.1
Chip Erase
Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the
last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset
during chip erase will stop the erase, but the data will be of an unknown state.
3.5.2
Plane Erase
As an alternative to a full Chip Erase, the device is organized into four planes that can be individually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address
is valid at the second rising edge of WE will be erased. The Plane Erase command does not
alter the data in the protected sectors.
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3.5.3
Sector Erase
The device is organized into multiple sectors that can be individually erased. The Sector Erase
command is a two-bus cycle operation. The sector whose address is valid at the second rising
edge of WE will be erased provided the given sector has not been protected.
3.6
Word Programming
The device is programmed on a word-by-word basis. Programming is accomplished via the
internal device command register and is a two-bus cycle operation. The programming address
and data are latched in the second cycle. The device will automatically generate the required
internal programming pulses. Please note that a “0” cannot be programmed back to a “1”; only
erase operations can convert “0”s to “1”s.
3.7
Flexible Sector Protection
The AT49BV6416C(T) offers two sector protection modes, the Softlock and the Hardlock. The
Softlock mode is optimized as sector protection for sectors whose content changes frequently.
The Hardlock protection mode is recommended for sectors whose content changes infrequently.
Once either of these two modes is enabled, the contents of the selected sector is read-only and
cannot be erased or programmed. Each sector can be independently programmed for either the
Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled.
3.7.1
Softlock And Unlock
The Softlock protection mode can be disabled by issuing a two-bus cycle Unlock command to
the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To
enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the
selected sector.
3.7.2
Hardlock And Write Protect (WP)
The Hardlock sector protection mode operates in conjunction with the Write Protection (WP) pin.
The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the
Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be
unlocked via the Unlock command.
To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.
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Table 3-1.
Hardlock and Softlock Protection Configurations in Conjunction with WP
Softlock
Erase/
Prog
Allowed?
VPP
WP
Hardlock
VCC
0
0
0
Yes
No sector is locked
VCC
0
0
1
No
Sector is Softlocked. The
Unlock command can unlock
the sector.
VCC
0
1
1
No
Hardlock protection mode is
enabled. The sector cannot be
unlocked.
VCC
1
0
0
Yes
No sector is locked.
VCC
1
0
1
No
Sector is Softlocked. The
Unlock command can unlock
the sector.
VCC
1
1
0
Yes
Hardlock protection mode is
overridden and the sector is
not locked.
Comments
VCC
1
1
1
No
Hardlock protection mode is
overridden and the sector can
be unlocked via the Unlock
command.
VIL
x
x
x
No
Erase and Program Operations
cannot be performed.
Figure 3-1.
Sector Locking State Diagram
UNLOCKED
[000]
LOCKED
A
B
[001]
C
Power-Up/Reset
Default
C
WP = VIL = 0
Hardlocked
[011]
A
[110]
B
C
WP = VIH = 1
A
[100]
Hardlocked is disabled by
WP = VIH
[111]
C
Power-Up/Reset
Default
B
[101]
A = Unlock Command
B = Softlock Command
C = Hardlock Command
Note:
1. The notation [X, Y, Z] denotes the locking state of a sector. The current locking state of a sector
is defined by the state of WP and the two bits of the sector-lock status D[1:0].
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3.7.3
Sector Protection Detection
A software method is available to determine if the sector protection Softlock or Hardlock features
are enabled. When the device is in the software product identification mode a read from the I/O0
and I/O1 at address location 00002H within a sector will show if the sector is unlocked, softlocked, or hardlocked.
Table 3-2.
3.8
Sector Protection Status
I/O1
I/O0
Sector Protection Status
0
0
Sector Not Locked
0
1
Softlock Enabled
1
0
Hardlock Enabled
1
1
Both Hardlock and Softlock Enabled
Read Status Register
The status register indicates the status of device operations and the success/failure of that operation. The Read Status Register command causes subsequent reads to output data from the
status register until another command is issued. To return to reading from the memory, issue a
Read command.
The status register bits are output on I/O7 - I/O0. The upper byte, I/O15 - I/O8, outputs 00H
when a Read Status Register command is issued.
The contents of the status register [SR7:SR0] are latched on the falling edge of OE or CE
(whichever occurs last), which prevents possible bus errors that might occur if status register
contents change while being read. CE or OE must be toggled with each subsequent status read,
or the status register will not indicate completion of a Program or Erase operation.
When the Write State Machine (WSM) is active, SR7 will indicate the status of the WSM; the
remaining bits in the status register indicate whether the WSM was successful in performing the
preferred operation (see Table 3-3 on page 7).
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Table 3-3.
Status Register Bit Definition
WSMS
ESS
ES
PRS
VPPS
PSS
SLS
PLS
7
6
5
4
3
2
1
0
Notes
SR7 WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine Word Program
or Sector Erase completion, before checking program or erase
status bits.
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1” – ESS bit remains set to “1” until
an Erase Resume command is issued.
SR5 = ERASE STATUS (ES)
1 = Error in Sector Erase
0 = Successful Sector Erase
When this bit is set to “1”, WSM has applied the max number of
erase pulses to the sector and is still unable to verify successful
sector erasure.
SR4 = PROGRAM STATUS (PRS)
1 = Error in Programming
0 = Successful Programming
When this bit is set to “1”, WSM has attempted but failed to
program a word
SR3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of VPP
level. The WSM interrogates VPP level only after the Program or
Erase command sequences have been entered and informs the
system if VPP has not been switched on. The VPP is also checked
before the operation is verified by the WSM.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1”. PSS bit remains set to “1”
until a Program Resume command is issued.
SR1 = SECTOR LOCK STATUS
1 = Prog/Erase attempted on a locked sector; Operation aborted.
0 = No operation to locked sectors
If a Program or Erase operation is attempted to one of the locked
sectors, this bit is set by the WSM. The operation specified is
aborted and the device is returned to read status mode.
SR0 = Plane Status (PLS)
Indicates program or erase status of the addressed plane.
Note:
1. A Command Sequence Error is indicated when SR1, SR3, SR4 and SR5 are set.
Table 3-4.
Status Register Device WSMS and Write Status Definition
WSMS
(SR7)
PLS
(SR0)
0
0
The addressed plane is performing a program/erase operation.
0
1
A plane other than the one currently addressed is performing a program/erase operation.
1
x
No program/erase operation is in progress in any plane. Erase and Program suspend bits (SR6, SR2)
indicate whether other planes are suspended.
Description
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3.9
Erase Suspend/Erase Resume
The Erase Suspend command allows the system to interrupt a sector erase or plane erase operation. The erase suspend command does not work with the Chip Erase feature. Using the erase
suspend command to suspend a sector erase operation, the system can program or read data
from a different sector within the same plane. Since this device is organized into four planes,
there is no need to use the erase suspend feature while erasing a sector when you want to read
data from a sector in another plane. After the Erase Suspend command is given, the device
requires a maximum time of 15 µs to suspend the erase operation. After the erase operation has
been suspended, the plane that contains the suspended sector enters the erase-suspend-read
mode. The system can then read data or program data to any other sector within the device. An
address is not required during the Erase Suspend command. During a sector erase suspend,
another sector cannot be erased. To resume the sector erase operation, the system must write
the Erase Resume command. The Erase Resume command is a one-bus cycle command,
which does require the plane address. Read, Read Status Register, Product ID Entry, Clear Status Register, Program, Program Suspend, Erase Resume, Sector Softlock/Hardlock, Sector
Unlock are valid commands during an erase suspend.
3.10
Program Suspend/Program Resume
The Program Suspend command allows the system to interrupt a programming operation and
then read data from a different word within the memory. After the Program Suspend command is
given, the device requires a maximum of 10 µs to suspend the programming operation. After the
programming operation has been suspended, the system can then read from any other word
within the device. An address is not required during the program suspend operation. To resume
the programming operation, the system must write the Program Resume command. The program suspend and resume are one-bus cycle commands. The command sequence for the
erase suspend and program suspend are the same, and the command sequence for the erase
resume and program resume are the same. Read, Read Status Register, Product ID Entry, Program Resume are valid commands during a Program Suspend.
3.11
128-bit Protection Register
The AT49BV6416C(T) contains a 128-bit register that can be used for security purposes in system design. The protection register is divided into two 64-bit blocks. The two blocks are
designated as block A and block B. The data in block A is non-changeable and is programmed
at the factory with a unique number. The data in block B is programmed by the user and can be
locked out such that data in the block cannot be reprogrammed. To program block B in the protection register, the two-bus cycle Program Protection Register command must be used as
shown in the “Command Definition Table” on page 15. To lock out block B, the two-bus cycle
lock protection register command must be used as shown in the Command Definition table. Data
bit D1 must be zero during the second bus cycle. All other data bits during the second bus cycle
are don’t cares. To determine whether block B is locked out, the Status of Sector B Protection
command is given. If data bit D1 is zero, block B is locked. If data bit D1 is one, block B can be
reprogrammed. Please see the “Protection Register Addressing Table” on page 16 for the
address locations in the protection register. To read the protection register, the Product ID Entry
command is given followed by a normal read operation from an address within the protection
register. After determining whether block B is protected or not or reading the protection register,
the Read command must be given to return to the read mode.
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3.12
Common Flash Interface (CFI)
CFI is a published, standardized data structure that may be read from a flash device. CFI allows
system software to query the installed device to determine the configurations, various electrical
and timing parameters, and functions supported by the device. CFI is used to allow the system
to learn how to interface to the flash device most optimally. The two primary benefits of using
CFI are ease of upgrading and second source availability. The command to enter the CFI Query
mode is a one-bus cycle command which requires writing data 98h to any address. The CFI
Query command can be written when the device is ready to read data or can also be written
when the part is in the product ID mode. Once in the CFI Query mode, the system can read CFI
data at the addresses given in the “Common Flash Interface Definition Table” on page 27. To
return to the read mode, the read command should be issued.
3.13
Hardware Data Protection
Hardware features protect against inadvertent programs to the AT49BV6416C(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the device is reset and the program and
erase functions are inhibited. (b) VCC power-on delay: once VCC has reached the VCC sense
level, the device will automatically time-out 10 ms (typical) before programming. (c) Program
inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. (e)
VPP is less than VILPP.
3.14
Input Levels
While operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE
and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device.
The I/O lines can be driven from 0 to VCCQ + 0.6V.
3.15
Output Levels
For the AT49BV6416C(T), output high levels are equal to VCCQ - 0.1V (not VCC). For 2.7V to
3.6V output levels, VCCQ must be tied to VCC.
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3.16
Word Program Flowchart
3.17
Word Program Procedure
Bus
Operation
Start
Write 40,
Word Address
Write Data,
Word Address
Command
Write
Program
Setup
Data = 40
Addr = Location to program
Write
Data
Data = Data to program
Addr = Location to program
Read
None
Status register data: Toggle CE
or
OE to update status register
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
(Setup)
(Confirm)
Program
Suspend
Loop
Read Status
Register
No
0
SR7 =
Suspend?
Yes
1
Full Status
Check
(If Desired)
Comments
Repeat for subsequent Word Program operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to set to the Read state.
Program
Complete
3.18
Full Status Check Flowchart
Read Status
Register
SR3 =
1
VP P Range
Error
3.19
Full Status Check Procedure
Bus
Operation
Command
Idle
None
Check SR3:
1 = VPP Error
Idle
None
Check SR4:
1 = Data Program Error
Idle
None
Check SR1:
1 = Sector locked; operation
aborted
0
SR4 =
1
Program
Error
0
SR1 =
1
Device
Protect Error
0
Comments
SR3 MUST be cleared before the Write State Machine allows
further program attempts.
If an error is detected, clear the status register before
continuing operations – only the Clear Status Register
command clears the status register error bits.
Program
Successful
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3.20
Program Suspend/Resume Flowchart
Program Suspend/Resume Procedure
Bus
Operation
Start
Write B0
Any Address
3.21
(Program Suspend)
Write 70
Any Address
(Read Status)
within
the Same Plane
Command
Program
Suspend
Write
Read
Status
Data = 70
Addr = Any address within the
Same Plane
Read
None
Status register data: Toggle CE
or
OE to update status register
Addr = Any address
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
Idle
None
Check SR2
1 = Program suspended
0 = Program completed
Write
Read Array
Read
None
Write
Program
Resume
0
1
SR2 =
0
Program
Completed
1
Write FF
Suspend Plane
(Read Array)
Read
Data
Done
Reading
Write FF
No
Read
Data
Yes
Write D0
Any Address
(Program Resume)
Program
Resumed
Write 70H
Any Address
within
the Same Plane
(Read
Array)
Data = B0
Addr = Sector address to
Suspend (SA)
Write
Read Status
Register
SR7 =
Comments
Data = FF
Addr = Any address within the
Suspended Plane
Read data from any sector in the
memory other than the one being
programmed
Data = D0
Addr = Any address
If the Suspend Plane was placed in Read mode:
(Read Status)
Write
Read
Status
Return Plane to Status mode:
Data = 70
Addr = Any address within the
Same Plane
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3.22
Sector Erase Flowchart
3.23
Sector Erase Procedure
Bus
Operation
Start
Write 20,
Sector Address
(Sector Erase)
Write D0,
(Erase Confirm)
Sector Address
Suspend
Erase
Loop
Read Status
Register
Command
Write
Sector
Erase
Setup
Data = 20
Addr = Sector to be erased (SA)
Write
Erase
Confirm
Data = D0
Addr = Sector to be erased (SA)
Read
None
Status register data: Toggle CE
or
OE to update status register data
Idle
None
Check SR7
1 = WSMS Ready
0 = WSMS Busy
No
Suspend
Erase
0
SR7 =
Yes
1
Full Erase
Status Check
(If Desired)
Repeat for subsequent sector erasures.
Full status register check can be done after each sector erase,
or after a sequence of sector erasures.
Write FF after the last operation to enter read mode.
Sector Erase
Complete
3.24
Full Erase Status Check Flowchart
3.25
Full Erase Status Check Procedure
Bus
Operation
Command
VP P Range
Error
Idle
None
Check SR3:
1 = VPP Range Error
Command
Sequence Error
Idle
None
Check SR4, SR5:
Both 1 = Command Sequence
Error
1
Sector Erase
Error
Idle
None
Check SR5:
1 = Sector Erase Error
1
Sector Locked
Error
Idle
None
Check SR1:
1 = Attempted erase of locked
sector; erase aborted.
Read Status
Register
SR3 =
1
0
SR4, SR5 =
1,1
0
SR5 =
0
SR1 =
0
Sector Erase
Successful
12
Comments
Comments
SR1, SR3 must be cleared before the Write State Machine
allows further erase attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4, SR5.
If an error is detected, clear the status register before
attempting an erase retry or other error recovery.
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AT49BV6416C(T)
3.26
Erase Suspend/Resume Flowchart
3.27
Erase Suspend/Resume Procedure
Bus
Operation
Start
Write B0,
Any Address
(Erase Suspend)
Write 70,
Any Address
(Read Status)
Command
0
Erase
Suspend
Write
Read
Status
Data = 70
Addr = Any address
Read
None
Status register data: Toggle CE
or
OE to update status register
Addr = Any address within the
Same Plane
Idle
None
Check SR7
1 = WSM Ready
0 = WSM Busy
Idle
None
Check SR6
1 = Erase suspended
0 = Erase completed
Write
Read or
Program
Read or
Write
None
Write
Program
Resume
1
SR6 =
0
Erase
Completed
1
Read
or Program?
Read
No
Program
Loop
Done?
Yes
(Erase Resume)
Write D0,
Any Address
Write FF
Erase
Resumed
Read Array
Data
Write 70H
Any Address
within
the Same Plane
(Read Status)
(Read Array)
Data = B0
Addr = Any address within the
Same Plane
Write
Read Status
Register
SR7 =
Comments
Data = FF or 40
Addr = Any address
Read or program data from/to
sector other than the one being
erased
Data = D0
Addr = Any address
If the Suspended Plane was placed in Read mode or a
Program loop:
Write
Read
Status
Return Plane to Status mode:
Data = 70
Addr = Any address within the
Same Plane
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3.28
Protection Register Programming
Flowchart
Write C0,
PR Address
Write PR
Address & Data
SR7 =
Program
PR Setup
Data = C0
Addr = First Location to Program
(Confirm Data)
Write
Protection
Program
Data = Data to Program
Addr = Location to Program
Read
None
Status register data: Toggle CE
or
OE to update status register data
Idle
None
Check SR7
1 = WSMS Ready
0 = WSMS Busy
0
Full Status
Check
(If Desired)
Program Protection Register operation addresses must be
within the protection register address space. Addresses
outside this space will return an error.
Repeat for subsequent programming operations.
Full status register check can be done after each program, or
after a sequence of program operations.
Write FF after the last operation to return to the Read mode.
Program
Complete
Full Status Check Flowchart
Read Status
Register Data
0, 1
1, 1
Register Locked;
Program Aborted
0
Program
Successful
14
Full Status Check Procedure
Bus
Operation
Command
Idle
None
Check SR1, SR3, SR4:
0,1,1 = VPP Range Error
Idle
None
Check SR1, SR3, SR4:
0,0,1 = Programming Error
Idle
None
Check SR1, SR3, SR4:
1, 0,1 = Sector locked; operation
aborted
Program Error
0
SR1, SR4 =
3.31
VP P Range Error
0
SR1, SR4 =
Comments
Write
1
1, 1
Command
(Program Setup)
Read Status
Register
SR3, SR4 =
Protection Register Programming
Procedure
Bus
Operation
Start
3.30
3.29
Comments
SR3 must be cleared before the Write State Machine allows
further program attempts.
Only the Clear Status Register command clears SR1, SR3,
SR4.
If an error is detected, clear the status register before
attempting a program retry or other error recovery.
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
4. Command Definition Table
1st Bus
Cycle
2nd Bus
Cycle
Bus
Cycles
Addr
Data
Read
1
PA(2)
FF
Chip Erase
2
xx
Plane Erase
2
Sector Erase
2
Command Sequence
Word Program
3rd Bus
Cycle
Addr
Data
21
Addr
D0
xx
22
Addr
D0
SA(3)
20
SA(3)
D0
(4)
DIN
Addr0
DIN0
2
Addr
3
Addr0
E0
Erase/Program Suspend
1
xx
B0
Erase/Program Resume
1
PA(2)
D0
Product ID Entry(6)(7)
1
PA(2)
90
2
SA
(3)
60
SA(3)
01
(3)
60
(3)
SA
2F
60
SA(3)
D0
70
(7)
Dual Word Program
(5)
Sector Softlock
40/10
(4)
Sector Hardlock
2
SA
Sector Unlock
2
SA(3)
Read Status Register
2
(2)
Clear Status Register
1
xx
Program Protection Register– Block B
2
(10)
Lock Protection Register – Sector B
2
xxxx80(10)
Status of Sector B Protection
2
(10)
CFI Query
1
Notes:
PA
xxxx
PA
Data
Addr1
DIN1
DOUT(8)
50
(9)
8x
xxxx80
xx
Addr
Addr
C0
xxxx(10)8x(9)
DIN
C0
xxxx80(10)
FFFD
90
(10)
xxxx80
DOUT(11)
98
1. The DATA FORMAT shown for each bus cycle is as follows; I/O7 - I/O0 (Hex). I/O15 - I/O8 are don’t care. The ADDRESS
FORMAT shown for each bus cycle is as follows: A7 - A0 (Hex). Address A21 through A8 are don’t care.
2. PA is the plane address (A21 - A20). Any address within a plane can be used.
3. SA = sector address. Any word address within a sector can be used to designate the sector address (see pages 17 - 20 for
details).
4. The first bus cycle address should be the same as the word address to be programmed.
5. This fast programming option enables the user to program two words in parallel only when VPP = 10V. The addresses, Addr0
and Addr1, of the two words, DIN0 and DIN1, must only differ in address A0. This command should be used during manufacturing purposes only.
6. During the second bus cycle, the manufacturer code is read from address PA+00000H, the device code is read from address
PA+00001H, and the data in the protection register is read from addresses 000081H - 000088H.
7. The plane address should be the same during the first and second bus cycle.
8. The status register bits are output on I/O7 - I/O0.
9. Any address within the user programmable protection register region. Please see “Protection Register Addressing Table” on
page 16
10. For the AT49BV6416C, xxxx = 0000H. For the AT49BV6416CT, xxxx = 3F80H.
11. If data bit D1 is “0”, sector B is locked. If data bit D1 is “1”, sector B can be reprogrammed.
15
3465C–FLASH–07/05
5. Absolute Maximum Ratings*
*NOTICE:
Temperature under Bias ................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages Except VPP
(Including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
VPP Input Voltage
with Respect to Ground ............................................ 0V to 10V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
All Output Voltages
with Respect to Ground ...........................-0.6V to VCCQ + 0.6V
6. Protection Register Addressing Table
Word
Use
Block
A7
A6
A5
A4
A3
A2
A1
A0
0
Factory
A
1
0
0
0
0
0
0
1
1
Factory
A
1
0
0
0
0
0
1
0
2
Factory
A
1
0
0
0
0
0
1
1
3
Factory
A
1
0
0
0
0
1
0
0
4
User
B
1
0
0
0
0
1
0
1
5
User
B
1
0
0
0
0
1
1
0
6
User
B
1
0
0
0
0
1
1
1
7
User
B
1
0
0
0
1
0
0
0
Notes:
1. For the AT49BV6416C, all address lines not specified in the above table, A21 - A8, must be 0 when accessing the Protection
Register.
2. For the AT49BV6416CT, all address lines not specified in the table, A21 - A8, must be 3F80H when accessing the Protection
Register.
16
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
7. Memory Organization –
AT49BV6416C (Continued)
7. Memory Organization –
AT49BV6416C
x16
x16
Plane
Sector
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
A
SA0
4K
00000 - 00FFF
A
SA36
32K
E8000 - EFFFF
A
SA1
4K
01000 - 01FFF
A
SA37
32K
F0000 - F7FFF
A
SA2
4K
02000 - 02FFF
A
SA38
32K
F8000 - FFFFF
A
SA3
4K
03000 - 03FFF
B
SA39
32K
100000 - 107FFF
A
SA4
4K
04000 - 04FFF
B
SA40
32K
108000 - 10FFFF
A
SA5
4K
05000 - 05FFF
B
SA41
32K
110000 - 117FFF
A
SA6
4K
06000 - 06FFF
B
SA42
32K
118000 - 11FFFF
A
SA7
4K
07000 - 07FFF
B
SA43
32K
120000 - 127FFF
A
SA8
32K
08000 - 0FFFF
B
SA44
32K
128000 - 12FFFF
A
SA9
32K
10000 - 17FFF
B
SA45
32K
130000 - 137FFF
A
SA10
32K
18000 - 1FFFF
B
SA46
32K
138000 - 13FFFF
A
SA11
32K
20000 - 27FFF
B
SA47
32K
140000 - 147FFF
A
SA12
32K
28000 - 2FFFF
B
SA48
32K
148000 - 14FFFF
A
SA13
32K
30000 - 37FFF
B
SA49
32K
150000 - 157FFF
A
SA14
32K
38000 - 3FFFF
B
SA50
32K
158000 - 15FFFF
A
SA15
32K
40000 - 47FFF
B
SA51
32K
160000 - 167FFF
A
SA16
32K
48000 - 4FFFF
B
SA52
32K
168000 - 16FFFF
A
SA17
32K
50000 - 57FFF
B
SA53
32K
170000 - 177FFF
A
SA18
32K
58000 - 5FFFF
B
SA54
32K
178000 - 17FFFF
A
SA19
32K
60000 - 67FFF
B
SA55
32K
180000 - 187FFF
A
SA20
32K
68000 - 6FFFF
B
SA56
32K
188000 - 18FFFF
A
SA21
32K
70000 - 77FFF
B
SA57
32K
190000 - 197FFF
A
SA22
32K
78000 - 7FFFF
B
SA58
32K
198000 - 19FFFF
A
SA23
32K
80000 - 87FFF
B
SA59
32K
1A0000 - 1A7FFF
A
SA24
32K
88000 - 8FFFF
B
SA60
32K
1A8000 - 1AFFFF
A
SA25
32K
90000 - 97FFF
B
SA61
32K
1B0000 - 1B7FFF
A
SA26
32K
98000 - 9FFFF
B
SA62
32K
1B8000 - 1BFFFF
A
SA27
32K
A0000 - A7FFF
B
SA63
32K
1C0000 - 1C7FFF
A
SA28
32K
A8000 - AFFFF
B
SA64
32K
1C8000 - 1CFFFF
A
SA29
32K
B0000 - B7FFF
B
SA65
32K
1D0000 - 1D7FFF
A
SA30
32K
B8000 - BFFFF
B
SA66
32K
1D8000 - 1DFFFF
A
SA31
32K
C0000 - C7FFF
B
SA67
32K
1E0000 - 1E7FFF
A
SA32
32K
C8000 - CFFFF
B
SA68
32K
1E8000 - 1EFFFF
A
SA33
32K
D0000 - D7FFF
B
SA69
32K
1F0000 - 1F7FFF
A
SA34
32K
D8000 - DFFFF
B
SA70
32K
1F8000 - 1FFFFF
A
SA35
32K
E0000 - E7FFF
C
SA71
32K
200000 - 207FFF
17
3465C–FLASH–07/05
7. Memory Organization –
AT49BV6416C (Continued)
7. Memory Organization –
AT49BV6416C (Continued)
x16
Plane
18
Sector
x16
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
C
SA72
32K
208000 - 20FFFF
D
SA108
32K
328000 - 32FFFF
C
SA73
32K
210000 - 217FFF
D
SA109
32K
330000 - 337FFF
C
SA74
32K
218000 - 21FFFF
D
SA110
32K
338000 - 33FFFF
C
SA75
32K
220000 - 227FFF
D
SA111
32K
340000 - 347FFF
C
SA76
32K
228000 - 22FFFF
D
SA112
32K
348000 - 34FFFF
C
SA77
32K
230000 - 237FFF
D
SA113
32K
350000 - 357FFF
C
SA78
32K
238000 - 23FFFF
D
SA114
32K
358000 - 35FFFF
C
SA79
32K
240000 - 247FFF
D
SA115
32K
360000 - 367FFF
C
SA80
32K
248000 - 24FFFF
D
SA116
32K
368000 - 36FFFF
C
SA81
32K
250000 - 257FFF
D
SA117
32K
370000 - 377FFF
C
SA82
32K
258000 - 25FFFF
D
SA118
32K
378000 - 37FFFF
C
SA83
32K
260000 - 267FFF
D
SA119
32K
380000 - 387FFF
C
SA84
32K
268000 - 26FFFF
D
SA120
32K
388000 - 38FFFF
C
SA85
32K
270000 - 277FFF
D
SA121
32K
390000 - 397FFF
C
SA86
32K
278000 - 27FFFF
D
SA122
32K
398000 - 39FFFF
C
SA87
32K
280000 - 287FFF
D
SA123
32K
3A0000 - 3A7FFF
C
SA88
32K
288000 - 28FFFF
D
SA124
32K
3A8000 - 3AFFFF
C
SA89
32K
290000 - 297FFF
D
SA125
32K
3B0000 - 3B7FFF
C
SA90
32K
298000 - 29FFFF
D
SA126
32K
3B8000 - 3BFFFF
C
SA91
32K
2A0000 - 2A7FFF
D
SA127
32K
3C0000 - 3C7FFF
C
SA92
32K
2A8000 - 2AFFFF
D
SA128
32K
3C8000 - 3CFFFF
C
SA93
32K
2B0000 - 2B7FFF
D
SA129
32K
3D0000 - 3D7FFF
C
SA94
32K
2B8000 - 2BFFFF
D
SA130
32K
3D8000 - 3DFFFF
C
SA95
32K
2C0000 - 2C7FFF
D
SA131
32K
3E0000 - 3E7FFF
C
SA96
32K
2C8000 - 2CFFFF
D
SA132
32K
3E8000 - 3EFFFF
C
SA97
32K
2D0000 - 2D7FFF
D
SA133
32K
3F0000 - 3F7FFF
C
SA98
32K
2D8000 - 2DFFFF
D
SA134
32K
3F8000 - 3FFFFF
C
SA99
32K
2E0000 - 2E7FFF
C
SA100
32K
2E8000 - 2EFFFF
C
SA101
32K
2F0000 - 2F7FFF
C
SA102
32K
2F8000 - 2FFFFF
D
SA103
32K
300000 - 307FFF
D
SA104
32K
308000 - 30FFFF
D
SA105
32K
310000 - 317FFF
D
SA106
32K
318000 - 31FFFF
D
SA107
32K
320000 - 327FFF
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
8. Memory Organization –
AT49BV6416CT (Continued)
8. Memory Organization –
AT49BV6416CT
x16
x16
Plane
Sector
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
D
SA0
32K
00000 - 07FFF
C
SA36
32K
120000 - 127FFF
D
SA1
32K
08000 - 0FFFF
C
SA37
32K
128000 - 12FFFF
D
SA2
32K
10000 - 17FFF
C
SA38
32K
130000 - 137FFF
D
SA3
32K
18000 - 1FFFF
C
SA39
32K
138000 - 13FFFF
D
SA4
32K
20000 - 27FFF
C
SA40
32K
140000 - 147FFF
D
SA5
32K
28000 - 2FFFF
C
SA41
32K
148000 - 14FFFF
D
SA6
32K
30000 - 37FFF
C
SA42
32K
150000 - 157FFF
D
SA7
32K
38000 - 3FFFF
C
SA43
32K
158000 - 15FFFF
D
SA8
32K
40000 - 47FFF
C
SA44
32K
160000 - 167FFF
D
SA9
32K
48000 - 4FFFF
C
SA45
32K
168000 - 16FFFF
D
SA10
32K
50000 - 57FFF
C
SA46
32K
170000 - 177FFF
D
SA11
32K
58000 - 5FFFF
C
SA47
32K
178000 - 17FFFF
D
SA12
32K
60000 - 67FFF
C
SA48
32K
180000 - 187FFF
D
SA13
32K
68000 - 6FFFF
C
SA49
32K
188000 - 18FFFF
D
SA14
32K
70000 - 77FFF
C
SA50
32K
190000 - 197FFF
D
SA15
32K
78000 - 7FFFF
C
SA51
32K
198000 - 19FFFF
D
SA16
32K
80000 - 87FFF
C
SA52
32K
1A0000 - 1A7FFF
D
SA17
32K
88000 - 8FFFF
C
SA53
32K
1A8000 - 1AFFFF
D
SA18
32K
90000 - 97FFF
C
SA54
32K
1B0000 - 1B7FFF
D
SA19
32K
98000 - 9FFFF
C
SA55
32K
1B8000 - 1BFFFF
D
SA20
32K
A0000 - A7FFF
C
SA56
32K
1C0000 - 1C7FFF
D
SA21
32K
A8000 - AFFFF
C
SA57
32K
1C8000 - 1CFFFF
D
SA22
32K
B0000 - B7FFF
C
SA58
32K
1D0000 - 1D7FFF
D
SA23
32K
B8000 - BFFFF
C
SA59
32K
1D8000 - 1DFFFF
D
SA24
32K
C0000 - C7FFF
C
SA60
32K
1E0000 - 1E7FFF
D
SA25
32K
C8000 - CFFFF
C
SA61
32K
1E8000 - 1EFFFF
D
SA26
32K
D0000 - D7FFF
C
SA62
32K
1F0000 - 1F7FFF
D
SA27
32K
D8000 - DFFFF
C
SA63
32K
1F8000 - 1FFFFF
D
SA28
32K
E0000 - E7FFF
B
SA64
32K
200000 - 207FFF
D
SA29
32K
E8000 - EFFFF
B
SA65
32K
208000 - 20FFFF
D
SA30
32K
F0000 - F7FFF
B
SA66
32K
210000 - 217FFF
D
SA31
32K
F8000 - FFFFF
B
SA67
32K
218000 - 21FFFF
C
SA32
32K
100000 - 107FFF
B
SA68
32K
220000 - 227FFF
C
SA33
32K
108000 - 10FFFF
B
SA69
32K
228000 - 22FFFF
C
SA34
32K
110000 - 117FFF
B
SA70
32K
230000 - 237FFF
C
SA35
32K
118000 - 11FFFF
B
SA71
32K
238000 - 23FFFF
19
3465C–FLASH–07/05
8. Memory Organization –
AT49BV6416CT (Continued)
8. Memory Organization –
AT49BV6416CT (Continued)
x16
Plane
20
Sector
x16
Size (Words)
Address Range (A21 - A0)
Plane
Sector
Size (Words)
Address Range (A21 - A0)
B
SA72
32K
240000 - 247FFF
A
SA108
32K
360000 - 367FFF
B
SA73
32K
248000 - 24FFFF
A
SA109
32K
368000 - 36FFFF
B
SA74
32K
250000 - 257FFF
A
SA110
32K
370000 - 377FFF
B
SA75
32K
258000 - 25FFFF
A
SA111
32K
378000 - 37FFFF
B
SA76
32K
260000 - 267FFF
A
SA112
32K
380000 - 387FFF
B
SA77
32K
268000 - 26FFFF
A
SA113
32K
388000 - 38FFFF
B
SA78
32K
270000 - 277FFF
A
SA114
32K
390000 - 397FFF
B
SA79
32K
278000 - 27FFFF
A
SA115
32K
398000 - 39FFFF
B
SA80
32K
280000 - 287FFF
A
SA116
32K
3A0000 - 3A7FFF
B
SA81
32K
288000 - 28FFFF
A
SA117
32K
3A8000 - 3AFFFF
B
SA82
32K
290000 - 297FFF
A
SA118
32K
3B0000 - 3B7FFF
B
SA83
32K
298000 -29FFFF
A
SA119
32K
3B8000 - 3BFFFF
B
SA84
32K
2A0000 - 2A7FFF
A
SA120
32K
3C0000 - 3C7FFF
B
SA85
32K
2A8000 - 2AFFFF
A
SA121
32K
3C8000 - 3CFFFF
B
SA86
32K
2B0000 - 2B7FFF
A
SA122
32K
3D0000 - 3D7FFF
B
SA87
32K
2B8000 - 2BFFFF
A
SA123
32K
3D8000 - 3DFFFF
B
SA88
32K
2C0000 - 2C7FFF
A
SA124
32K
3E0000 - 3E7FFF
B
SA89
32K
2C8000 - 2CFFFF
A
SA125
32K
3E8000 - 3EFFFF
B
SA90
32K
2D0000 - 2D7FFF
A
SA126
32K
3F0000 - 3F7FFF
B
SA91
32K
2D8000 - 2DFFFF
A
SA127
4K
3F8000 - 3F8FFF
B
SA92
32K
2E0000 - 2E7FFF
A
SA128
4K
3F9000 - 3F9FFF
B
SA93
32K
2E8000 - 2EFFFF
A
SA129
4K
3FA000 - 3FAFFF
B
SA94
32K
2F0000 - 2F7FFF
A
SA130
4K
3FB000 - 3FBFFF
B
SA95
32K
2F8000 - 2FFFFF
A
SA131
4K
3FC000 - 3FCFFF
A
SA96
32K
300000 - 307FFF
A
SA132
4K
3FD000 - 3FDFFF
A
SA97
32K
308000 - 30FFFF
A
SA133
4K
3FE000 - 3FEFFF
A
SA98
32K
310000 - 317FFF
A
SA134
4K
3FF000 - 3FFFFF
A
SA99
32K
318000 - 31FFFF
A
SA100
32K
320000 - 327FFF
A
SA101
32K
328000 - 32FFFF
A
SA102
32K
330000 - 337FFF
A
SA103
32K
338000 - 33FFFF
A
SA104
32K
340000 - 347FFF
A
SA105
32K
348000 - 34FFFF
A
SA106
32K
350000 - 357FFF
A
SA107
32K
358000 - 35FFFF
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
9. DC and AC Operating Range
AT49BV6416C(T)-70
Operating Temperature (Case)
Industrial
-40°C - 85°C
VCC Power Supply
2.7V - 3.6V
10. Operating Modes
Mode
CE
Read
VIL
(3)
OE
VIL
VPP(4)
Ai
I/O
VIH
X
Ai
DOUT
Ai
DIN
X
High Z
WE
Reset
VIH
Program/Erase
VIL
VIH
VIL
VIH
VIHPP(5)
Standby/Program
Inhibit
VIH
X(1)
X
VIH
X
X
X
VIH
VIH
X
X
VIL
X
VIH
X
X
X
X
X
VILPP(6)
Output Disable
X
VIH
X
VIH
X
Reset
X
X
X
VIL
X
Program Inhibit
High Z
X
High Z
A0 = VIL, A1 - A21 = VIL
Manufacturer Code(3)
A0 = VIH, A1 - A21 = VIL
Device Code(3)
Product Identification
Software
Notes:
VIH
1. X can be VIL or VIH.
2. Refer to AC programming waveforms.
3. Manufacturer Code: 001FH; Device Code: 00C5H – AT49BV6416C; 00DFH – AT49BV6416CT
4. The VPP pin can be tied to VCC. For faster program/erase operations, VPP can be set to 9.5V ± 0.5V.
5. VIHPP (min) = 1.65V.
6. VILPP (max) = 0.7V.
21
3465C–FLASH–07/05
11. DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
Max
Units
VIN = 0V to VCC
1
µA
Output Leakage Current
VI/O = 0V to VCC
1
µA
ISB1
VCC Standby Current CMOS
CE = VCCQ - 0.3V to VCC
35
µA
ICC(1)
VCC Active Current
f = 5 MHz; IOUT = 0 mA
30
mA
ICCRE
VCC Read While Erase Current
f = 5 MHz; IOUT = 0 mA
60
mA
ICCRW
VCC Read While Write Current
f = 5 MHz; IOUT = 0 mA
60
mA
VIL
Input Low Voltage
0.6
V
VIH
Input High Voltage
VOL
Output Low Voltage
IOL = 2.1 mA
VOH
Output High Voltage
IOH = -100 µA; VCCQ = 2.2V - 3.6V
Note:
Min
VCCQ - 0.6
V
0.45
V
VCCQ - 0.1
V
1. In the erase mode, ICC is 35 mA.
12. Input Test Waveforms and Measurement Level
2.0V
AC
DRIVING
LEVELS
1.5V
AC
MEASUREMENT
LEVEL
0.6V
tR, tF < 5 ns
13. Output Test Load
VCCQ
1.8K
OUTPUT
PIN
1.3K
30 pF
14. Pin Capacitance
f = 1 MHz, T = 25°C(1)
CIN
COUT
Note:
22
Typ
Max
Units
Conditions
4
6
pF
VIN = 0V
8
12
pF
VOUT = 0V
1. This parameter is characterized and is not 100% tested.
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
15. AC Asynchronous Read Timing Characteristics
Symbol
Parameter
Min
Max
tRC
Read Cycle Time
tACC
Access, Address to Data Valid
70
ns
tCE
Access, CE to Data Valid
70
ns
tOE
OE to Data Valid
20
ns
tDF
CE, OE High to Data Float
25
ns
tOH
Output Hold from OE, CE or Address, whichever Occurs First
tRO
Reset to Output Delay
70
Units
ns
0
ns
150
ns
16. Asynchronous Read Cycle Waveform(1)(2)(3)
tRC
ADDRESS VALID
A0 - A21
CE
tCE
tOE
OE
tDF
tOH
tACC
tRO
RESET
I/O0 - I/O15
Notes:
HIGH Z
OUTPUT
VALID
1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC.
2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change
without impact on tACC.
3. tDF is specified from OE or CE, whichever occurs first (CL = 5 pF).
23
3465C–FLASH–07/05
17. AC Asynchronous Read Timing Characteristics
Symbol
Parameter
Min
Max
Units
tACC
Access, Address to Data Valid
70
ns
tCE
Access, CE to Data Valid
70
ns
tOE
OE to Data Valid
20
ns
tDF
CE, OE High to Data Float
25
ns
tRO
Reset to Output Delay
150
ns
tPAA
Page Address Access Time
20
ns
18. Page Read Cycle Waveform
tCE
CE
tDF
I/O0-I/O15
DATA VALID
tACC
tDF
A2 -A21
tPAA
tACC
A0 -A1
tOE
OE
tRO
RESET
24
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
19. AC Word Load Characteristics
Symbol
Parameter
Min
Max
Units
tAS
Address Setup Time to WE and CE High
50
ns
tAH
Address Hold Time
0
ns
tDS
Data Setup Time
50
ns
tDH
Data Hold Time
0
ns
tWP
CE or WE Low Pulse Width
35
ns
tWPH
CE or WE High Pulse Width
25
ns
20. AC Word Load Waveforms
20.1
WE Controlled
CE
I/O0 - I/O15
DATA VALID
A0 - A21
WE
20.2
CE Controlled
WE
I/O0 - I/O15
DATA VALID
A0 - A21
CE
25
3465C–FLASH–07/05
21. Program Cycle Characteristics
Symbol
Parameter
Min
tBP
Word Programming Time
15
µs
tSEC1
Sector Erase Cycle Time (4K word sectors)
200
ms
tSEC2
Sector Erase Cycle Time (32K word sectors)
700
ms
tES
Erase Suspend Time
15
µs
tPS
Program Suspend Time
10
µs
tERES
Delay between Erase Resume and Erase Suspend
500
Typ
Max
Units
µs
22. Program Cycle Waveforms
PROGRAM CYCLE
OE
(2)
CE
tBP
tWP
WE
tWPH
tDH
tAS
tAH
(1)
A0 - A21
ADDRESS
XX
tWC
I/O0 - I/O15
tDS
INPUT DATA
Note 3
23. Sector, Plane or Chip Erase Cycle Waveforms
OE
(2)
CE
tWP
tWPH
WE
tDH
tAS
A0 - A21
XX
tAH
(1)
Note 4
tWC
I/O0 - I/O15
Notes:
tDS
tSEC1/2
Note 5
D0
WORD 0
WORD 1
1. Any address can be used to load data.
2. OE must be high only when WE and CE are both low.
3. The data can be 40H or 10H.
4. For chip erase, any address can be used. For plane erase or sector erase, the address depends on what plane or sector is
to be erased.
5. For chip erase, the data should be 21H, for plane erase, the data should be 22H, and for sector erase, the data should
be 20H.
26
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
24. Common Flash Interface Definition Table
Address
AT49BV6416CT
AT49BV6416C
Comments
10h
0051h
0051h
“Q”
11h
0052h
0052h
“R”
12h
0059h
0059h
“Y”
13h
0003h
0003h
14h
0000h
0000h
15h
0041h
0041h
16h
0000h
0000h
17h
0000h
0000h
18h
0000h
0000h
19h
0000h
0000h
1Ah
0000h
0000h
1Bh
0027h
0027h
VCC min write/erase
1Ch
0036h
0036h
VCC max write/erase
1Dh
0009h
0009h
VPP min voltage
1Eh
000Ah
000Ah
VPP max voltage
1Fh
0004h
0004h
Typ word write – 15 µs
20h
0000h
0000h
21h
0009h
0009h
Typ block erase – 500 ms
22h
0010h
0010h
Typ chip erase – 64,300 ms
23h
0004h
0004h
Max word write/typ time
24h
0000h
0000h
n/a
25h
0003h
0003h
Max block erase/typ block erase
26h
0003h
0003h
Max chip erase/ typ chip erase
27h
0017h
0017h
Device size
28h
0001h
0001h
x16 device
29h
0000h
0000h
x16 device
2Ah
0000h
0000h
Multiple byte write not supported
2Bh
0000h
0000h
Multiple byte write not supported
2Ch
0002h
0002h
2 regions, x = 2
2Dh
007Eh
0007h
64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom)
2Eh
0000h
0000h
64K bytes, Y = 126 (Top); 8K bytes, Y = 7 (Bottom)
2Fh
0000h
0020h
64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
30h
0001h
0000h
64K bytes, Z = 256 (Top); 8K bytes, Z = 32 (Bottom)
31h
0007h
007Eh
8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom)
32h
0000h
0000h
8K bytes, Y = 7 (Top); 64K bytes, Y = 126 (Bottom)
33h
0020h
0000h
8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom)
34h
0000h
0001h
8K bytes, Z = 32 (Top);64K bytes, Z = 256 (Bottom)
27
3465C–FLASH–07/05
24. Common Flash Interface Definition Table
Address
AT49BV6416CT
AT49BV6416C
Comments
VENDOR SPECIFIC EXTENDED QUERY
41h
0050h
0050h
“P”
42h
0052h
0052h
“R”
43h
0049h
0049h
“I”
44h
0031h
0031h
Major version number, ASCII
45h
0030h
0030h
Minor version number, ASCII
46h
00AFh
00AFh
Bit 0 – chip erase supported, 0 – no, 1 – yes
Bit 1 – erase suspend supported, 0 – no, 1 – yes
Bit 2 – program suspend supported, 0 – no, 1 – yes
Bit 3 – simultaneous operations supported, 0 – no, 1 – yes
Bit 4 – burst mode read supported, 0 – no, 1 – yes
Bit 5 – page mode read supported, 0 – no, 1 – yes
Bit 6 – queued erase supported, 0 – no, 1 – yes
Bit 7 – protection bits supported, 0 – no, 1 – yes
47h
0000h
0001h
Bit 0 – top (“0”) or bottom (“1”) boot block device
Undefined bits are “0”
0000h
Bit 0 – 4 word linear burst with wrap around, 0 – no, 1 – yes
Bit 1 – 8 word linear burst with wrap around, 0 – no, 1 – yes
Bit 2 – 16 word linear burst with wrap around, 0 – no, 1 – yes
Bit 3 – continuous burst, 0 – no, 1 – yes
Undefined bits are “0”
48h
28
0000h
49h
0001h
0001h
Bit 0 – 4 word page, 0 – no, 1 – yes
Bit 1 – 8 word page, 0 – no, 1 – yes
Undefined bits are “0”
4Ah
0080h
0080h
Location of protection register lock byte, the section’s first byte
4Bh
0003h
0003h
# of bytes in the factory prog section of prot register – 2*n
4Ch
0003h
0003h
# of bytes in the user prog section of prot register – 2*n
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
25. Ordering Information
25.1
Standard Packaging
ICC (mA)
tACC
(ns)
Active
Standby
Ordering Code
Package
Operation Range
70
30
0.035
AT49BV6416C-70CI
48C20
Industrial
(-40° to 85°C)
70
30
0.035
AT49BV6416CT-70CI
48C20
Industrial
(-40° to 85°C)
Package Type
48C20
48-ball, Plastic Chip-size Ball Grid Array Package (CBGA)
29
3465C–FLASH–07/05
26. Packaging Information
26.1
48C20 – CBGA
E
A1 BALL ID
D
Top View
A1
A
E1
0.875 REF
e
A1 BALL CORNER
Side View
3.125 REF
COMMON DIMENSIONS
(Unit of Measure = mm)
A
SYMBOL
MIN
NOM
MAX
6.90
7.00
7.10
NOTE
B
E
C
D1
D
E1
D
E
5.25 TYP
9.90
D1
F
7
6
5
4
3
2
1
10.10
3.75 TYP
A
–
–
1.0
A1
0.21
–
–
e
8
10.00
b
Ø
0.75 BSC
0.35 TYP
Øb
Bottom View
01/8/04
R
30
2325 Orchard Parkway
San Jose, CA 95131
TITLE
48C20, 48-ball (8 x 6 Array),0.75 mm Pitch, 7.0 x 10.0 x 1.0 mm
Chip-scale Ball Grid Array Package (CBGA)
DRAWING NO.
48C20
REV.
A
AT49BV6416C(T)
3465C–FLASH–07/05
AT49BV6416C(T)
27. Revision History
Revision No.
History
Revision A – April 2004
•
Initial Release
Revision B – November 2004
•
•
•
•
Removed “Preliminary” from the datasheet.
Modified note 6 and added notes 7 and 10 on page 13.
Modified note 1 and added note 2 on page 14.
Changed the ISB1 spec to 35 µA.
•
•
Converted datasheet to new template.
Changed the VPP value to 9.5 ± 0.5V in the text, tables on
pages 15, 16, 21 and CFI table on page 27. VPP text also
changed to show that a high voltage on VPP improves
only the programming time.
Changed the maximum voltage that can be applied on the
address inputs and control inputs to 5.5V on page 9.
Changed the maximum input voltage under absolute maximum
ratings to 6.25V on page 16.
Revision C – July 2005
•
•
31
3465C–FLASH–07/05
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3465C–FLASH–07/05