NLAS7222A High−Speed USB 2.0 (480 Mbps) DPDT Switch ON Semiconductor’s NLAS7222A series of analog switch circuits are produced using the company’s advanced sub−micron CMOS technology, achieving industry−leading performance. The NLAS7222A is a 2− to 1−port analog switch. Its wide bandwidth and low bit−to−bit skew allow it to pass high−speed differential signals with good signal integrity. The switch is bidirectional and offers little or no attenuation of the high−speed signals at the outputs. Industry−leading advantages include a propagation delay of less than 250 ps, resulting from its low channel resistance and low I/O capacitance. Its high channel−to−channel crosstalk rejection results in minimal noise interference. Its bandwidth is wide enough to pass High−Speed USB 2.0 differential signals (480 Mb/s). http://onsemi.com MARKING DIAGRAM • • • • • • • XX M G G UQFN−10 CASE 488AT XX M G G 1 Features • • • • WQFN−10 CASE 488AQ 1 RON is Typically 6.5 at VCC = 3 V Low Bit−to−Bit Skew: Typically 50 ps OVT on D+ and D− up to 3.6 V Power OFF Protection: When VCC = 0 V, D+ and D− Can Tolerate up to 3.6 V Low Crosstalk: −45 dB @ 250 MHz Low Current Consumption: 1 A Near−Zero Propagation Delay: 250 ps Channel On−Capacitance: 6.5 pF (Typical) VCC Operating Range: +3.0 V to +3.6 V > 700 MHz Bandwidth (or Data Frequency) This is a Pb−Free Device XX = Device Code xx = 2A or Y = Date Code M G = Pb−Free Device (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet. Typical Applications • Differential Signal Data Routing • USB 2.0 Signal Routing Important Information • Continuous Current Rating Through Each Switch ±50 mA • 8 kV I/O to GND ESD Protection © Semiconductor Components Industries, LLC, 2007 February, 2007 − Rev. 1 1 Publication Order Number: NLAS7222A/D NLAS7222A HSD1− 7 HSD2− Table 1. PIN DESCRIPTION 6 Pin Function S OE 8 VCC 9 S 10 5 CONTROL 1 2 HSD1+ HSD2+ D− Select Input OE 4 GND 3 D+ Output Enable HSD1+, HSD1−, HSD2+, HSD2−, D+, D− Data Ports Table 2. TRUTH TABLE OE S HSD1+, HSD1− HSD2+, HSD2− 1 0 0 X 0 1 OFF ON OFF OFF OFF ON Figure 1. Pin Connections and Logic Diagram (Top View) MAXIMUM RATINGS Symbol Parameter VCC Positive DC Supply Voltage VIS Analog Switch Input Voltage HSD1+, HSD1−, HSD2+, HSD2− D+, D− VIN Digital Select Input Voltage ID PD TS Storage Temperature ESD Human Body Model I/O to GND All Pins Value Unit −0.5 to +4.6 V V −0.5 to VCC + 0.3 −0.5 to +4.6 −0.5 to +4.6 V Continuous DC Current (Through Analog Switch) 50 mA Power Dissipation 0.5 W −65 to +150 °C kV 8 2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit 3.0 3.6 V VCC V VCC Positive DC Supply Voltage VIS Analog I/O Voltage (HSD1+, HSD1−, HSD2+, HSD2−) GND VOS Analog Common Output Voltage (D+, D−) GND 3.6 V VIN Digital Select Input Voltage GND VCC V TA Operating Temperature Range −40 +85 °C tr, tf Input Rise or Fall Time 0 15 ns VCC = 3.3 V ± 0.3 V http://onsemi.com 2 NLAS7222A DC ELECTRICAL CHARACTERISTICS FOR USB 2.0 SWITCHING OVER OPERATIONAL RANGE −40°C to +85°C Symbol Parameter Test Conditions VCC (V) Min Typ (Note 1) Max Unit VIH Input HIGH Voltage (VIN) 3.0 to 3.6 1.3 − − V VIL Input LOW Voltage (VIN) 3.0 to 3.6 − − 0.5 V VIK Clamp Diode Voltage IIS = −18 mA 3.0 − − −1.2 V ICC Quiescent Supply Current VIS = VCC or GND; ID = 0 A 3.6 − − 1.0 A ICCT Increase in ICC per Control Voltage VIN = 2.6 V 3.6 − − 10.0 A II Input Leakage Current 0 ≤ VIS ≤ VCC 3.6 − − ±1.0 A IOZ OFF State Leakage 0 ≤ VIS; VOS ≤ VCC 3.6 − − ±1.0 A IOFF Power OFF Leakage Current (D+, D−) 0 ≤ VIS; VOS ≤ VCC 0 − − ±1.0 A RON Switch On−Resistance VIS = 0 to 0.4 V; ID = 8 mA 3.0 − 6.5 9.0 RFLAT(ON) On−Resistance Flatness VIS = 0 to 1.0 V; ID = 8 mA 3.0 − 2.0 − RON On−Resistance match from center ports to any other ports VIS = 0 to 0.4 V; ID = 8 mA 3.0 − 0.35 − 1. Typical values are at VCC = 3.3 V and TA = +25°C AC ELECTRICAL CHARACTERISTICS −405C to +855C Symbol Parameter Test Conditions VCC (V) Min Typ (Note 2) Max Unit tON Turn−ON Time VIS = 0.8 V 3.0 to 3.6 − 13.0 30.0 ns tOFF Turn−OFF Time VIS = 0.8 V 3.0 to 3.6 − 12.0 25.0 ns tBBM Break−Before−Make Delay VIS = 0.8 V 3.0 to 3.6 2.0 4.7 6.5 ns Propagation Delay CL = 10 pF 3.0 to 3.6 − 0.25 − ns OIRR tPD OFF−Isolation f = 250 MHz; RL = 50 3.0 to 3.6 − −28 − dB XTALK Non−Adjacent Channel Crosstalk f = 250 MHz; RL = 50 3.0 to 3.6 − −45 − dB −3 dB Bandwidth RL = 50 ; CL = 0 pF − 700 − MHz − 500 − BW RL = 50 ; CL = 5 pF 3.0 to 3.6 AC ELECTRICAL CHARACTERISTICS FOR USB 2.0 SWITCHING OVER OPERATIONAL RANGE tSK(O) TJITTER Channel−to−Channel Skew CL = 10 pF 3.0 to 3.6 − 0.05 − ns Total Jitter RL = 50 ; CL = 10 pF tr = tf = 500 ps at 480 Mbps 3.0 to 3.6 − 0.2 − ns 2. Typical values are at VCC = 3.3 V and TA = +25°C CAPACITANCE −405C to +855C Symbol Parameter Test Conditions Min Typ (Note 3) Max Unit CIN Control Pin Input Capacitance VCC = 0 V − 4.5 − pF CON HSD+, HSD− ON Capacitance VCC = 3.3 V; OE = 0 V − 14 − pF COFF HSD+, HSD− OFF Capacitance VCC = VIS = 3.3 V; OE = 3.3 V − 12 − pF 3. Typical values are at VCC = 3.3 V and TA = +25°C http://onsemi.com 3 NLAS7222A VCC DUT VCC Input Output GND VOUT 0.1 F 50 35 pF tBMM Output 50 % OF DROOP VOLTAGE DROOP Switch Select Pin Figure 2. tBBM (Time Break−Before−Make) VCC Input DUT VCC 0.1 F 50% Output VOUT Open 50% 0V 50 VOH 90% 35 pF 90% Output VOL Input tON tOFF Figure 3. tON/tOFF VCC VCC Input DUT Output 50 50% 0V VOUT Open 50% VOH 35 pF Output Input tOFF Figure 4. tON/tOFF http://onsemi.com 4 10% 10% VOL tON NLAS7222A 50 DUT Reference Transmitted Input Output 50 Generator 50 Channel switch control/s test socket is normalized. Off isolation is measured across an off channel. On loss is the bandwidth of an On switch. VISO, Bandwidth and VONL are independent of the input signal direction. ǒVVOUT Ǔ for VIN at 100 kHz IN VOUT Ǔ for VIN at 100 kHz to 50 MHz VONL = On Channel Loss = 20 Log ǒ VIN VISO = Off Channel Isolation = 20 Log Bandwidth (BW) = the frequency 3 dB below VONL VCT = Use VISO setup and test to all other switch analog input/outputs terminated with 50 Figure 5. Off Channel Isolation/On Channel Loss (BW)/Crosstalk (On Channel to Off Channel)/VONL DUT VCC VIN Output Open GND CL Output Off VIN Figure 6. Charge Injection: (Q) http://onsemi.com 5 On Off VOUT NLAS7222A APPLICATIONS INFORMATION (www.usb.org), the industry group responsible for defining the USB certification requirements. The test patterns were generated by a PC and MATLAB software, and were inputted to the analog switch through USB connectors J1 (HSD1) or J2 (HSD2). A USB certified device was plugged into connector J4 to function as a data transceiver. The high speed and full speed tests used a flash memory device, while the low speed tests used a mouse. Test connectors J3 and J5 provide a direct connection of the USB device and were used to verify that the analog switch does not distort the data signals. The low on resistance and capacitance of the NLAS7222A provides for a high bandwidth analog switch suitable for applications such as USB data switching. Results for the USB 2.0 signal quality tests will be shown in this section, along with a description of the evaluation test board. The data for the eye diagram signal quality and jitter tests verifies that the NLAS7222A can be used as a data switch in low, full and high speed USB 2.0 systems. Figures 7, 8 and 9 provide a description of the test evaluation board. The USB tests were conducted per the procedures provided by the USB Implementers Forum Figure 7. Schematic of the NLAS7222A USB Demo Board http://onsemi.com 6 NLAS7222A Figure 8. Block Diagram of the NLAS7222A USB Demo Board Figure 9. Photograph of the NLAS7222A USB Demo Board http://onsemi.com 7 NLAS7222A AND8267/D – NLAS7222A USB 2.0 Signal Quality Compliance Tests Figures 10, 11 and 12 show the test results for USB eye diagram tests. A summary of the USB tests is provided in Table 3. The NLAS7222A passes the low, full and high speed signal quality, eye diagram and jitter tests. Application note AND8267/D provides a detailed description of the USB 2.0 test results. Figure 10. Low Speed Signal Quality Eye Diagram Test (NLAS7222A with VCC = 3.6 V) Figure 11. Full Speed Signal Quality Eye Diagram Test (NLAS7222A with VCC = 3.6 V) http://onsemi.com 8 NLAS7222A Figure 12. High Speed Signal Quality Eye Diagram Test (NLAS7222A with VCC = 3.0 V) Table 3. Summary of the USB 2.0 Signal Quality Tests Results Compliance Test Low Speed Full Speed High Speed Signal Quality Test Pass Pass Pass Signal Eye Test Pass Pass Pass EOP Width 1.29 ms 166.86 ns 7.98 bits Measured Signal Rate 1.5140 MHz 12.0016 MHz 480.0685 MHz Crossover Voltage Range 1.75 to 1.83 V, mean crossover = 1.78 V 1.70 to 1.73 V, mean crossover = 1.71 V N/A Connective Jitter Range −2.2 to 2.2 ns, RMS jitter = 1.3 ns −0.2 to 0.2 ns, RMS jitter = 0.1 ns −79.4 to 77.4 ps, RMS jitter = 35.0 ps Paired JK Jitter Range −1.4 to 2.7 ns, RMS jitter = 1.3 ns −0.1 to 0.1 ns, RMS jitter = 0.1 ns −93.2 to 78.7 ps, RMS jitter = 24.4 ps Paired KJ Jitter Range −1.9 to 1.1 ns, RMS jitter = 1.0 ns −0.2 to 0.1 ns, RMS jitter = 0.1 ns −72.8 to 50.9 ps, RMS jitter = 15.6 ps ORDERING INFORMATION Device Package NLAS7222AMTR2G WQFN−10 (Pb−Free) NLAS7222AMUR2G UQFN−10 (Pb−Free) Shipping† 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. http://onsemi.com 9 NLAS7222A PACKAGE DIMENSIONS WQFN10, 1.4x1.8x0.4P CASE 488AQ−01 ISSUE B D ÉÉÉ ÉÉÉ ÉÉÉ PIN 1 REFERENCE 2X 2X 0.15 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. EXPOSED PADS CONNECTED TO DIE FLAG. USED AS TEST CONTACTS. A E 0.15 C DIM A A1 A3 b D E e L L1 B A 0.10 C 0.08 C SEATING PLANE MILLIMETERS MIN MAX 0.70 0.80 0.00 0.050 0.20 REF 0.15 0.25 1.40 BSC 1.80 BSC 0.40 BSC 0.30 0.50 0.40 0.60 A1 A3 3 9X 5 C SOLDERING FOOTPRINT* e/2 1.700 0.0669 L 6 e 1 0.663 0.0261 0.200 0.0079 10 L1 10 X b 0.10 C A B 0.05 C 9X 0.563 0.0221 1 2.100 0.0827 NOTE 3 0.400 0.0157 PITCH 10 X 0.225 0.0089 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 10 NLAS7222A PACKAGE DIMENSIONS 10 PIN UQFN, 1.4x1.8, 0.4P CASE 488AT−01 ISSUE O ÉÉÉ ÉÉÉ ÉÉÉ D PIN 1 REFERENCE 2X 2X 0.10 C E 0.10 C DIM A A1 b D E e L L3 B 0.05 C 10X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A A 0.05 C A1 C MILLIMETERS MIN MAX 0.45 0.60 0.00 0.05 0.15 0.25 1.40 BSC 1.80 BSC 0.40 BSC 0.30 0.50 0.40 0.60 MOUNTING FOOTPRINT* SEATING PLANE 1.700 0.0669 3 9X 5 0.663 0.0261 e/2 L 6 10 L3 0.200 0.0079 e 1 10 X b 1 2.100 0.0827 0.10 C A B 0.05 C 9X 0.563 0.0221 NOTE 3 0.400 0.0157 PITCH 10 X 0.225 0.0089 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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