AD AD5560JSVUZ 1.2 a programmable device power supply Datasheet

Data Sheet
1.2 A Programmable Device Power Supply
with Integrated 16-Bit Level Setting DACs
AD5560
FEATURES
Programmable device power supply (DPS)
FV, MI, MV, FNMV functions
5 internal current ranges (on-chip RSENSE)
±5 µA, ±25 µA, ±250 µA, ±2.5 mA, ±25 mA
2 external high current ranges (external RSENSE)
EXTFORCE1: ±1.2 A maximum
EXTFORCE2: ±500 mA maximum
Integrated programmable levels
All 16-bit DACs: force DAC, comparator DACs, clamp DACs,
offset DAC, OSD DAC, DGS DAC
Programmable Kelvin clamp and alarm
Offset and gain correction registers on-chip
Ramp mode on force DAC for power supply slewing
Programmable slew rate feature, 1 V/μs to 0.3 V/μs
DUTGND Kelvin sense and alarm
25 V FV span with asymmetrical operation within −22 V/+25 V
On-chip comparators
Gangable for higher current
Guard amplifier
System PMU connections
Current clamps
Die temperature sensor and shutdown feature
On-chip diode thermal array
Diagnostic register allows access to internal nodes
Open-drain alarm flags (temperature, current clamp, Kelvin
alarm)
SPI-/MICROWIRE-/DSP-compatible interface
64-lead (10 mm × 10 mm) TQFP with exposed pad (on top)
72-ball (8 mm × 8 mm) flip-chip BGA
APPLICATIONS
Automatic test equipment (ATE)
Device power supply
GENERAL DESCRIPTION
The AD5560 is a high performance, highly integrated device
power supply consisting of programmable force voltages and
measure ranges. This part includes the required DAC levels to
set the programmable inputs for the drive amplifier, as well as
clamping and comparator circuitry. Offset and gain correction
is included on-chip for DAC functions. A number of programmable measure current ranges are available: five internal fixed
ranges and two external customer-selectable ranges (EXTFORCE1
and EXTFORCE2) that can supply currents up to ±1.2 A and
±500 mA, respectively. The voltage range possible at this high
current level is limited by headroom and the maximum power
dissipation. Current ranges in excess of ±1.2 A or at high
current and high voltage combinations can be achieved by
paralleling or ganging multiple DPS devices. Open-drain
alarm outputs are provided in the event of overcurrent,
overtemperature, or Kelvin alarm on either the SENSE or
DUTGND line.
The DPS functions are controlled via a simple 3-wire serial
interface compatible with SPI, QSPI™, MICROWIRE™, and DSP
interface standards running at clock speeds of up to 50 MHz.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008-2012 Analog Devices, Inc. All rights reserved.
AD5560
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Adjusting the Autocompensation Mode ................................. 39
Applications ....................................................................................... 1
Dealing with Parallel Load Capacitors .................................... 39
General Description ......................................................................... 1
DAC Levels .................................................................................. 39
Revision History ............................................................................... 3
Force and Comparator DACs ................................................... 39
Functional Block Diagram .............................................................. 4
Clamp DACs ............................................................................... 39
Specifications..................................................................................... 5
OSD DAC .................................................................................... 40
Timing Characteristics .............................................................. 13
DUTGND DAC .......................................................................... 40
Timing Diagrams........................................................................ 13
Offset DAC .................................................................................. 40
Absolute Maximum Ratings .......................................................... 15
Offset and Gain Registers.......................................................... 40
ESD Caution ................................................................................ 15
Reference Selection .................................................................... 41
Pin Configurations and Function Descriptions ......................... 16
Choosing AVDD/AVSS Power Supply Rails ............................... 41
Typical Performance Characteristics ........................................... 20
Choosing HCAVSSx and HCAVDDx Supply Rails ................... 41
Terminology .................................................................................... 28
Power Dissipation....................................................................... 41
Theory of Operation ...................................................................... 29
Package Composition and Maximum Vertical Force ............ 42
Force Amplifier ........................................................................... 29
Slew Rate Control ....................................................................... 42
DAC Reference Voltage (VREF) ............................................... 29
Serial Interface ................................................................................ 44
Open-Sense Detect (OSD) Alarm and Clamp ....................... 29
SPI Interface ................................................................................ 44
Device Under Test Ground (DUTGND)................................. 29
SPI Write Mode .......................................................................... 44
GPO .............................................................................................. 30
SDO Output ................................................................................ 44
Comparators................................................................................ 30
RESET Function ......................................................................... 44
Current Clamps .......................................................................... 30
BUSY Function ........................................................................... 44
Short-Circuit Protection ............................................................ 30
LOAD Function .......................................................................... 44
Guard Amplifier ......................................................................... 30
Register Update Rates ................................................................ 45
Compensation Capacitors ......................................................... 30
Control Registers ............................................................................ 46
Current Range Selection ............................................................ 31
DPS and DAC Addressing ........................................................ 46
High Current Ranges ................................................................. 31
Readback Mode .......................................................................... 57
Ideal Sequence for Gang Mode ................................................. 32
DAC Readback............................................................................ 57
Compensation for Gang Mode ................................................. 32
Power-On Default ...................................................................... 57
System Force/Sense Switches .................................................... 32
Using the HCAVDDx and HCAVSSx Supplies .......................... 59
Die Temperature Sensor and Thermal Shutdown.................. 33
Power Supply Sequencing ......................................................... 59
Measure Output (MEASOUT) ................................................. 33
Required External Components ............................................... 60
VMID Voltage ................................................................................ 33
Power Supply Decoupling ......................................................... 61
Force Amplifier Stability............................................................ 36
Applications Information .............................................................. 62
Poles and Zeros in a Typical System ........................................ 37
Thermal Considerations............................................................ 62
Minimizing the Number of External Compensation
Components ................................................................................ 37
Temperature Contour Map on the Top of the Package ......... 63
Extra Poles and Zeros in the AD5560...................................... 37
Compensation Strategies ........................................................... 38
Outline Dimensions ....................................................................... 64
Ordering Guide .......................................................................... 65
Optimizing Performance for a Known Capacitor Using
Autocompensation Mode .......................................................... 38
Rev. D | Page 2 of 68
Data Sheet
AD5560
REVISION HISTORY
8/12—Rev. C to Rev. D
12/08—Rev. 0 to Rev. A
Added 72-Ball Flip-Chip BGA (Throughout) ............................... 1
Added Figure 7 and Table 5 (Renumbered Sequentially) ..........18
Added Applications Information Section ....................................62
Updated Outline Dimensions ........................................................64
Changes to Ordering Guide ...........................................................65
Changes to Figure 1 .......................................................................... 4
Changes to Table 1 ............................................................................ 4
Changes to Table 2 .......................................................................... 13
Changes to Table 3 .......................................................................... 15
Changes to Open-Sense Detect (OSD) Alarm and Clamp ....... 27
Changes to Figure 53 ...................................................................... 30
Change to gm Maximum Rating, Table 13 .................................. 34
Changes to Table 19 ........................................................................ 46
Changes to Bit 7, Bit 8 Functions, Table 21 ................................. 48
Changes to Power Supply Decoupling Section ........................... 59
10/10—Rev. B to Rev. C
Changes to Force Output Voltage Parameter and Load Transient
Response Parameter, Table 1............................................................ 5
Changes to Figure 52 ......................................................................29
Changes to Table 9 ..........................................................................32
9/09—Rev. A to Rev. B
11/08—Revision 0: Initial Version
Changes to Table 1, Measure Current and Measure Voltage
Parameters .......................................................................................... 6
Changes to Die Temperature Sensor and Thermal
Shutdown Section ............................................................................31
Changes to Table 10 and Table 11 .................................................32
Changes to Table 18, Bit 15 ............................................................45
Changes to Table 23, Bits[15:12] ...................................................50
Changes to Table 25 ........................................................................54
Rev. D | Page 3 of 68
Figure 1.
Rev. D | Page 4 of 68
VREF
SW16
MEASOUT
RESET
GPO
16
16
16
OFFSET
OFFSET
16-BIT
DAC
ISENSE
VSENSE
KSENSE
TSENSE
DUTGND SENSE
DIAGNOSTIC A
DIAGNOSTIC B
×2 REG
×2 REG
16-BIT
DAC
SDO SCLK SDI
SYNC
BUSY
SERIAL SPI INTERFACE
×1/×0.2
MUX
AND
GAIN
×8
×8
S/W INH
R3
OFFSET
16-BIT
DAC
OFFSET
SW3
A
B
TMPALM
DIE TEMP
SENSOR AND
THERMAL
SHUTDOWN
R4
FIN
CLAMP
OFFSET
CONTROL
CLH
16-BIT
DAC
THERMAL SHUTDOWN
R2
16
16
16
CLH
CLEN/
LOAD CLALM
CPL
×1 REG
M REG
C REG
×1 REG
M REG
C REG
AGND
R1
CLH DAC
OFFSET DAC
CLH
16-BIT
×2 REG
×2 REG
×2 REG
16-BIT
DAC
DGND
CPOL
POWER-ON
RESET
×1
×1
RAMP REG
×1 REG
M REG
C REG
×1
×1 REG
M REG
C REG
×1 REG
M REG
C REG
DVCC
CPH
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
AVDD
CPOH/
CPO
HW_INH/LOAD
RCLK
REFGND
AGND
B
A
SW1
C
C
VREF
SW2
A B
6kΩ
VREF
16
AGND
VSENSE
ISENSE
16
OSD
DAC
×1
–
+
×10 +
OR ×20
–
DAC MID CODE
VOLTAGE TO
CENTER IRANGE
LOCAL FEEDBACK
EXTFORCE1
EXTFORCE2
SLEW RATE
CONTROL
gm
40µA/V
80µA/V
400µA/V
1000µA/V
RZ: 500Ω
TO 1.6MΩ
CC0 CC1 CC2 CC3
25kΩ
DGS
DAC
RP: 200Ω
TO 1MΩ
100kΩ
+
–
+
–
+
–
+
–
SW4
KELALM
ALARM BLOCK
KSENSE
DUTGND SENSE
GUARD
DUTGND SENSE
AND ALARM
INHIBIT
OPEN
SENSE
DETECT
8pF
RSENSE
SW7
25mA
SW17
5µA
25µA
250µA
2.5mA
AD5560
GUARD
AMP
SW15
SW14
SW13
100kΩ
20kΩ
2kΩ
200Ω
20Ω
SW5a
SW5b
HCAVDD1x HCAVSS1x HCAVSS2x HCAVDD2x
SW18
SW9
10kΩ
SW11
SW8
UP TO ±500mA
UP TO ±1.2A
MUX
SW6
DUTGND
GUARD/
SYS_DUTGND
SENSE
EXTMEASIL
EXTMEASIH2
EXTMEASIH1
SYS_SENSE
FORCE
SYS_FORCE
CF0 TO CF4
EXTFORCE2
EXTFORCE1
CF0 TO CF4
MASTER_OUT
SLAVE_IN
DUT
EXT
RSENSE2
EXT
RSENSE1
07779-001
AVSS
AD5560
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Data Sheet
AD5560
SPECIFICATIONS
HCAVDDx ≤ (AVSS + 33 V), HCAVDDx ≤ AVDD, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, DVCC =
2.3 V to 5.5 V, VREF = 5 V, gain (m), offset (c), and DAC offset registers are at default values; AGND = DGND = 0 V; TJ = 25°C to 90°C,
maximum specifications, unless otherwise noted. FSV is full-scale voltage, FSVR is full-scale voltage range, FSC is full-scale current, FSCR is
full-scale current range.
Table 1.
Parameter
FORCE VOLTAGE
Force Output Voltage 1
EXTFORCE1
Max
Unit
Test Conditions/Comments
AVSS + 2.25
HCAVSS1x + 1.75
HCAVSS1x + 1.25
AVDD − 2.25
HCAVSS1x − 1.75
HCAVDD1x − 1.25
V
V
V
EXTFORCE2
AVSS + 2.25
HCAVSS2x + 1.75
HCAVSS2x + 1.25
AVDD − 2.25
HCAVDD2x − 1.75
HCAVDD2x − 1.25
V
V
V
FORCE
AVSS + 2.75
AVDD − 2.75
V
Headroom/Footroom1
−2.75
+2.75
V
Headroom/Footroom1
−2.25
+2.25
V
Force Output Voltage Span
−22
+25
V
Allow ±500 mV for external RSENSE voltage drop.
Allow ±500 mV for external RSENSE voltage drop.
Allow ±500 mV for external RSENSE voltage drop.
Reduced headroom/footroom, clamps must be
enabled. 2
Allow ±500 mV for external RSENSE voltage drop
Allow ±500 mV for external RSENSE voltage drop
Allow ±500 mV for external RSENSE voltage drop.
Reduced headroom/footroom, clamps must be
enabled.2
Internal current ranges, includes ±500 mV for
internal RSENSE voltage drop
Internal current ranges to AVDD/AVSS, includes
±500 mV for internal RSENSE voltage drop.
External current ranges, EXTFORCE1/
EXTFORCE2 to HCAVDDx and HCAVSSx supplies;
includes ±500 mV for external RSENSE voltage drop.
May be a skewed range but within headroom
requirements and maximum power dissipation
for current range.
Forced Voltage Linearity Error
Forced Voltage Offset Error
−2
−50
+2
+50
mV
mV
+25
μV/°C
mV
ppm/°C
Forced Voltage Offset Error Tempco1
Forced Voltage Gain Error
Forced Voltage Gain Error Tempco1
Short-Circuit Current Limit3
EXTFORCE1
EXTFORCE2
FORCE
Min
Typ
27
−25
4
−3.5
−1.25
−75
±2.7
±0.9
±50
+3.5
+1.25
+75
A
A
mA
−20
±10
+20
mA
+64
+1
+0.4
70
mA
mV
mV
mV
140
mV
NSD1
MEASURE CURRENT RANGES
350
nV/√Hz
Internal Sense Resistors1
100
20
2
200
20
kΩ
kΩ
kΩ
Ω
Ω
Active CFx Buffer
DC Load Regulation1
Load Transient Response1
−64
−1
−0.4
Rev. D | Page 5 of 68
Uncalibrated, use c register to calibrate, measured at midscale.
Standard deviation = 23 μV/°C.
Uncalibrated, use m register to calibrate.
Standard deviation = 3 ppm/°C.
Clamps off.
Positive and negative dc short-circuit current.
Positive and negative dc short-circuit current.
±25 mA range, positive and negative dc shortcircuit current.
All other ranges, positive and negative dc
short-circuit current.
EXTFORCE1 range, ±1 A load current change.
EXTFORCE2 range, ±0.5 A load current change.
1.2 A load step into 100 μF DUT capacitance
(10 mΩ ESR), autocompensation mode.
1.2 A load step into 30 µF DUT capacitance
(10 mΩ ESR), autocompensation mode.
Measured at 1 kHz, at output of FORCE.
Sense resistors are trimmed to within 1%,
nominal ±500 mV VRSENSE.
±5 µA current range.
±25 µA current range.
±250 µA current range.
±2.5 mA current range.
±25 mA current range.
AD5560
Parameter
Measure Current Ranges
Data Sheet
Min
Typ
Max
Unit
±5
±25
±250
±2.5
±25
±500
µA
µA
µA
mA
mA
mA
±120
0
mA
MEASURE CURRENT
Differential Input Voltage Range1
Output Voltage Span1
Offset Error
Offset Error Tempco1
Offset Error
Offset Error Tempco1
Offset Error
Offset Error Tempco1
Offset Error
Offset Error Tempco1
Gain Error
Gain Error1
Gain Error Tempco1
MEASOUT Gain = 1
Linearity Error
MEASOUT Gain = 0.2
Linearity Error
Linearity Error
MEASOUT Gain = 0.2
Linearity Error
Linearity Error
MEASOUT Gain = 0.2
Linearity Error
Linearity Error
Common-Mode Error
−0.64
−0.7
25
−1
+1
−1
−1.5
+1.5
−1
−1.5
+1.5
3
−3
+3
8
−2
−1
+2
+1
20
V
V
V
% FSC
ppm of FSC/°C
% FSC
ppm of FSC/°C
% FSC
ppm of FSC/°C
% FSC
ppm of FSC/°C
% FSC
% FSC
ppm/°C
−0.01
+0.01
% FSCR
−0.06
−0.05
+0.06
+0.05
% FSCR
% FSCR
−0.125
−0.175
+0.125
+0.175
% FSCR
% FSCR
−0.0875
−0.1
−0.005
+0.0875
+0.1
+0.005
% FSCR
% FSCR
%FSVR/V
NSD1
MEASURE VOLTAGE
Measure Voltage Range1
Gain Error
Gain Error Tempco1
MEASOUT Gain = 1
Linearity Error
Offset Error
Offset Error Tempco1
NSD1
+0.64
+0.7
900
nV/√Hz
550
nV/√Hz
170
nV/√Hz
110
nV/√Hz
AVSS + 2.75
−0.1
AVDD − 2.75
+0.1
3
−2
−12
+2
+12
2
100
Rev. D | Page 6 of 68
V
% FS
ppm/°C
mV
mV
µV/°C
nV/√Hz
Test Conditions/Comments
Specified current ranges with VREF = 5 V and MI
gain = 20, or with VREF = 2.5 V and MI gain = 5.
Set using internal sense resistor.
Set using internal sense resistor.
Set using internal sense resistor.
Set using internal sense resistor.
Set using internal sense resistor.
EXTFORCE2, set by user with external sense
resistor, limited by headroom requirements
and maximum power dissipation.
EXTFORCE1, set by user with external sense
resistor, limited by headroom requirements
and maximum power dissipation.
All offset DAC/supply combinations settings, all
gain settings are measure current = (IDUT ×
RSENSE × MI gain), unless otherwise noted.
Maximum voltage across RSENSE, MI gain = 20.
Maximum voltage across RSENSE, MI gain = 10.
Measure current block alone (internal node).
At 0 A, MI gain = 20, MEASOUT gain = 1.
Standard deviation = 13 ppm/°C.
At 0 A, MI gain = 10, MEASOUT gain = 1.
Standard deviation = 13 ppm/°C.
At 0 A, MI gain = 20, MEASOUT gain = 0.2.
Standard deviation = 13 ppm/°C.
At 0 A, MI gain = 10, MEASOUT gain = 0.2.
Standard deviation = 15 ppm/°C.
Internal current ranges, all gain settings.
External current ranges, excluding RSENSE.
Standard deviation = 5 ppm/°C.
All supply conditions.
MI gain = 20 and 10.
Nominal supply (±16.5 V, 0x8000 offset DAC).
MI gain = 20.
MI gain = 10.
Low supply (−25 V/+8 V, 0xD4EB offset DAC).
MI gain = 20.
MI gain = 10.
High supply (−5 V/+28 V, 0xD1D offset DAC).
MI gain = 20.
MI gain = 10.
% of FS change at measure output per volts
change in DUT voltage.
MI gain = 20, MEASOUT gain = 1, measured at
MEASOUT @ 1 kHz, inputs grounded.
MI gain = 10, MEASOUT gain = 1, measured at
MEASOUT @ 1 kHz, inputs grounded.
MI gain = 20, MEASOUT gain = 0.2, measured at
MEASOUT @ 1 kHz, inputs grounded.
MI gain = 10, MEASOUT gain = 0.2, measured at
MEASOUT @ 1 kHz, inputs grounded.
MEASOUT Gain 1 and MEASOUT Gain 0.2.
All voltage ranges.
Standard deviation = 2 ppm/°C.
Standard deviation = 12 µV/°C.
@ 1 kHz, at MEASOUT, inputs grounded.
Data Sheet
Parameter
MEASOUT Gain = 0.2
Linearity Error
Offset Error
Offset Error Tempco1
AD5560
Min
Max
Unit
Test Conditions/Comments
−5.5
+5.5
mV
−9
+24
mV
−4
+13
mV
+20
10
mV
µV/°C
50
nV/√Hz
Referred to MV input, nominal supply (±16.5 V,
0x8000 offset DAC).
Referred to MV input, low supply (−25 V/+8 V,
0xD4EB offset DAC).
Referred to MV input, high supply (−5 V/+28 V,
0xD1D offset DAC).
Referred to MV output.
Standard deviation = 12 µV/°C, referred to MV
output.
@ 1 kHz, at MEASOUT, inputs grounded.
Includes SYS_SENSE, SYS_FORCE, EXTFORCE1,
EXTFORCE2, EXTMEASIH1, EXTMEASIH2,
EXTMEASIL, FORCE, and SENSE; measured with
PD = 1, SW-INH = 0 (power up and tristate).
−30
NSD1
COMBINED LEAKAGE
Leakage Current
Leakage Current Tempco1
SENSE INPUT
Leakage Current
−37.5
−30
±0.1
−2.5
Leakage Current Tempco1
Pin Capacitance1
EXTMEASIH1, EXTMEASIH2, EXTMEASIL
Leakage Current
−2.5
Leakage Current
Leakage Current
Path On Resistance
Pin Capacitance1
nA
nA
pF
mA
nA
pF
mA
−7.5
+7.5
nA
±0.06
nA/°C
Set with external sense resistor, limited by
headroom and power dissipation.
Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
pF
−500
+500
mA
−5
+5
nA
±0.05
nA/°C
±0.0
05
Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
nA/°C
+1200
AVSS
−2.5
Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
nA/°C
−1200
±0.0
2
100
Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
pF
+30
+10
±0.0
3
275
TJ = 25°C to 70°C.
nA/°C
±0.0
3
120
Leakage Current Tempco1
Pin Capacitance1
SYS_SENSE
Voltage Range
Leakage Current
Leakage Current Tempco1
+2.5
+2.5
−30
−10
Leakage Current Tempco1
Pin Capacitance1
EXTFORCE2 OUTPUTS
Maximum Current Drive1
nA
nA
nA/°C
±0.0
1
5
Leakage Current Tempco1
Pin Capacitance1
EXTFORCE1 OUTPUTS
Maximum Current Drive1
+37.5
+30
±0.4
±0.0
1
10
Leakage Current Tempco1
Pin Capacitance1
FORCE OUTPUT, FORCE
Maximum Current Drive1
Leakage Current
Typ
Set with external sense resistor, limited by
headroom and power dissipation.
Measured with PD = 1, SW-INH = 0 (power-up
and tristate).
pF
AVDD
+2.5
±0.025
V
nA
nA/°C
280
Ω
pF
5
Rev. D | Page 7 of 68
SYS_SENSE high-Z, force amplifier inhibited.
AVDD = 16.5 V, AVSS = −16.5 V.
AD5560
Parameter
SYS_FORCE
Voltage Range
Current Carrying Capability1
Leakage Current
Leakage Current Tempco1
Path On Resistance
Pin Capacitance1
SYS_DUTGND
Voltage Range
Path On Resistance
CURRENT CLAMP
Clamp Accuracy
Data Sheet
Min
Typ
AVSS
−25
−2.5
±0.00
5
Max
Unit
AVDD
+25
+2.5
±0.025
V
mA
nA
nA/°C
35
Ω
pF
AVDD
400
V
Ω
Programmed clamp
value + 10
Programmed clamp
value + 20
% of FS
5
AVSS
300
VCLL to VCLH1
Programmed
clamp value
Programmed
clamp value
2
VCLL to 0 A1
1
V
VCLH to 0 A1
1
V
% of FS
V
Test Conditions/Comments
SYS_FORCE high-Z, force amplifier inhibited.
AVDD = 16.5 V, AVSS = −16.5 V.
AVDD = 16.5 V, AVSS = −16.5 V.
MI gain = 20, with clamp separation of 2 V, and
1 V separation from AGND/0 A.
MI gain = 10, with clamp separation of 2 V, and
1 V separation from AGND/0 A.
10% of FSCR (MI gain = 20), 20% of FSCR (MI
gain = 10), restriction to prevent both clamps
activating together.
5% of FSCR (MI gain = 20), 10% of FSCR (MI gain
= 10), restriction to avoid impinging on FV
before programmed level.
5% of FSCR (MI gain 20), 10% of FSCR (MI gain =
10), restriction to avoid impinging on FV before
programmed level.
Measured from BUSY going low to visible
clamping.
Measured from BUSY going low to visible
recovery.
Time for CLALM to flag.
Clamp Activation Response Time1
20
100
μs
Clamp Recovery1
2
5
μs
Alarm Delay 1
50
μs
1
0.312
V/µs
V/µs
µF
%
Fastest slew rate, controlled via serial interface.
Slowest slew rate, controlled via serial interface.
µs
µs
µs
µs
µs
µs
µs
µs
3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc
load.
15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 400 kΩ, CDUT = 0.22 µF, full dc load.
1 V step, RDUT = 200 kΩ, CDUT = 0.22 µF, full dc load.
µs
µs
3 V step, CDUT = 2.2 µF, full dc load.
8 V step, CDUT = 2.2 µF, full dc load.
µs
µs
3 V step, CDUT = 10 µF, full dc load.
8 V step, CDUT = 10 µF, full dc load.
µs
µs
3 V step, CDUT = 20 µF, full dc load.
8 V step, CDUT = 20 µF, full dc load.
FORCE AMPLIFER
Slew Rate1
Maximum Stable Load Capacitance1
Voltage Overshoot/Undershoot1
SETTLING TIME (FORCE AMPLIFER)
FV (1200 mA EXTFORCE1 Range)1
FV (900 mA EXTFORCE1 Range)1
FV (500 mA EXTFORCE2 Range)1
FV (300 mA EXTFORCE2 Range)1
FV (25 mA Range)1, 3
FV (2.5 mA Range)1, 3
FV (250 µA Range)1, 3
FV (25 µA Range)1, 3
FV (5 µA Range)1, 3
FV (180 mA EXTFORCE1 Range)1
FV (100 mA EXTFORCE2 Range)1
FV (180 mA EXTFORCE1 Range)1
FV (100 mA EXTFORCE2 Range)1
FV (180 mA EXTFORCE1 Range)1
FV (100 mA EXTFORCE2 Range)1
160
5
Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
16
25
18
30
34
53
25
50
125
180
300
500
300
500
400
600
20
40
Compensation Register 1 = 0x8880 (1.7 μF to
2.9 μF, ESR 74 to 140 mΩ)
16
25
60
80
Compensation Register 1 = 0xB880 (7.9μF to
13 μF, ESR 74 to 140 mΩ)
55
70
210
260
Compensation Register 1 = 0xC880 (13 μF to
22 μF, ESR 74 to 140 mΩ)
65
80
310
370
Rev. D | Page 8 of 68
µs
Of programmed value (≥1 V).
To within 10 mV of programmed value.
Data Sheet
Parameter
SETTLING TIME (FV, MEASURE CURRENT)
MI (1200 mA EXTFORCE1 Range)1
MI (900 mA EXTFORCE1 Range)1
MI (500 mA EXTFORCE2 Range)1
AD5560
Min
Typ
Max
Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
30
40
32
42
69
95
Unit
Test Conditions/Comments
To within 10 mV of programmed value.
µs
µs
µs
3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load.
15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc
load.
0.5 V step using MEASOUT high-Z to within
10 mV of final value.
To within 10 mV of programmed value.
MI (300 mA EXTFORCE2 Range)1
MI (25 mA Range)1, 3
MI (2.5 mA Range)1, 3
70
650
6400
100
µs
µs
µs
MI Buffer Alone1
10
15
µs
SETTLING TIME (FV, MEASURE VOLTAGE)
MV (1200 mA Range)1
MV (900 mA Range)1
MV (500 mA Range)1
Compensation Register 1 = 0x4880 (229 nF to
380 nF, ESR 74 to 140 mΩ)
16
20
34
µs
µs
µs
MV (300 mA Range)1
MV (25 mA Range)1, 3
MV (2.5 mA Range)1, 3
25
125
300
180
500
µs
µs
µs
MV (250 µA Range)1, 3
MV Buffer Alone1
300
2
500
5
µs
µs
SETTLING TIME (FV) SAFE MODE
FV (1200 mA EXTFORCE1 Range1
FV (180 mA EXTFORCE1 Range)1
25
303
µs
µs
FV (100 mA EXTFORCE2 Range)1
660
µs
FV (25 mA Range)1, 3
SWITCHING TRANSIENTS
Range Change Transient1
760
1000
µs
0.5
% of FV
20
DAC SPECIFICATIONS
Force/Comparator/Offset DACs
Resolution
Voltage Output Span
Differential Nonlinearity1
Offset DAC
Gain Error
Clamp DAC
Resolution
Voltage Output Span
Differential Nonlinearity1
OSD DAC
Resolution
Voltage Output Span
Differential Nonlinearity1
DGS DAC
Resolution
Voltage Output Span
Differential Nonlinearity1
mV
3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load.
8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load.
15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc
load.
10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load.
20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load.
10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc
load.
10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load.
10 V step using MEASOUT high-Z to within
10 mV of final value.
To within 100 mV of programmed value.
3.7 V step, RDUT = 3.1 Ω, CDUT = 0.22 µF, full dc load.
3 V step, RDUT = 16 Ω, CDUT = 0. 22 µF to 20 μF, full
dc load.
8 V step, RDUT = 33.3 Ω, CDUT = 0. 22 µF to 20 μF,
full dc load.
20 V step, RDUT = 400 Ω, CDUT = 0.22 µF, full dc load.
CDUT = 10 μF, changing from higher to adjacent
lower ranges (except EXTFORCE1 to EXTFORCE2).
CDUT = 10 μF, changing from lower (5 µA) to
higher range (EXTFORCE1).
CDUT = 100 μF, changing between all ranges.
0.5
% of FV
−22
+25
Bits
V
−1
+1
LSB
−20
+20
mV
−22
+25
Bits
V
−1
+1
LSB
5
+2
Bits
V
LSB
VREF = 5 V.
5
+2
Bits
V
LSB
VREF = 5 V.
16
VREF = 5 V, minimum and maximum values set
by offset DAC.
Guaranteed monotonic.
CLL < CLH.
16
16
0.62
−2
16
0
−2
Rev. D | Page 9 of 68
VREF = 5 V, minimum and maximum values set
by offset DAC.
Guaranteed monotonic.
AD5560
Parameter
Comparator DAC Dynamic
Output Voltage Settling Time1
Slew Rate1
Digital-to-Analog Glitch Energy1
Glitch Impulse Peak Amplitude1
REFERENCE INPUT
VREF DC Input Impedance
VREF Input Current
VREF Range1
COMPARATOR
Error
VOLTAGE COMPARATOR
Propagation Delay1
Error1
CURRENT COMPARATOR
Propagation Delay1
Error1
MEASURE OUTPUT, MEASOUT
Measure Output Voltage Span1
Measure Output Voltage Span1
Measure Output Voltage Span1
Measure Output Voltage Span1
Measure Pin Output Impedance
Output Leakage Current
Output Capacitance1
Short-Circuit Current1
OPEN-SENSE DETECT/CLAMP/ALARM
Measurement Accuracy
Clamp Accuracy
Alarm Delay1
DUTGND
Voltage Range1
Pull-Up Current
Leakage Current
Trip Point Accuracy
Alarm Delay1
GUARD AMPLIFIER
Voltage Range1
Voltage Span1
Output Offset
Short-Circuit Current1
Load Capacitance1
Output Impedance
Alarm Delay1
DIE TEMPERATURE SENSOR
Accuracy1
Output Voltage at 25°C
Output Scale Factor1
Output Voltage Range1
Data Sheet
Min
Typ
3.5
1
10
40
1
−10
2
Max
Unit
Test Conditions/Comments
6
µs
V/µs
nV-s
mV
1 V change to 1 LSB.
MΩ
µA
V
Typically 100 MΩ.
Per input; typically ±30 nA.
+10
5
−7
Measured directly at comparator; does not
include measure block errors.
Uncalibrated.
With respect to the measured voltage.
+7
mV
+12
µs
mV
Uncalibrated.
−1.5
1
+1.5
µs
%
Of programmed current range, uncalibrated.
−12.81
+12.81
V
−6.405
0
+6.405
5.125
V
V
0
2.56
115
+100
V
Ω
nA
pF
mA
0.25
−12
0.25
−100
5
−10
+10
−200
600
50
−1
+50
−1
−30
+200
900
mV
mV
μs
+1
+70
V
μA
+1
μA
+10
mV
μs
AVDD − 2.25
25
+10
+20
100
V
V
mV
mA
nF
Ω
μs
50
AVSS + 2.25
−10
−20
100
200
−10
+10
1.54
4.7
1
2
Rev. D | Page 10 of 68
%
V
mV/°C
V
MEASOUT gain = 1, VREF = 5 V, offset DAC =
0x8000.
MEASOUT gain = 1, VREF = 2.5 V.
MEASOUT gain = 0.2, VREF = 5 V, offset DAC =
0x8000.
MEASOUT gain = 0.2, VREF = 2.5 V.
When HW_INH is low.
Pull-up for purpose of detecting open circuit on
DUTGND, can be disabled.
When pull-up disabled, DGS DAC = 0x3333 (1 V
with VREF = 5 V). If DUTGND voltage is far away
from one of comparator thresholds, more
leakage may be present.
If it moves 100 mV away from input level.
Relative to a temperature change.
Data Sheet
Parameter
SPI INTERFACE LOGIC
Logic Inputs
Input High Voltage, VIH
AD5560
Min
Typ
Max
1.7/2.0
Input Low Voltage, VIL
Unit
Test Conditions/Comments
V
(2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant
input levels.
(2.3 V to 2.7 V)/(2.7 V to 5.5 V) JEDEC-compliant
input levels.
0.7/0.8
V
+1
10
µA
pF
0.4
+1
10
V
V
μA
pF
0.4
10
V
pF
4
28
V
HCAVSS1x
HCAVDD2x
−25
4
−5
28
V
V
HCAVSS2x
AVDD
AVSS
DVCC
AIDD 4
AISS4
DICC
AIDD4
−25
8
−25
2.3
−5
28
−5
5.5
30
V
V
V
V
mA
mA
mA
mA
AISS4
−27
Input Current, IINH, IINL
Input Capacitance, CIN1
CMOS Logic Outputs
Output High Voltage, VOH
Output Low Voltage, VOL
Tristate Leakage Current
Output Capacitance1
Open-Drain Logic Outputs
Output Low Voltage, VOL
Output Capacitance1
POWER SUPPLIES
HCAVDD1x
HCAIDD1
HCAIDD1
HCAISS1
HCAISS1
HCAIDD2
HCAIDD2
HCAISS2
HCAISS2
POWER-DOWN CURRENTS
HCAIDD
HCAISS
HCAIDD
HCAISS
AIDD
AISS
DICC
Maximum Power Dissipation
EXTFORCE1
EXTFORCE2
Power-Up Overshoot1
−1
SDO, CPOL, CPOH, GPO, CPO.
DVCC − 0.4
−1
10
10
−30
3
27
mA
20
0.5
−20
−0.5
15
0.25
−15
−0.25
250
mA
mA
mA
mA
mA
mA
mA
mA
3
μA
μA
μA
μA
mA
mA
mA
10
5
5
W
W
%
−250
250
−250
5
−5
Rev. D | Page 11 of 68
IOL = 500 µA.
SDO, CPOL, CPOH, CPO.
SDO, CPOL, CPOH, CPO.
BUSY, TMPALM, CLALM, KELALM.
IOL = 500 µA, CL = 50 pF, RPULLUP = 1 kΩ.
|HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS,
HCAVDDx ≤ AVDD.
|HCAVDDx – HCAVSSx| < 33 V, HCAVSSx ≥ AVSS,
HCAVDDx ≤ AVDD.
|AVDD – AVSS| < 33 V.
All ranges.
All ranges.
Channel inhibited/tristate, HW_INH or
SW-INH low.
Channel inhibited/tristate, HW_INH or
SW-INH low.
HCAVDDx and HCAVSSx supply currents shown
are excluding load currents; however, for
power budget calculations, the supply currents
here are consumed by the load.
When enabled, excluding load conditions.
When disabled.
When enabled, excluding load condition.
When disabled.
When enabled, excluding load conditions.
When disabled.
When enabled, excluding load conditions.
When disabled.
Supply currents on power-up or during a
power-down condition.
Of programmed value.
AD5560
Parameter
Power Supply Sensitivity1
ΔForced Voltage/ΔAVDD
ΔForced Voltage/ΔAVSS
ΔForced Voltage/ΔHCAVDDx
ΔForced Voltage/ΔHCAVSSx
ΔMeasured Current/ΔAVDD
ΔMeasured Current/ΔAVSS
ΔMeasured Current/ΔHCAVDDx
ΔMeasured Current/ΔHCAVSSx
ΔMeasured Voltage/ΔAVDD
ΔMeasured Voltage/ΔAVSS
ΔMeasured Voltage/ΔHCAVDDx
ΔMeasured Voltage/ΔHCAVSSx
ΔForced Voltage/ΔDVCC
ΔMeasured Current/ΔDVCC
ΔMeasured Voltage/ΔDVCC
Data Sheet
Min
Typ
Max
−65
−65
−90
−90
−50
−43
−90
−90
−65
−65
−90
−90
−80
−80
−80
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Guaranteed by design and characterization, not subject to production test.
Programmable clamps must be enabled if taking advantage of reduced headroom/footroom.
3
Clamps disabled.
4
Not including internal pull-up current between AVDD/AVSS and HCAVDDx/HCAVSSx pins.
1
2
Rev. D | Page 12 of 68
Test Conditions/Comments
DC to 1 kHz.
−30 dB at 100 kHz.
−25 dB at 100 kHz.
−60 dB at 100 kHz.
−62 dB at 100 kHz.
−25 dB at 100 kHz.
−20 dB at 100 kHz.
−60 dB at 100 kHz.
−60 dB at 100 kHz.
−30 dB at 100 kHz.
−25 dB at 100 kHz.
−60 dB at 100 kHz.
−65 dB at 100 kHz.
−46 dB at 100 kHz.
−36 dB at 100 kHz.
−46 dB at 100 kHz.
Data Sheet
AD5560
TIMING CHARACTERISTICS
HCAVDDx ≤ AVSS + 33 V, HCAVSSx ≥ AVSS, AVDD ≥ 8 V, AVSS ≤ −5 V, |AVDD − AVSS| ≥ 16 V and ≤ 33 V, VREF = 5 V (TJ = 25°C to 90°C,
maximum specifications, unless otherwise noted).
Table 2. SPI Interface
Parameter 1, 2, 3
tUPDATE
t1
t2
t3
t4
t5
t6
t7
t8
t9 4
t10
t11
t12
t13
t14 5, 6
t15
LOAD TIMING
t16
t17
t18
t19
DVCC = 2.3 V
to 2.7 V
600
25
10
10
10
15
5
5
4.5
40
1.5
280
25
400
250
45
30
DVCC = 2.7 V
to 3.3 V
600
20
8
8
10
15
5
5
4.5
35
1.5
280
20
400
250
35
30
DVCC = 4.5 V
to 5.5 V
600
20
8
8
10
15
5
5
4.5
30
1.5
280
10
400
250
25
30
Unit
ns max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
μs max
ns max
ns min
µs max
ns min
ns max
ns max
Description
Channel update cycle time
SCLK cycle time; 60/40 duty cycle
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
Minimum SYNC high time
24th SCLK falling edge to SYNC rising edge
Data setup time
Data hold time
SYNC rising edge to BUSY falling edge
BUSY pulse width low for DAC x1 write
BUSY pulse width low for other register write
RESET pulse width low
RESET time indicated by BUSY low
Minimum SYNC high time in readback mode
SCLK rising edge to SDO valid
SYNC rising edge to SDO high-Z
20
150
0
150
150
20
150
0
150
150
20
150
0
150
150
ns min
ns min
ns min
ns min
ns min
LOAD pulse width low
BUSY rising edge to force output response time
BUSY rising edge to LOAD falling edge
LOAD rising edge to FORCE output response time
LOAD rising edge to current range response
1
Guaranteed by design and characterization, not production tested.
All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3
See Figure 4 and Figure 5.
4
This is measured with the load circuit shown in Figure 2.
5
This is measured with the load circuit shown in Figure 3.
6
Longer SCLK cycle time is required for correct operation of readback mode; consult timing diagrams and timing specifications.
2
TIMING DIAGRAMS
200µA
RLOAD
2.2kΩ
CLOAD
50pF
VOL
TO OUTPUT
PIN
CLOAD
50pF
07779-002
TO OUTPUT
PIN
IOL
VOH (MIN) – VOL (MAX)
2
200µA
Figure 2. Load Circuit for Open Drain
IOL
Figure 3. Load Circuit for CMOS
Rev. D | Page 13 of 68
07779-003
DVCC
AD5560
Data Sheet
t1
SCLK
1
24
2
t2
t3
t4
t6
SYNC
t5
t7
t8
DB0
DB23
SDI
t9
t10
BUSY
t16
LOAD1,3
FORCE
EXTFORCE1
EXTFORCE21
t17
t18
t16
LOAD2,3
FORCE
EXTFORCE1
EXTFORCE22,3
t19
t11
RESET
t12
1LOAD ACTIVE DURING BUSY.
2LOAD ACTIVE AFTER BUSY.
3LOAD FUNCTION IS AVAILABLE
07779-004
BUSY
VIA CLEN OR HW_INH AS DETERMINED BY DPS REGISTER 2.
Figure 4. SPI Write Timing
SCLK
48
24
t14
t13
SYNC
t15
DB23
D0B
DB23
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
DB0
NOP CONDITION
DB23
DB0
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. SPI Read Timing
Rev. D | Page 14 of 68
07779-005
SDI
Data Sheet
AD5560
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
AVDD to AVSS
AVDD to AGND
AVSS to AGND
HCAVDDx to HCAVSSx
HCAVDDx to AGND
HCAVSSx to AGND
HCAVDDx to AVSS
HCAVDDx to AVDD
HCAVSSx to AVSS
DVCC to DGND
AGND to DGND
REFGND to AGND
Digital Inputs to DGND
Analog Inputs to AGND
EXTFORCE1 and EXTFORCE2 to AGND1
Storage Temperature
Operating Junction Temperature
Reflow Profile
Junction Temperature
Power Dissipation
ESD
HBM
FICDM
1
Rating
34 V
−0.3 V to +34 V
−34 V to +0.3 V
34 V
−0.3 V to +34 V
−34 V to +0.3 V
−0.3 V to AVSS + 34 V
−0.3 V to AVDD + 0.3 V
+0.3 V to AVSS − 0.3 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to DVCC + 0.3 V
AVSS − 0.3 V to AVDD + 0.3 V
AVDD − 28 V
−65°C to +125°C
25°C to 90°C
J-STD 20 (JEDEC)
150°C max
10 W max (EXTFORCE1 stage)
5 W max (EXTFORCE2 stage)
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
1500 V
500 V
When an EXTFORCE1 or EXTFORCE2 stage is enabled and the supply differential |AVDD − AVSS| > 28 V, take care to ensure that these pins are not directly
shorted to AVSS voltage at any time because this can cause damage to the device.
Rev. D | Page 15 of 68
AD5560
Data Sheet
EXTFORCE1A
HCAV DD1A
HCAV SS2A
HCAV SS1A
EXTFORCE2A
HCAV DD2A
HCAV DD1B
EXTFORCE1B
HCAV SS2B
HCAV SS1B
EXTFORCE2B
HCAV DD2B
HCAV DD1C
EXTFORCE1C
HC_V SS1C
GPO
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
EXTMEASIH2
47
EXTMEASIH1
TMPALM 3
46
AVDD
CPOH/CPO 4
45
AVSS
CPOL 5
44
AGND
BUSY 6
43
GUARD/SYS_DUTGND
42
EXTMEASIL
41
SENSE
40
DUTGND
39
CF0
SDI 11
38
CF1
SYNC 12
37
CF2
RCLK 13
36
CF3
RESET 14
35
CF4
CLEN/LOAD 15
34
NC
HW_INH/LOAD 16
33
AVDD
CLALM 1
PIN 1
KELALM 2
SDO 7
AD5560
DVCC 8
TOP VIEW
(Not to Scale)
DGND 9
EXPOSED PAD ON TOP
SCLK 10
NOTES
1. NC = NO CONNECT.
2. EXPOSED PAD ON TOP OF PACKAGE. EXPOSED PAD IS INTERNALLY CONNECTED TO
MOST NEGATIVE POINT, AVSS.
07779-006
FORCE
SYS_FORCE
AVSS
SYS_SENSE
MASTER_OUT
SLAVE_IN
CC2
CC1
CC0
CC3
MEASOUT
AVDD
AVSS
AGND
VREF
REFGND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Figure 6. TQFP_EP Pin Configuration
Table 4. TQFP_EP Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CLALM
2
KELALM
3
TMPALM
4
5
6
7
CPOH/CPO
CPOL
BUSY
SDO
8
9
10
11
12
13
DVCC
DGND
SCLK
SDI
SYNC
RCLK
14
15
RESET
CLEN/LOAD
16
HW_INH/LOAD
17
REFGND
Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either
latched or unlatched.
Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
Comparator High Output (CPOH) or Window Comparator Output (CPO).
Comparator Low Output.
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
Digital Supply Voltage.
Digital Ground Reference Point.
Clock Input, Active Falling Edge.
Serial Data Input.
Frame Sync, Active Low.
Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied to
this input to drive the ramp circuitry. Tie RCLK low if it is unused.
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as
LOAD input (see the system control register, Address 0x1).
Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow
synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system
control register, Address 0x1).
Accurate Ground Reference for Applied Voltage Reference.
Rev. D | Page 16 of 68
Data Sheet
Pin No.
18
19, 44
20, 30, 45
Mnemonic
VREF
AGND
AVSS
21, 33, 46
AVDD
22
23
24
25
26
27
28
29
31
32
34
35
36
37
38
39
40
41
42
43
MEASOUT
CC3
CC0
CC1
CC2
SLAVE_IN
MASTER_OUT
SYS_SENSE
SYS_FORCE
FORCE
NC
CF4
CF3
CF2
CF1
CF0
DUTGND
SENSE
EXTMEASIL
GUARD/SYS_DUTGND
47
48
49, 55, 61
EXTMEASIH1
EXTMEASIH2
HCAVDD1A,
HCAVDD1B,
HCAVDD1C
EXTFORCE1A,
EXTFORCE1B,
EXTFORCE1C
HCAVSS1A,
HCAVSS1B,
HCAVSS1C
HCAVSS2A, HCAVSS2B
EXTFORCE2A,
EXTFORCE2B
HCAVDD2A,
HCAVDD2B
GPO
EP
AD5560
Description
Reference Input for DAC Channels, Input Range 2 V to 5 V.
Analog Ground.
Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.
Compensation Capacitor Input 3.
Compensation Capacitor Input 0.
Compensation Capacitor Input 1.
Compensation Capacitor Input 2.
Slave Input When Ganging Multiple DPS Devices.
Master Output When Ganging Multiple DPS Devices.
External Sense Signal Output.
External Force Signal Input.
Output Force Pin for Internal Current Ranges.
No Connect.
Feedforward Capacitor 4.
Feedforward Capacitor 3.
Feedforward Capacitor 2.
Feedforward Capacitor 1.
Feedforward Capacitor 0.
Device Under Test Ground.
Input Sense Line.
Low Side Measure Current Line for External High Current Ranges.
Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19
for addressing details.
50, 56, 62
51, 57, 63
52, 58
53, 59
54, 60
64
65
Input High Measure Line for External High Current Range 1.
Input High Measure Line for External High Current Range 2.
High Current Positive Analog Supply Voltage, for EXTFORCE1 Range.
Output Force. This pin is used for high Current Range 1, up to a maximum of ±1.2 A.
High Current Negative Analog Supply Voltage, for EXTFORCE1 Range.
High Current Negative Analog Supply Voltage, for EXTFORCE2 Range.
Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA.
High Current Positive Analog Supply Voltage, for EXTFORCE2 Range.
Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT.
The exposed pad is internally connected to AVSS.
Rev. D | Page 17 of 68
Data Sheet
9
8
7
6
5
4
3
2
1
A
EXTFORCE1A
EXTFORCE1A
EXTFORCE2A
EXTFORCE1B
EXTFORCE1B
EXTFORCE2B
EXTFORCE1C
EXTFORCE1C
GPO
B
HCAV DD1A
HCAV SS1A
HCAV DD2A
HCAV DD1B
HCAV SS1B
HCAV DD2B
HCAV DD1C
HCAV SS1C
CLALM
C
HCAVDD1A
HCAVSS1A
HCAVSS2A
HCAVDD1B
HCAVSS1B
HCAVSS2B
HCAVDD1C
HCAVSS1C
KELALM
D
AVDD
EXTMEASIH1
EXTMEASIH2
CPOL
CPOH/CPO
TMPALM
E
AVSS
AGND
GUARD/
SYS_DUTGND
DVCC
SDO
BUSY
F
DUTGND
EXTMEASIL
SENSE
SDI
SCLK
DGND
G
CF0
CF2
SYS_FORCE
SYS_SENSE
CC0
AVSS
RESET
RCLK
SYNC
H
CF1
CF3
SLAVE_IN
MASTER_OUT
CC1
MEASOUT
AVDD
VREF
CLEN/
LOAD
J
CF4
AVDD
FORCE
CC2
CC3
AVSS
AGND
REFGND
HW_INH/
LOAD
3 × 3 ARRAY IS VOID OF BALLS
07779-062
AD5560
Figure 7. Flip-Chip BGA Pin Configuration, Bottom Side (BGA Balls Are Visible)
Table 5. Flip-Chip BGA Pin Function Descriptions
Pin No.
A1
A2, A3
A4
A5, A6
A7
A8, A9
B1
Mnemonic
GPO
EXTFORCE1C
EXTFORCE2B
EXTFORCE1B
EXTFORCE2A
EXTFORCE1A
CLALM
B2, C2
B3, C3
B4
B5, C5
B6, C6
B7
B8, C8
B9, C9
C1
HCAVSS1C
HCAVDD1C
HCAVDD2B
HCAVSS1B
HCAVDD1B
HCAVDD2A
HCAVSS1A
HCAVDD1A
KELALM
C4
C7
HCAVSS2B
HCAVSS2A
Description
Extra Logic Output Bit. Ideal for external functions such as switching out a decoupling capacitor at DUT.
Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A.
Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA.
Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A.
Output Force. This pin is used for high Current Range 2, up to a maximum of ±500 mA.
Output Force. These pins are used for high Current Range 1, up to a maximum of ±1.2 A.
Clamp Alarm Output. Open-drain output, active low; this pin can be programmed to be either latched or
unlatched.
High Current Negative Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE2 Range.
High Current Negative Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE2 Range.
High Current Negative Analog Supply Voltage for EXTFORCE1 Range.
High Current Positive Analog Supply Voltage for EXTFORCE1 Range.
Kelvin Alarm Pin for SENSE and DUTGND, Open-Drain Active Low. This pin can be programmed to be either
latched or unlatched.
High Current Negative Analog Supply Voltage for EXTFORCE2 Range.
High Current Negative Analog Supply Voltage for EXTFORCE2 Range.
Rev. D | Page 18 of 68
Data Sheet
Pin No.
D1
Mnemonic
TMPALM
D2
D3
D7
D8
D9,H3, J8
CPOH/CPO
CPOL
EXTMEASIH2
EXTMEASIH1
AVDD
E1
E2
BUSY
SDO
E3
E7
DVCC
GUARD/SYS_DUTGND
E8
E9, G4, J4
AGND
AVSS
F1
F2
F3
F7
F8
F9
G1
G2
DGND
SCLK
SDI
SENSE
EXTMEASIL
DUTGND
SYNC
RCLK
G3
G5
G6
G7
G8
G9
H1
RESET
CC0
SYS_SENSE
SYS_FORCE
CF2
CF0
CLEN/LOAD
H2
H4
H5
H6
H7
H8
H9
J1
VREF
MEASOUT
CC1
MASTER_OUT
SLAVE_IN
CF3
CF1
HW_INH/LOAD
J2
J3
J5
J6
J7
J9
REFGND
AGND
CC3
CC2
FORCE
CF4
AD5560
Description
Temperature Alarm Flag. Open-drain output, active low; this pin can be programmed to be either latched
or unlatched.
Comparator High Output (CPOH) or Window Comparator Output (CPO).
Comparator Low Output.
Input High Measure Line for External High Current Range 2.
Input High Measure Line for External High Current Range 1.
Positive Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
Open-Drain Active Low Output. This pin indicates the status of the calibration engine for the DAC channels.
Serial Data Output. This pin is used for reading back DAC and DPS register information for diagnostic
purposes.
Digital Supply Voltage.
Guard Amplifier Output Pin or System Device Under Test Ground Pin. See the DPS Register 2 in Table 19
for addressing details.
Analog Ground.
Negative Analog Supply Voltage. These pins supply DACs and other high voltage circuitry, such as
measure blocks.
Digital Ground Reference Point.
Clock Input, Active Falling Edge.
Serial Data Input.
Input Sense Line.
Low Side Measure Current Line for External High Current Ranges.
Device Under Test Ground.
Frame Sync, Active Low.
Ramp Clock Logic Input. If the ramp function is used, a clock signal of 833 kHz maximum should be applied
to this input to drive the ramp circuitry. Tie RCLK low if it is unused.
Logic Input. This pin is used to reset all internal nodes on the device to their power-on reset value.
Compensation Capacitor Input 0.
External Sense Signal Output.
External Force Signal Input.
Feedforward Capacitor 2.
Feedforward Capacitor 0.
Clamp Enable. This input allows the user to enable or disable the clamp circuitry. This pin can be configured
as a LOAD function to allow synchronization of multiple devices. Either CLEN or HW_INH can be chosen as
LOAD input (see the system control register, Address 0x1).
Reference Input for DAC Channels, Input Range is 2 V to 5 V.
Multiplexed DUT voltage sense, DUT current sense, Kelvin sense, or temperature output; refer to AGND.
Compensation Capacitor Input 1.
Master Output When Ganging Multiple DPS Devices.
Slave Input When Ganging Multiple DPS Devices.
Feedforward Capacitor 3.
Feedforward Capacitor 1.
Hardware Inhibit Input to Disable Force Amplifier. This pin can be configured as a LOAD function to allow
synchronization of multiple devices. Either CLEN or HW_INH can be chosen as a LOAD input (see the system
control register, Address 0x1).
Accurate Ground Reference for Applied Voltage Reference.
Analog Ground.
Compensation Capacitor Input 3.
Compensation Capacitor Input 2.
Output Force Pin for Internal Current Ranges.
Feedforward Capacitor 4.
Rev. D | Page 19 of 68
AD5560
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1.2
12
1.0
10
8
MV LINEARITY (mV)
0.6
0.4
0.2
6
MEASOUT GAIN = 0.2
4
2
0
MEASOUT GAIN = 1
–2
0
10,000
20,000
30,000
40,000
50,000
60,000
CODE
–4
07779-026
–0.2
0
10,000
20,000
30,000
40,000
Figure 8. Force Voltage Linearity vs. Code, VREF = 5 V, No Load
60,000
Figure 11. Measure Voltage Linearity vs. Code (MEASOUT Gain 1,
MEASOUT Gain = 0.2, Negative Skew Supply)
2.0
0.0100
TJ = 25°C
AVDD = 16.25V
AVSS = –16.25V
VREF = 5V
1.5
HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D
LOW: AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB
NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000
VREF = 5V
0.0075
1.0
0.5
LINEARITY (%)
0.0050
MEASOUT GAIN = 0.2
0
–0.5
–1.0
0.0025
0
LOW SUPPLIES
–0.0025
–0.0050
–1.5
NOMINAL SUPPLIES
–0.0075
MEASOUT GAIN = 1
0
10,000
20,000
30,000
40,000
50,000
60,000
CODE
07779-027
HIGH SUPPLIES
–2.0
–0.0100
0
10,000
20,000
30,000
40,000
50,000
60,000
70,000
CODE
Figure 9. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1,
MEASOUT Gain = 0.2, Nominal Supplies)
Figure 12. Measure Current Linearity vs. Code (MEASOUT Gain = 1,
MI Gain = 20), TJ = 25°C
0.010
5
TJ = 25°C
AVDD = 28V
AVSS = –5V
VREF = 5V
OFFSET DAC = 0xD1D
4
HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D
LOW: AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB
NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000
VREF = 5V
0.005
3
MI LINEARITY (%)
MV LINEARITY (mV)
50,000
CODE
07779-034
0
07779-035
LINEARITY (mV)
0.8
MV LINEARITY ERROR (mV)
TJ = 25°C
AVDD = 8V
AVSS = –25V
VREF = 5V
OFFSET DAC = 0xD4EB
MEASOUT GAIN = 0.2
2
1
0
LOW SUPPLIES
0
–0.005
MEASOUT GAIN = 1
–1
NOMINAL SUPPLIES
10,000
20,000
30,000
CODE
40,000
50,000
60,000
–0.010
Figure 10. Measure Voltage Linearity vs. Code (MEASOUT Gain = 1,
MEASOUT Gain = 0.2, Positive Skew Supply)
0
10,000
20,000
30,000
40,000
50,000
60,000
70,000
CODE
Figure 13. Measure Current Linearity vs. Code (MEASOUT Gain = 1,
MI Gain = 10)
Rev. D | Page 20 of 68
07779-036
0
07779-033
HIGH SUPPLIES
–2
Data Sheet
0.0500
HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D
LOW: AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB
NOM: AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000
VREF = 5V
±25mA RANGE
0.0375
AVDD = +16.25V
AVSS = –16.25V
0.0375 V
REF = 5V
OFFSET DAC = 0x8000
0.0250 MI GAIN = 20
MEASOUT GAIN = 0.2
NOMINAL SUPPLIES
0.0125
LINEARITY (%)
LOW SUPPLIES
0
–0.0125
–0.0375
0
–0.0125
10,000
20,000
30,000
40,000
50,000
60,000
70,000
CODE
Figure 14. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2,
MI Gain = 20)
0.100
–0.0500
07779-037
0
0
10,000
20,000
30,000
40,000
50,000
60,000
CODE
Figure 17. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 0.2,
MI Gain = 20)
1.5
HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D
LOW : AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB
NOM : AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000
VREF = 5V ±25mA RANGE
0.075
2.5mA
25mA RANGE
–0.0375
HIGH SUPPLIES
–0.0500
TJ = 25°C
1.0
0.5
HIGH SUPPLIES
0.025
0
–0.025
NOMINAL SUPPLIES
–0.050
LOW SUPPLIES
0
EXTFORCE1A
EXTFORCE2B
FORCE
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
COMBINED LEAKAGE
–0.5
–1.0
–1.5
–2.0
–0.075
–2.5
0
10,000
20,000
30,000
40,000
50,000
60,000
–3.0
–10
07779-038
–0.100
70,000
CODE
5
0
5
10
STRESS VOLTAGE (V)
07779-030
LEAKAGE CURRENT (nA)
0.050
LINEARITY (%)
0.0125
–0.0250
–0.0250
Figure 18. Leakage Current vs. Stress Voltage (Force and Combined Leakage)
Figure 15. Measure Current Linearity vs. Code (MEASOUT Gain = 0.2,
MI Gain = 10)
7
0.0100
AVDD = +16.25V
AVSS = –16.25V
0.0075 V
REF = 5V
OFFSET DAC = 0x8000
0.0050 MI GAIN = 20
MEASOUT GAIN = 1
VSTRESS = 9V
6
LEAKAGE CURRENT (nA)
25µA RANGE
0.0025
0
–0.0025
2.5mA
–0.0050
–0.0075
–0.0100
0
10,000
20,000
5
4
3
2
1
25mA RANGE
30,000
40,000
50,000
60,000
CODE
Figure 16. Measure Current Linearity vs. IRANGE (MEASOUT Gain = 1,
MI Gain = 20)
0
25
07779-039
LINEARITY (%)
25µA RANGE
EXTFORCE1A
EXTFORCE2B
FORCE
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
COMBINED LEAKAGE
35
45
55
65
TEMPERATURE (°C)
75
85
95
07779-031
LINEARITY (%)
0.0250
07779-040
0.0500
AD5560
Figure 19. Leakage Current vs. Temperature (Force and Combined Leakage),
VSTRESS = 9 V
Rev. D | Page 21 of 68
AD5560
Data Sheet
0
0.15
EXTFORCE1A
EXTFORCE2B
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
0.05
0
TJ = 25°C
–0.02
–0.04
GAIN ERROR (%)
LEAKAGE CURRENT (nA)
0.10
–0.05
HIGH
NOMINAL
–0.06
LOW
–0.08
–0.10
–0.10
–0.15
5
10
STRESS VOLTAGE (V)
25
35
45
55
0
AV DD = ±16.25V
AV SS = –16.25V
VREF = 5V
OFFSET DAC = 0x8000
VSTRESS = 9V
1.6
0.6
EXTFORCE1A
EXTFORCE2B
EXTFORCE1B
EXTMEASIH1
SENSE
EXTFORCE1C
EXTMEASIH2
SYS_FORCE
EXTFORCE2A
EXTMEASIL
SYS_SENSE
1.2
–1.0
1.0
0.8
–1.5
0.6
0.4
0.1
–2.0
0.2
35
45
55
65
75
85
95
TEMPERATURE (°C)
–2.5
0
25
07779-061
0
25
–0.5
35
45
55
65
75
07779-043
0.2
1.4
POSITIVE GAIN ERROR (mV)
LEAKAGE CURRENT (nA)
0.7
0.3
85
1.8
0.8
0.4
75
Figure 23. MI Positive Gain Error vs. Temperature, MI Gain = 20,
MEASOUT Gain = 1
Figure 20. Leakage Current vs. Stress Voltage
0.5
65
TEMPERATURE (°C)
NEGATIVE GAIN ERROR (mV)
0
07779-032
5
07779-48
–0.12
–0.20
–10
85
TEMPERATURE (°C)
Figure 21. Leakage Current vs. Temperature, VSTRESS = 9 V
Figure 24. FV Gain Error vs. Temperature
0.10
23.0
HIGH 0.2
LOW
0.05
22.5
OFFSET ERROR (mV)
NOMINAL 0.2
HIGH
–0.05
–0.10
LOW 0.2
HIGH: AVDD = 28V, AVSS = –5V, OFFSET DAC = 0xD1D
LOW : AVDD = 5V, AVSS = –25V OFFSET DAC = 0xD4EB
NOM : AVDD/AVSS = ±16.25V, OFFSET DAC = 0x8000
VREF = 5V
LOW0.2/HIGH0.2/NOM0.2 MEAN FOR MEASOUT GAIN = 0.2
–0.15
–0.20
25
35
45
55
65
75
85
TEMPERATURE (°C)
22.0
21.5
21.0
20.5
Figure 22. MI Offset Error vs. Temperature, MI Gain = 20,
MEASOUT Gain = 1 and 0.2
20.0
25
35
45
55
65
75
TEMPERATURE (°C)
Figure 25. FV Offset Error vs. Temperature
Rev. D | Page 22 of 68
85
07779-041
0
07779-047
OFFSET ERROR (%)
NOMINAL
Data Sheet
AD5560
0
5
HIGH
4
–0.001
3
–0.003
LOW
NOMINAL
2
OFFSET ERROR (mV)
GAIN ERROR (%)
–0.002
–0.004
–0.005
1
0
NOMINAL
–1
–2
HIGH
–3
LOW
–0.006
35
45
55
65
75
85
TEMPERATURE (°C)
–5
25
07779-045
–0.007
25
35
45
55
65
75
07779-044
–4
85
TEMPERATURE (°C)
Figure 26. MV Gain Error vs. Temperature, MEASOUT Gain = 1
Figure 29. MV Offset Error vs. Temperature, MEASOUT Gain = 0.2
1.0
CH1 p-p
27mV
CH1 AREA
10.92µVs
0.9
HIGH
0.8
OFFSET ERROR (mV)
NOMINAL
0.7
LOW
0.6
FORCE
0.5
1
0.4
0.3
0.2
07779-015
SYNC
0.1
0
25
35
45
55
65
75
85
TEMPERATURE (°C)
07779-042
3
Figure 27. MV Offset Error vs. Temperature, MEASOUT Gain = 1
CH1 50mV
CH3 5V
B
W
B
W
M200µs
T 10.4%
A CH3
1.5V
Figure 30. Range Change 2.5 mA to 25 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load
0.030
CH1 p-p
16mV
CH1 AREA
–5.336µVs
NOMINAL
LOW
0.020
HIGH
FORCE
0.015
1
0.010
0.005
07779-016
SYNC
3
0
25
35
45
55
65
75
85
TEMPERATURE (°C)
Figure 28. MV Gain Error vs. Temperature, MEASOUT Gain = 0.2
07779-046
GAIN ERROR (%)
0.025
CH1 50mV
CH3 5V
B
W
B
W
M200µs
T 10.4%
A CH3
1.5V
Figure 31. Range Change 25 mA to 2.5 mA, Safe Mode, 2.5 mA ILOAD, 10 μF Load
Rev. D | Page 23 of 68
AD5560
Data Sheet
CH1 p-p
159mV
CH1 AREA
14.31µVs
CH1 p-p
84mV
TRIGGER
2
FORCE
FORCE
1
1
3
CH1 50mV
CH3 5V
M200µs
T 10.4%
B
W
B
W
A CH3
07779-020
07779-017
SYNC
1.5V
CH1 100mV
B
W
CH2 5V
M40µs
T 120.4µs
A CH2
1.6V
Figure 35. Autocompensation Mode 90% to 10% ILOAD Change,
EXTFORCE2 Range, 10 µF Load
Figure 32. Range Change 25 mA to EXTFORCE2, Safe Mode,
25 mA ILOAD, 10 μF Load
CH1 p-p
36mV
CH1 AREA
–9.738µVs
TRIGGER
CH1 p-p
86mV
2
FORCE
FORCE
1
07779-018
SYNC
3
CH1 50mV
CH3 5V
07779-021
1
M200µs
T 10.4%
A CH3
CH1 100mV
1.5V
B
W
CH2 5V
M40µs
T 120.4µs
A CH2
4V
Figure 36. Autocompensation Mode 10% to 90% ILOAD Change,
EXTFORCE2 Range, 10 µF Load
Figure 33. Range Change EXTFORCE2 to 25 mA, Safe Mode,
25 mA ILOAD, 10 µF Load
350
10µF LOAD
30µF LOAD
100µF LOAD
PEAK-TO-PEAK (mV)
300
CH1 p-p
172mV
TRIGGER
250
2
200
FORCE
1
150
100
07779-022
50
EXT RANGE 1
SAFE
MODE
AUTO
COMP
EXT RANGE 2
SAFE
MODE
AUTO
COMP
25mA RANGE
SAFE
MODE
AUTO
COMP
07779-019
0
Figure 34. Kick/Droop Response vs. IRANGE, Compensation, and CLOAD,,
10% to 90% to 10% ILOAD Change
Rev. D | Page 24 of 68
CH1 100mV
B
W
CH2 5V
M40µs
T 120.4µs
A CH2
1.6V
Figure 37. Safe Mode 80% to 10%, EXTFORCE2 Range, 10 µF Load
Data Sheet
AD5560
CH1 p-p
174mV
TRIGGER
FORCE
MEASOUT – MI
2
FORCE
1
2
07779-023
BUSY
B
CH1 100mV
CH2 5V
W
M40µs
T 120.4µs
A CH2
07779-055
1
TA = 25°C
AVDD = +16.25V
AVSS = –16.25V
VREF = 5V
OFFSET DAC = 0x8000
IRANGE /ILOAD = 25mA
0 TO 10V STEP
RLOAD = 40kΩ
CLOAD = 220nF
AUTOCOMP MODE 0x4480
MEASOUT GAIN 1, MI GAIN 20
4
3
4.6V
CH1 5V
CH3 5V
Figure 38. Safe Mode 10% to 90%, EXTFORCE2 Range, 10 µF Load
CH2 2V BW
CH4 10V
M20µs
T 1.4%
A CH3
2.9V
Figure 41. Transient Response FVMI Mode, 25 mA Range,
Autocompensation Mode
2.0
AVDD = +16.5V
AVSS = –16.5V
FORCE
1.9
MEASOUT VOLTAGE (V)
MEASOUT – MI
1.8
1
1.6
2
1.5
BUSY
35
45
55
65
75
4
3
07779-024
1.4
25
85
FORCED TEMPERATURE (°C)
TA = 25°C
AVDD = +16.25V
AVSS = –16.25V
VREF = 5V
OFFSET DAC = 0x8000
IRANGE /ILOAD = 250µA
0 TO 10V STEP
RLOAD = 40kΩ
CLOAD = 220nF
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
07779-056
1.7
CH1 5V
CH3 5V
CH2 2V BW
CH4 10V
M100µs
T 7.2%
A CH3
2.9V
Figure 42. Transient Response FVMI Mode, 25mA Range, Safe Mode
Figure 39. MEASOUT TSENSE Temperature Sensor vs. Temperature
(Multiple Devices)
FORCE
MEASOUT – MI
MEASOUT – MI
1
2
2
07779-054
BUSY
4
3
CH1 5V
CH3 5V
CH2 2V BW
CH4 10V
M400µs
T 10.2%
TA = 25°C
AVDD = +16.25V
AVSS = –16.25V
VREF = 5V
OFFSET DAC = 0x8000
IRANGE /ILOAD = EXTFORCE1/1.2A
0 TO 3.7V STEP
CLOAD = 10µF CERAMIC
AUTOCOMP MODE 0x9680
MEASOUT GAIN 1, MI GAIN 20
1
A CH3
BUSY
4
3
CH1 5V
CH3 5V
2.9V
CH2 1V BW
CH4 10V
M4µs
T 3%
A CH3
07779-057
FORCE
TA = 25°C
AVDD = +16.25V
AVSS = –16.25V
VREF = 5V
OFFSET DAC = 0x8000
IRANGE /ILOAD = 250µA
0 TO 10V STEP
RLOAD = 40kΩ
CLOAD = 220nF
AUTOCOMP MODE 0x4880
MEASOUT GAIN 1, MI GAIN 20
2.9V
Figure 43. Transient Response FVMI Mode, EXTFORCE1 Range,
Autocompensation Mode
Figure 40. Transient Response FVMI Mode, ±250 µA Range,
Autocompensation Mode
Rev. D | Page 25 of 68
AD5560
Data Sheet
1000
PART H1
PART H2
PART H3
900
800
700
NSD (nV/√Hz)
MEASOUT – MI
TA = 25°C
AVDD = +16.25V
AVSS = –16.25V
VREF = 5V
OFFSET DAC = 0x8000
IRANGE /ILOAD = EXTFORCE1/1.2A
0 TO 3.7V STEP
CLOAD = 10µF CERAMIC
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
200
FORCE
100
Figure 44. Transient Response FVMI Mode, EXTFORCE1 Range, Safe Mode
07779-025
GAIN = 11
GAIN = 10
FVMI
GAIN = 01
2.9V
FNMV
GAIN = 00
A CH3
FVMV
GAIN = 10
M20µs
T 4.6%
FVMN
GAIN = 00
CH2 1V BW
CH4 10V
0
GAIN = 10
BUSY
4
3
CH1 5V
CH3 5V
400
GAIN = 00
2
500
300
07779-058
1
600
Figure 47. NSD vs. Amplifier Stage and Gain Setting at 1 kHz
20
DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V
0
4
3
CH1 5V
CH3 5V
CH2 2V BW
CH4 10V
M10µs
T 9.8%
A CH3
–40
FOH
MV: GAIN 0
MV: GAIN 1
MV: GAIN 2
MV: GAIN 3
MI: GAIN 0
MI:GAIN 1
MI: GAIN 2
MI: GAIN 3
–60
–80
–100
10
2.9V
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 45. Transient Response FVMI Mode, EXTFORCE2 Range,
Autocompensation Mode
07779-049
2
ACPSRR (dB)
1
–20
07779-059
TA = 25°C
AVDD = +16.25V
MEASOUT – MI
AVSS = –16.25V
VREF = 5V
OFFSET DAC = 0x8000
IRANGE /ILOAD = EXTFORCE2/
300mA
FORCE
0 TO 10V STEP
CLOAD = 220nF
AUTOCOMP MODE 0x4880
MEASOUT GAIN 1, MI GAIN 20
BUSY
Figure 48. ACPSRR of AVDD vs. Frequency
0
FORCE
–20
MEASOUT – MI
BUSY
4
3
CH1 5V
CH3 5V
CH2 2V BW
CH4 10V
M100µs
T 9.8%
A CH3
ACPSRR (dB)
–60
FOH
MV: GAIN 0
MV: GAIN 1
MV: GAIN 2
MV: GAIN 3
MI: GAIN 0
MI:GAIN 1
MI: GAIN 2
MI: GAIN 3
–80
–100
–120
DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V
–140
10
2.9V
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 46. Transient Response FVMI Mode, EXTFORCE2 Range, Safe Mode
Rev. D | Page 26 of 68
Figure 49. ACPSRR of AVSS vs. Frequency
10M
07779-050
2
TA = 25°C
AVDD = +16.25V
AVSS = –16.25V
VREF = 5V
OFFSET DAC = 0x8000
IRANGE /ILOAD = EXTFORCE2/300mA
0 TO 10V STEP
CLOAD = 220nF
SAFE MODE
MEASOUT GAIN 1, MI GAIN 20
07779-060
1
–40
Data Sheet
AD5560
0
0
MI: GAIN 0
–20
–20
FOH
MI: GAIN 0
–40
ACPSRR (dB)
ACPSRR (dB)
–40
–60
MV: GAIN 0
–60
MV: GAIN 0
–80
–80
–100
–100
–120
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
–140
10
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 50. ACPSRR of DVCC vs. Frequency
Figure 52. ACPSRR of HCAVSSx vs. Frequency
1600
0
MI: GAIN 0
1400
–20
CABLE L =
CABLE L =
CABLE L =
CABLE L =
2µH, CLAMP AT 1.2A
1µH, CLAMP AT 1.2A
0.2µH, CLAMP AT 1.2A
0µH, CLAMP AT 1.2A
CABLE L =
CABLE L =
CABLE L =
CABLE L =
2µH, CLAMP AT 800mA
1µH, CLAMP AT 800mA
0.2µH, CLAMP AT 800mA
0µH, CLAMP AT 800mA
CABLE L =
CABLE L =
CABLE L =
CABLE L =
2µH, CLAMP AT 400mA
1µH, CLAMP AT 400mA
0.2µH, CLAMP AT 400mA
0µH, CLAMP AT 400mA
CABLE L =
CABLE L =
CABLE L =
CABLE L =
2µH, CLAMP AT 100mA
1µH, CLAMP AT 100mA
0.2µH, CLAMP AT 100mA
0µH, CLAMP AT 100mA
1200
ICLAMP VALUE (mA)
–40
MV: GAIN 0
–60
–80
–100
1000
800
600
400
FOH
–120
200
–140
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 51. ACPSRR of HCAVDDx vs. Frequency
0
0.001
0.01
0.1
1
RLOAD (Ω)
Figure 53. ICLAMP Value vs. RLOAD – Cal at 1Ohm
Rev. D | Page 27 of 68
10
07779-063
DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V
07779-052
ACPSRR (dB)
100
07779-053
10
07779-051
–120
FOH
DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V
DVCC = +5.25V, AVDD = +16.5V, AVSS = –16.5V
AD5560
Data Sheet
TERMINOLOGY
Offset Error
Offset error is a measure of the difference between the actual
voltage and the ideal voltage at midscale or at zero current
expressed in millivolts (mV) or percentage of full-scale range
(%FSR).
Gain Error
Gain error is the difference between full-scale error and zeroscale error. It is expressed in percentage of full-scale range
(%FSR).
Gain Error = Full-Scale Error − Zero-Scale Error
where:
Full-Scale Error is the difference between the actual voltage and
the ideal voltage at full scale.
Zero-Scale Error is the difference between the actual voltage and
the ideal voltage at zero scale.
Linearity Error
Linearity error, or endpoint linearity, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the full-scale range. It is measured after adjusting
for offset error and gain error and is expressed in millivolts (mV).
Common-Mode (CM) Error
CM error is the error at the output of the amplifier due to the
common-mode input voltage. It is expressed in percentage of
full-scale voltage range per volt (%FSVR/V).
Clamp Limit
Clamp limit is a measure of where the clamps begin to function
fully and limit the clamped voltage or current.
Slew Rate
The slew rate is the rate of change of the output voltage
expressed in volts per microsecond (V/μs).
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of ±1 LSB maximum ensures monotonicity.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a full-scale
input change.
Digital-to-Analog Glitch Energy
Digital-to-analog glitch energy is the amount of energy that is
injected into the analog output at the major code transition. It
is specified as the area of the glitch in nanovolts per second
(nV-sec). It is measured by toggling the DAC register data
between 0x7FFF and 0x8000.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the part’s ability to avoid coupling
noise and spurious signals that appear on the supply voltage
pin to the output of the switch. The dc voltage on the device
is modulated by a sine wave of 0.2 V p-p. The ratio of the
amplitude of the signal on the output to the amplitude of the
modulation is the ACPSRR. It is expressed in decibels (dB).
VSTRESS
VSTRESS is the stress voltage applied to each pin during leakage
testing.
Leakage Current
Leakage current is the current measured at an output pin when
the circuit connected to that pin is in high impedance state.
Rev. D | Page 28 of 68
Data Sheet
AD5560
THEORY OF OPERATION
The AD5560 is a single-channel, device power supply for use
in semiconductor automatic test equipment. All the DAC levels
required to operate the device are available on chip.
This block performs three functions related to the force and
sense lines.
•
This device contains programmable modes to force a pin voltage and measure the corresponding current (FVMI) covering
a wide current measure range of up to ±1.2 A. A voltage sense
amplifier allows measurement of the DUT voltage. Measured
current or voltage is available on the MEASOUT pin.
FORCE AMPLIFIER
The force amplifier is a unity gain amplifier forcing voltage
directly to the device under test (DUT). This high bandwidth
amplifier allows suppression of load transient induced glitching
on the amplifier output. Headroom and footroom requirements
for the amplifier are 2.25 V and an additional ±500 mV dropped
across the selected sense resistor with full-scale current flowing.
•
•
It clamps the sense line to within a programmable
threshold level (plus a VBE) of the force line, where the
programmable threshold is set by the OSD DAC voltage
level. This limits the maximum or minimum voltage that
can appear on the FORCE pin; it can be driven no higher
than [V(FIN DAC) + threshold + VBE] and no lower than
[V(FIN DAC) − threshold − VBE].
It triggers an alarm on KELALM if the force line goes more
than the threshold voltage away (OSD DAC level) from the
sense line.
It translates the V(force − sense) voltage to a level
relative to AGND so that it can be measured through
the MEASOUT pin.
An extra control bit (GPO) is available to switch out DUT
decoupling when making low current measurements.
The open-sense detect level is programmable over the range
0.62 V to 5 V (16-bit OSD DAC plus one diode drop). The 5 V
OSD DAC can be accessed through the serial interface (see the
DAC register addressing portion of Table 24). There is a 10 kΩ
resistor that can be connected between the FORCE and SENSE
pins by use of SW11. This 10 kΩ resistor is intended to
maintain a force/sense connection when a DUT is not in place.
It is not intended to be connected when measurements are
being made because this defeats the purpose of the OSD circuit
in identifying an open circuit between FORCE and SENSE. In
addition, the sense path has a 2.5 kΩ resistor in series; therefore, if the 10 kΩ switch is closed, errors may become apparent
when in high current ranges.
HW_INH Function
DEVICE UNDER TEST GROUND (DUTGND)
A hardware inhibit pin (HW_INH/LOAD) allows disabling of
the force amplifier, making the output high impedance. This
function is also available through the serial interface (see the
SW-INH bit in the DPS Register 1, Address 0x2).
DUTGND is the ground level of the DUT.
The amplifier is designed to drive high currents up to ±1.2 A
with the capability of ganging together outputs of multiple
AD5560 devices for currents in excess of ±1.2 A.
The force amplifier can be compensated to ensure stability
when driving DUT capacitances of up to 160 μF.
The device is capable of supplying transient currents in excess
of ±1.2 A when powering a DUT with a large decoupling
capacitor. A clamp enable pin (CLEN) allows disabling of the
clamp circuitry to allow the amplifier to quickly charge this
large capacitance.
This pin can also be configured as a LOAD function to allow
multiple devices to be synchronized. Note that either CLEN
or HW_INH can be chosen as a LOAD function.
DAC REFERENCE VOLTAGE (VREF)
One analog reference input, VREF, supplies all DAC levels with
the necessary reference voltage to generate the required dc levels.
OPEN-SENSE DETECT (OSD) ALARM AND CLAMP
The open-sense detect (OSD) circuitry protects the DUT from
overvoltage when the force and sense lines of the force
amplifier becoming disconnected from each other.
DUTGND Kelvin Sense
KELALM flags when the voltage at the DUTGND pin moves
too far away from the AGND line (>1 V default setting of the
DGS DAC). This alarm trigger is programmable via the serial
interface. The threshold for the alarm function is programmable using the DUTGND SENSE DAC (DGS DAC) (see
Table 24).
The DUTGND pin has a 50 μA pull-up resistor that allows
the alarm function to detect whether DUTGND is open. Setting
the disable DUTALM bit high (Register 0x6, Bit 10) disables the
50 μA pull-up resistor and also disables the alarm feature. The
alarm feature can also be set to latched or unlatched (Register 0x6,
Bit 11).
Kelvin Alarm (KELALM)
The open-drain active low Kelvin alarm pin flags the user when
an open occurs in either the sense or DUTGND line; it can be
programmed to be either latched or unlatched (Register 0x6,
Bit 13, Bit 11, Bit 7). The delay in the alarm flag is 50 μs.
Rev. D | Page 29 of 68
AD5560
Data Sheet
GPO
The GPO pin can be used as an extra control bit for external
switching functions, such as for switching out DUT decoupling
when making low current measurements.
The GPO pin is also internally connected to an array of thermal
diodes scattered across the AD5560. The diagnostic register
(Address 0x7) details the addressing and location of the diodes.
These can be used for diagnostic purposes to determine the
thermal gradients across the die and across a board containing
many AD5560 devices. When selected, the anode of these
diodes is connected to GPO and the cathode to AGND. The
AD5560 evaluation board uses the ON Semiconductor®
ADT7461 temperature sensor for the purpose of analyzing the
temperature at different points across the die.
COMPARATORS
The DUT measured value is monitored by two comparators
(CPOL, CPOH). These comparators give the advantage of
speed for go-no-go testing.
CPOL
1
0
1
The clamp register limits the CLL clamp to the range 0x0000 to
0x7FFF; any code in excess of this is seen as 0x7FFF. Similarly,
the CLH clamp registers are limited to the range 0x8000 to
0xFFFF (see Table 24).
Clamp Alarm Function (CLALM)
The CLALM open-drain output flags the user when a clamp
limit has been hit; it can be programmed to be either latched or
unlatched.
Pin 15 (CLEN) allows the user to disable the clamping function
when powering a device with large DUT capacitance, thus allowing
increased current drive to the device and, therefore, speeding
up the charging time of the load capacitance. CLEN is active high.
CPOH
0
1
This pin can also be configured as LOAD to allow multiple devices
to be synchronized. Note that either CLEN or HW_INH can be
chosen as a LOAD function.
1
To minimize the number of comparator output lines routed
back to the controller, it is possible to change the comparator
function to a window comparator that outputs on one single
pin, CPO. This pin is shared with CPOH and, when configured
through the serial interface, it provides information on whether
the measured DUT current or voltage is inside or outside the
window set by the CPL and CPH DAC levels (see Table 24).
SHORT-CIRCUIT PROTECTION
The AD5560 force amplifier stage has built-in short-circuit
protection per stage as noted in the Specifications section.
When the current clamps are disabled, the user must minimize
the duration of time that the device is left in a short-circuit
condition (for all current ranges).
GUARD AMPLIFIER
A guard amplifier allows the user to force the shield of the
coaxial cable to be driven to the same forced voltage at the
DUT, ensuring minimal voltage drops across the cable to
minimize errors from cable insulation leakage.
Table 7. Comparator Output Function in CPO Mode
Test Condition
(VDUT or IDUT) > CPL and < CPH
(VDUT or IDUT) < CPL or > CPH
The clamp levels should not be set to the same level; instead,
they should be set a minimum of 2 V apart (irrespective of the
MI gain setting). This equates to 10% of FSCR (MI gain = 20)
(20% of FSCR, MI gain of 10) apart. They should also be 1 V
away from the 0 A level.
Clamp Enable Function (CLEN/LOAD)
Table 6. Comparator Output Function
Test Condition
(VDUT or IDUT) > CPH
(VDUT or IDUT) < CPH
(VDUT or IDUT) > CPL
(VDUT or IDUT) < CPL
CPH > (VDUT or IDUT) > CPL
If a clamp level is exceeded, this is flagged via the latched opendrain CLALM pin, and the resulting alarm information can be
read back via the SPI interface.
CPO Output
1
0
CURRENT CLAMPS
High and low current clamps are included on chip. These protect
the DUT in the event of a short circuit. The CLH and CLL
levels are set by the 16-bit DAC levels. The clamp works to
limit the current supplied by the force amplifier to within the
set levels. The clamp circuitry compares the voltage across the
sense resistor (multiplied by an in-amp gain of 10 or 20) to
compare to the programmed clamp limit and activates the
clamp circuit if either the high level or low level is exceeded,
thus ensuring that the DUT current can never exceed the
programmed clamp limit + 10% of full-scale current.
The guard amplifier also has an alarm function that flags the
open-drain KELALM pin when the guard output is shorted.
The delay in the alarm flag is 200 μs.
The guard amplifier output (GUARD/SYS_DUTGND, Pin 43)
can also be configured to function as a SYS_DUTGND pin; to
do this, the guard amplifier must be tristated via software (see
DPS Register 2, Table 19).
COMPENSATION CAPACITORS
The force amplifier is capable of driving DUT capacitances up
to 160 μF. Four external compensation capacitor (CCx) inputs
are provided to ensure stability into the maximum load capacitance while ensuring that settling time is optimized. In addition,
five CFx capacitor inputs are provided to switch across the sense
Rev. D | Page 30 of 68
Data Sheet
AD5560
resistors to further optimize stability and settling time performance. The AD5560 has three compensation modes: safe mode,
autocompensation mode, and manual compensation mode, all
of which are described in more detail in the Force Amplifier
Stability section.
HIGH CURRENT RANGES
The range of suggested compensation capacitors allows
optimum performance for any capacitive load from 0 pF
to 160 μF using one of the modes previously listed.
Master and Slaves in Force Voltage (FV) Mode
Although there are four compensation input pins and five feedforward capacitor inputs pins, all capacitor inputs may be used
only if the user intends to drive large variations of DUT load
capacitances. If the DUT load capacitance is known and does
not change for all combinations of voltage ranges and test
conditions, then it is possible only one set of CCx and CFx
capacitors may be required.
Table 8. Suggested Compensation Capacitor Selection
Value
100 pF
100 pF
330 pF
3.3 nF
4.7 nF
22 nF
100 nF
470 nF
2.2 μF
All devices are placed in force voltage (FV) mode. One device
acts as the master device and the other devices act as slaves. By
connecting in this manner, any device can be configured as the
master. Here, the MASTER_OUT pin of the master device is
connected to the output of the force amplifier, and it feeds the
inputs of each slave force amplifier (via the SLAVE_IN pin ).
All devices are connected externally to the DUT. For current
to be shared equally, there must be good matching between
each of the paths to the DUT. Settings for DPS Register 2 are
master = 0x0000, slave = 0x0400. Clamps should be disabled in
the slave devices.
MASTER DPS
SLAVE IN
SW5-a
SW6
MASTER OUT
SW16
SW5-b
FIN
DAC
SW5-a
LOCAL
FEEDBACK
×20
OR
×W
RSENSE
SENSE
×1
SLAVE DPS 1
SLAVE IN
SW5-a
SW6
MASTER OUT
SW16
SW5-b
FIN
DAC
CURRENT RANGE SELECTION
SW5-a
LOCAL
FEEDBACK
×20
OR
×W
EXTFORCE2
EXTMEASIH1
EXTMEASIL
ISENSE
AMP
VSENSE
AMP
EXTFORCE1
SENSE
×1
SLAVE DPS 2
SLAVE IN
SW5-a
SW6
MASTER OUT
The measure current amplifier has two gain settings, 10 and
20. The two gain settings allow users to achieve the quoted/
specified current ranges with large or small voltage swings.
The gain of 20 setting is intended for use with a 5 V reference,
and the gain of 10 setting is for use with a 2.5 V reference. Both
combinations ensure the specified current ranges. Other
VREF/gain setting combinations should only be used to
achieve smaller current ranges. Attempting to achieve greater
current ranges than the specified ranges is outside the intended
operation of the AD5560. The maximum guaranteed voltage
across RSENSE is ±0.64 V (gain of 20) or ±0.7 V (gain of 10).
SW16
SW5-b
FIN
DAC
SW5-a
LOCAL
FEEDBACK
×20
OR
×W
EXTFORCE1
EXTFORCE2
EXTMEASIH1
EXTMEASIL
ISENSE
AMP
×1
SENSE
VSENSE
AMP
DUT
DUTGND
Figure 54. Simplified Block Diagram of High Current Ganging Mode
Rev. D | Page 31 of 68
07779-007
Integrated thin film resistors minimize external components
and allow easy selection of current ranges from ±5 µA to
±25 mA. Using external current sense resistors, two higher
current ranges are possible: EXTFORCE1 can drive currents
up to ±1.2 A, while EXTFORCE2 is designed to drive currents
up to ±500 mA. The voltage drop across the selected sense resistor
is ±500 mV when full-scale current is flowing through it.
EXTMEASIH1
RSENSE
The voltage range for the CCx and CFx pins is the same as the
voltage range expected on FORCE; therefore, choice of capacitors should take this into account. CFx capacitors can have
10% tolerance; this extra variation directly affects settling
times, especially when measuring current in the low current
ranges. Selection of CCx should be at ≤5% tolerance.
EXTFORCE2
EXTMEASIL
ISENSE
AMP
VSENSE
AMP
EXTFORCE1
RSENSE
Capacitor
CC0
CC1
CC2
CC3
CF0
CF1
CF2
CF3
CF4
For currents in excess of 1200 mA, a gang mode is available
whereby multiple devices are ganged together for higher currents.
There are two methods of ganging channels together; these are
discussed in the following two sections.
AD5560
Data Sheet
Master in FV Mode, Slaves in Force Current (FI) Mode
The master device is placed into FV mode, and all slave devices
into force current (FI) mode. The measured current of the
master device (MASTER_OUT) is applied to the input of all
slave devices (SLAVE_IN), and the slaves act as followers. All
channels work to share the current equally among all devices
in the gang. Because the slaves force current, matching the
DUT paths is not so critical. Settings for DPS Register 2 are
master = 0x0200, slave = 0x0600. Clamps should be disabled in
the slave devices.
MASTER DPS
SLAVE IN
SW5-a
FIN
DAC
SW5-b
SW5-a
For example, ganging five 25 V/25 mA devices using the 25 mA
range achieves a 25 V/625 mA range, whereas five 15 V/200 mA
devices using the EXTFORCE2 path can achieve a 15 V/1 A
range. Similarly, ganging four 3.5 V/1.2 A devices using the
EXTFORCE1 path results in a 3.5 V/4.8 A DPS.
IDEAL SEQUENCE FOR GANG MODE
Use the following steps to bring devices into and out of gang mode:
SW6
MASTER OUT
SW16
The EXTFORCE1, EXTFORCE2, or ±25 mA ranges can be
used for the gang mode. Therefore, it is possible to gang devices
to get a high voltage/high current combination, or a low
voltage/high current combination.
1.
EXTFORCE1
2.
EXTFORCE2
SENSE
MEASOUT
BUFFER
AND GAIN
3.
4.
EXTMEASIH1
×20
RSENSE
EXTMEASIL
ISENSE
AMP
SLAVE DPS 1
5.
SLAVE IN
SW5-a
To remove devices from the gang, the master device should
be programmed to force 0 V out again. The procedure for
removing devices should be the reverse of Step 1 through Step 5.
SW6
MASTER OUT
SW16
FIN
DAC
SW5-b
SW5-a
EXTFORCE1
Note that this may not always be possible in practice; therefore,
it is also possible to gang and ungang while driving a load. Just
ensure that the slave devices are in high-Z mode while configuring them into the required range and gang setting.
EXTFORCE2
SENSE
EXTMEASIH1
×20
RSENSE
MEASOUT
BUFFER
AND GAIN
EXTMEASIL
ISENSE
AMP
SLAVE DPS 2
Gang mode extends only to the ±25 mA range and the two high
current ranges, EXTFORCE1 and EXTFORCE2. Therefore, where
an accurate measurement is required at a low current, the user
should remove slaves from the gang to move to the appropriate
lower current range to make the measurement. Similarly, slaves
can be brought back into the gang if needed.
SLAVE IN
SW5-a
SW6
MASTER OUT
SW16
FIN
DAC
SW5-b
SW5-a
EXTFORCE1
COMPENSATION FOR GANG MODE
EXTFORCE2
SENSE
×20
ISENSE
AMP
EXTMEASIL
When ganging, the slave devices should be set to the fastest
response.
DUT
DUTGND
Figure 55. Simplified Block Diagram of Gang Mode,
Using an FV/FI Combination
07779-008
EXTMEASIH1
RSENSE
MEASOUT
BUFFER
AND GAIN
Choose the master device and force 0 V output, corresponding to zero current.
Select slave DPS 1 and place it in slave mode (keep slaves in
high-Z mode via SW-INH or HW_INH until ready to gang).
Select to gang in either current or voltage mode.
Repeat Step 2 and Step 3 one at a time through the chain of
slaves.
Load the required voltage to the master device. The other
devices copy either voltage or current as programmed.
When slaves are in FI mode, the AD5560 force amplifier overrides other compensation settings to enforce CFx = 0, RZ = 0,
and gmx ≤ 1. This is done internally to the force amplifier;
therefore, readback will not show that the signals inside the
force amplifier actually change.
SYSTEM FORCE/SENSE SWITCHES
System force/sense switches allow easy connection of a central
or system parametric measurement unit (PMU) for calibration
or additional measurement purposes.
The system device under test ground (SYS_DUTGND) switch
is shared with the GUARD/SYS_DUTGND pin (Pin 43). See
the DPS Register 2 in Table 19 for addressing details.
Rev. D | Page 32 of 68
Data Sheet
AD5560
DIE TEMPERATURE SENSOR AND THERMAL
SHUTDOWN
These diodes can be muxed out onto the GPO pin. The
diagnostic register (Address 0x7) details the addressing and
location of the diodes. These can be used for diagnostic
purposes to determine the thermal gradients across the die
and across a board containing many AD5560 devices. When
selected, the anode of each diode is connected to GPO and
the cathode to AGND. The AD5560 evaluation board uses
the ON Semiconductor ADT7461 temperature sensor for
the purpose of analyzing the temperature at different
points across the die.
There are three types of temperature sensors in the AD5560.
•
The first is a temperature sensor available on the MEASOUT
pin and expressed in voltage terms. Nominally at 25°C, this
sensor reads 1.54 V. It has a temperature coefficient of
4.7 mV/°C. This sensor is active during power-down mode.
Die Temp = (VMEASOUT(TSENSE) − 1.54)/0.0047 + 25°C
Based on typical temperature sensor output voltage at
25°C and output scaling factor.
•
The second type of temperature sensor is related to the
thermal shutdown feature in the device. Here, there are
sensors located in the middle of the enabled power stage,
which are used to trip the thermal shutdown. The thermal
shutdown feature senses only the power stages, and the power
stage that it senses is determined by the active stage.
If ranges of <25 mA are selected, the EXTFORCE1 sensor is
monitored. The EXTFORCE1 power stage itself is made
up of three identical stages, but the thermal shutdown is
activated by only one stage (EXTFORCE1B). Similarly, the
EXTFORCE2 stage is made up of two identical output
stages, but the thermal shutdown can be activated by only
one stage (EXTFORCE2A).
The thermal shutdown circuit monitors these sensors and,
in the event of the die temperature exceeding the programmable threshold temperature (100°C, 110°C, 120°C, 130°C
(default)), the device protects itself by inhibiting the force
amplifier stage, clearing SW-INH in DPS Register 1 and
flagging the overtemperature event via the open-drain
TMPALM pin, which can be programmed to be either
latched or unlatched. These temperature sensors can be
read via the MEASOUT pin by selecting them in the
diagnostic register (Table 23, VPTAT low and VPTAT
high). They are expressed in voltage and to scale to
temperature. They must be referred to the VTSD reference
voltage levels (see Table 23) also available on MEASOUT.
This set of sensors is not active in power-down mode.
Die Temp_y = {(VPTAT_x − VTSD_low)/[(VTSD_high −
VTSD_low)/(Temp_high – Temp_low)]} + Temp_low
where:
x, y are (high, NPN) and (low, PNP).
Temp_low = −273°C.
Temp_high = +130°C.
•
The third set of temperature sensors is an array of thermal
diodes scattered across the die. These diodes allow the user
to evaluate the temperature of different parts of the die and
are of great use to determine the temperature gradients
across the die and the temperature of the accurate portions
of the die when the device is dissipating high power. For
further details on the thermal array and locations, see the
diagnostic register section in Table 23.
Note that, when a thermal shutdown occurs, as the force
amplifier is inhibited or tristated, user intervention is required
to reactivate the device. It is necessary to clear the temperature
alarm flag by issuing a read command of Register Address 0x44
(alarm status and clear alarm status register, Table 25), and
then issuing a new write to the DPS Register 1 (SW-INH = 1)
to reenable the force amplifier.
See also the Thermal Considerations section.
MEASURE OUTPUT (MEASOUT)
The measured DUT voltage, current (voltage representation
of DUT current), KSENSE, or die temperature is available on
MEASOUT with respect to AGND. The default MEASOUT
range is the forced voltage range for voltage measure and
current measure (nominally ±12.81 V, depending on reference
voltage and offset DAC) and includes overrange to allow for
system error correction.
The serial interface allows the user to select another MEASOUT
range of (1.025 × VREF) to AGND; this range is suitable for use
with an ADC with a smaller input range.
To allow for system error correction, there is additional gain
for the force function. If this overrange is used as intended,
the output range on MEASOUT scales accordingly.
The MEASOUT line can be tristated via the serial interface.
When using low supply voltages, ensure that there is sufficient
headroom and footroom for the required force voltage range.
VMID VOLTAGE
The midcode voltage (VMID) is used in the measure current
amplifier block to center the current ranges at about 0 A.
This is required to ensure that the quoted current ranges can
be achieved when using offset DAC settings other than the
default. VMID corresponds to 0x8000 or the DAC midcode
value, that is, the middle of the voltage range set by the offset
DAC setting (see Table 15 and Figure 56).
VMID = 5.125 × VREF × (32,768/216) − (5.125 × VREF ×
(OFFSET_DAC_CODE/216))
or
Rev. D | Page 33 of 68
VMID = 5.125 × VREF × ((32,768 − Offset DAC)/216)
AD5560
Data Sheet
VMIN is another inportant voltage level that is used in other
parts of the circuit. When using a MEASOUT gain of 0.2, the
VMIN level is used to scale the voltage range; therefore, when
choosing supply rails, it is very important to ensure that there
is sufficient footroom so that the VMIN level is not impinged
on (the high voltage DAC amplifiers used here require
approximately 2 V footroom to AVSS). See the Choosing
AVDD/AVSS Power Supply Rails section for more information.
VMIN = −5.125 × VREF × (OFFSET_DAC_CODE/216)
Table 9. MEASOUT Output Ranges
Output Voltage Range 1
MEASOUT Function
GAIN1 = 0, MEASOUT Gain = 1
Measure Voltage (MV)
MI gain = 20
Measure GAIN0 = 0
Current
MI gain = 10
GAIN0 = 1
(MI)
1
Transfer Function
±VDUT
(IDUT × RSENSE × 20) + VMID
(IDUT × RSENSE × 10) + VMID
Offset DAC =
0x0
0 V to 25.62 V
0 V to 25.62 V
0 V to 12.81 V
(VREF = 2.5 V)
Offset DAC = 0x8000
±12.81 V
±12.81 V
±6.4 V
(VREF = 2.5 V)
Offset DAC = 0xE000
−22.42 V to +3.2 V
−22.42 V to +3.2 V
−11.2 V to +1.6 V
(VREF = 2.5 V)
VREF = 5 V, unless otherwise noted.
Table 10.
MEASOUT Function
GAIN1 = 1, MEASOUT Gain = 0.2
Measure Voltage (MV)
Measure
Current
(MI)
1
2
Transfer Function
MV = 0.2 × (VDUT − VMIN)
GAIN0 = 0
MI gain = 20
(IDUT × RSENSE × 20 × 0.2) + 0.5125 × VREF
GAIN0 = 1
MI gain = 10
(IDUT × RSENSE × 10 × 0.2) + 0.5125 × VREF
Output Voltage Range 1, 2
0 V to 5.12 V (±2.56 V centered around 2.56 V)
(includes overrange)
0 V to 5.12 V (±2.56 V centered around 2.56 V)
(includes overrange)
1.28 V to 3.84 V (±1.28 V, centered around 2.56 V)
0 V to 2.56 V (±1.28 V, centered around 1.28 V)
(VREF = 2.5 V)
VREF = 5 V, unless otherwise noted.
The offset DAC setting has no effect on the output voltage range.
Table 11. Possible ADCs and ADC Drivers for Use with AD5560 1
Part
No.
AD7685
Resolution
16
Sample
Rate
250 kSPS
Channels
1
AIN Range 2
0 to VREF
Interface
Serial, SPI
ADC Driver
ADA4841-x
Multiplexer 3
ADG704, ADG708
AD7686
16
500 kSPS
1
0 to VREF
Serial, SPI
ADA4841-x
ADG704, ADG708
AD7693
16
500 kSPS
1
−VREF to +VREF
Serial, SPI
ADA4841-x,
ADA4941-1
AD7610
16
250 kSPS
1
Serial, parallel
AD8021
AD7655
16
1 MSPS
4
Bipolar 10 V, bipolar
5 V, unipolar 10 V,
unipolar 5 V
0 V to 5 V
ADG1404,
ADG1408,
ADG1204
AD1404, ADG1408,
ADG1204
Serial, SPI
ADA4841-x/
AD8021
1
2
3
Package
MSOP,
LFCSP
MSOP,
LFCSP
MSOP,
LFCSP
LFCSP,
LQFP
LQFP,
LFCSP
Subset of the possible ADCs, ADC drivers, and multiplexers suitable for use with the AD5560. Visit http://www.analog.com for more options.
Do not allow the MEASOUT output range to exceed the AIN range of the ADC.
For the purposes of sharing ADCs among multiple DPS channels, note that the multiplexer is not absolutely necessary because the AD5560 MEASOUT path has a
tristate mode.
Rev. D | Page 34 of 68
Data Sheet
AD5560
VREF
VMID = (VTOP – VBOT)/2
VMID
VTOP
R
8.25R
2R
HV DAC AMP
LOW VOLTAGE
OFFSET DAC
DAC
att
VOS = (1 + 2/8.25) × (OFFSET DAC VOLTAGE)
8.25R
2R
2R
8.25R
R
VBOT
VMIN
5R
att
REFGND
MEASOUT
OSD DAC IN
R
INTERNAL
MEASI LOW
INTERNAL
MEASI HIGH
10R
tri
MI_x10
MEASURE
CURRENT
ISENSE AMP
5R
1kΩ
MI_x20
mi
mi_gain
R
10R
2R
att
2R
5R
MEASURE
VOLTAGE
1kΩ
mv att
att
5R
5R
5R
5R
5R
DUTGND
VSENSE AMP
SENSE
NOTES
1. att: ATTENUATION FOR EXTERNAL MEASOUT × 0.20 FOR OUTPUT VOLTAGE RANGE 0V TO 5.125V (WITH OVERRANGE) (VREF = 5V).
tri: TRISTATE MODE
mv: MEASURE VOLTAGE
mi: MEASURE CURRENT
mi_gain: MEASURE I GAIN SELECTION
Figure 56. MI, MV, and MEASOUT Block Showing Gain Settings and Offset DAC Influence
Rev. D | Page 35 of 68
07779-009
-
AD5560
Data Sheet
FORCE AMPLIFIER STABILITY
Table 12. External Variables
There are three modes for configuring the force amplifier: safe
mode, autocompensation mode, and manual compensation mode.
Manual compensation mode has highest priority, followed by safe
mode, then autocompensation mode.
Name
CR
RC
CD
RD
IR
Safe Mode
Selected through Compensation Register 1 (see Table 20), this
mode guarantees stability of the force amplifier under all
conditions. Where the load is unknown, this mode is useful but
results in a slow response. This is the power-on default of the
AD5560.
Description
DUT capacitance with contributing
ESR
ESR in series with CR
DUT capacitance with negligible ESR
Loading resistance at the DUT
Current range
Min
10 nF
Max
160 μF
1 mΩ
100 pF
~2 Ω
±5 μA
10 Ω
10 nF
Infinity
±1.2 A
Table 13. Internal Variables
Name
RZ
Autocompensation Mode
RP
Using this mode, the user inputs the CR and ESR values, and
the AD5560 decides the most appropriate compensation
scheme for these load conditions. The compensation chosen
is for an optimum tradeoff between ac response and stability.
CC0:CC3
CF0:CF4
gmx
Manual Compensation Mode
This mode allows access to all of the internal programmable
parameters to configure poles/zeros, which affect the dynamic
performance of the loop. These variables are outlined in
Table 12 and Table 13.
Description
Resistor in series with CC0, which
contributes a zero.
Resistor to 8 pF to contribute an
additional pole
Capacitors to ensure
unconditional stability
Capacitors to optimize ac
performance into different CR, CD
Transconductance of force
amplifier input stage
Min
500 Ω
Max
1.6 MΩ
200 Ω
1 MΩ
100 pF
100 nF
4.7 nF
10 μF
40 μA/V
900 μA/V
Figure 57 shows more details of the force amplifier block.
AD5560
CF0
FORCE VOLTAGE LOOP
RP:
200Ω TO 1MΩ
4.7nF
CF1
22nF
CF2
100nF
CF3
470nF
CF4
2.2µF
EXTFORCE2
RSENSE 2
EXTFORCE1
RSENSE 1
20Ω
200Ω
2kΩ
8pF
FORCE
20kΩ
100kΩ
CC0
6kΩ
CC1
100pF
CC2
100pF
25kΩ
100kΩ
FORCE
DAC
+
gm
AGND
VSENSE
–
+
–
×1
+
–
CC3
330pF
SENSE
+
–
CD
RC
CR
RD
DUTGND
3.3nF
07779-010
RZ:
500Ω TO
1.6MΩ
Figure 57. Block Diagram of a Force Amplifier Loop
Rev. D | Page 36 of 68
Data Sheet
AD5560
POLES AND ZEROS IN A TYPICAL SYSTEM
Typical closed loop systems have one dominant pole in the
feedback path, providing −20 dB/decade gain roll off and 90°
of phase shift so that the gain decreases to 0 dB where there
is a conservative 90° of phase margin.
The AD5560 has compensation options to help cope with the
various load conditions that a DPS is presented with.
MINIMIZING THE NUMBER OF EXTERNAL
COMPENSATION COMPONENTS
Note that, depending on the range of load conditions, not all
external capacitors are required.
CFx Pins
There are five external CFx pins. All five pins are used
in the autocompensation mode to choose a suitable capacitor,
depending on the load being driven. To reduce component
count, it is possible to connect just one capacitor, for instance,
CF2 to the CF2, CF1, and CF0 pins. Therefore, when any of the
smallest three external capacitors are selected, the same physical
capacitor is used because it is connected to all three pins. A
disadvantage here is that the larger CF2 capacitor should be
bigger than optimal and may increase settling time of the
whole circuit (particularly the measure current).
CCx Pins
To make the AD5560 stable with any unknown capacitor
from 0 pF to 160 μF, all four CCx capacitors are required.
However, if the range of load is from 0 pF to 20 µF, then
CC3 can be omitted. Similarly, if the load range is from 0 pF to
2.2 µF, then CC2 and CC3 can be omitted. Only CC0 is required
in autocompensation mode.
Note that safe mode, which makes the device stable in any
load from 0 pF to 160 μF, simply switches in all of the four
CCx capacitors. Stability into 160 μF is assured only if all four
capacitors are present; otherwise, the maximum capacitor for
stability is reduced to 20 μF, 2.2 μF, or 220 nF, depending on
how many capacitors are missing.
EXTRA POLES AND ZEROS IN THE AD5560
The Effect of CCx
CC0 is switched on at all times. CC3, CC2, and CC1 can be connected in addition to CC0 to slow down the force amplifier loop.
In the ±500 mA range looking into a small load capacitor, with
only CC0 connected, the ac gain vs. phase response results in
~90° of phase margin and a unity gain bandwidth (UGB) of
~400 kHz.
The Effect of CFx
The output of the AD5560 passes through a sense resistor to
the DUT. Coupled with the load capacitor, this sense resistor
can act as a low-pass filter that adds phase shift and decreases
phase margin (particularly in the low current ranges where the
sense resistors are large).
Placing a capacitor in parallel with this sense resistor provides
an ac feedforward path to the DUT. Therefore, at high frequencies, the DUT is driven through the CFx capacitor rather than
through the sense resistor.
Note that each CFx output has an output impedance of about
3 Ω. This is very small compared to the sense resistors of the
low current ranges but not so for the highest current ranges.
Therefore, the CFx capacitors are most effective in the low current
ranges but are of lesser benefit in higher current ranges.
As shown in the force amplifier diagram (see Figure 57), there
is a pole at 1/( RSENSE × [CFx + CR]) and a zero at 1/[ RSENSE × CFx].
Therefore, the output impedance of each CFx output, at around
1 Ω, limits the improvement available by using the CFx capacitors. For a large load capacitance, there is still a pole at −1/[1 Ω
× CR] above which the phase improvement is lost. If there is
also a cable resistance to the DUT, or if CFx has significant ESR,
this should be added to the 1 Ω to calculate the pole frequency.
If CFx is chosen to be bigger than the load capacitance, it can
dominate the settling time and slow down the settling of the
whole circuit. Also, it directly affects the time taken to measure
a current (RSENSE × CFx).
The Effect of RZ
When the load capacitance is known, RZ can be used to optimize the response of the AD5560. Because the CFx buffers have
some output impedance of about 1 Ω, there is likely to be some
additional resistance to the DUT. There can still be an output
pole associated with this resistance and the load capacitance,
CR, 1/[R0 × CR] (where R0 = the series/parallel combination of
the sense resistor, the CFx output impedance, the CFx capacitor
ESR, and the cable to DUT). This is particularly significant for
larger load capacitances in any current range. By programming
a zero into the loop response by setting RZ (in series with CC0),
it is possible to cancel this pole. Above the frequency 1/[CC0 ×
RZ], the series resistance and capacitance begin to look resistive
rather than capacitive, and the 90° phase shift and 20 dB/decade
contributed by CC0 no longer apply. Note that, to cancel the
load pole with the RZ zero, the load pole must be known to
exist. Adding a zero to cancel a pole that does not exist causes
an oscillation (perhaps the expected load capacitor is not
present). Also, it is recommended to avoid creating a zero
frequency lower than the pole frequency; instead, allow the zero
frequency to be 2× or 3× higher than the calculated pole
frequency.
The Effect of RP
RP can be used to ensure circuit stability when a poor load
capacitor with significant ESR is present. Above the frequency,
1/[CR × RC], the DUT begins to look resistive. The ESR of the
DUT capacitor, RC, contributes a zero at this frequency. The
load capacitor, CR, is counted on to stabilize the system when
the user has cancelled the load pole with the RZ zero. Just as the
absence of CR under these circumstances can cause oscillations,
the presence of ESR RC while nonzero RZ is used can cause
Rev. D | Page 37 of 68
AD5560
Data Sheet
stability problems. This is most likely to be the case when there
are both a large CR and large RC.
settings when using the manual compensation register (this
algorithm is what the autocompensation method is based upon):
The RP resistor is intended to solve this problem. Again, it is
prudent not to cancel exact pole/zero cancellation with RZ and
instead allow the zero to be 2× to 3× the frequency of the pole.
It is best to be very conservative when using RZ to cancel the
load pole. Choose a high zero frequency to avoid flat spots in
the gain curve that extend bandwidth, and be conservative when
choosing RP to create a pole. Aim to place the RZ zero at 5× the
exact cancellation frequency and the RP pole at around 2× the
exact cancellation frequency. The best solution here is to avoid
this complexity by using a high quality capacitor with low ESR.
1.
2.
COMPENSATION STRATEGIES
Ensuring Stability into an Unknown Capacitor Up to a
Maximum Value
If the AD5560 has to be stable in a range of load capacitance
from no load capacitance to an upper limit, then select manual
compensation mode and, in Compensation Register 2, set the
parameters according to the maximum load capacitance listed
in Table 14.
3.
Table 14. Suggested Compensation Settings for Load Capacitance Range of Unknown Value to Some Maximum Value
4.
Capacitor
Min Max
0
0.22 μF
0
2.2 μF
0
10 μF
0
20 μF
0
160 μF
gm[1:0]
RP[2:0]
RZ[2:0]
CC[3:1]
CF[2:0]
2
2
2
2
2
0
0
0
0
0
0
0
0
0
0
000
001
010
011
111
2
3
4
4
4
5.
6.
Table 14 assumes that the CCx and CFx capacitor values are those
suggested in Table 8.
Making a circuit stable over a range of load capacitances for
no load capacitance or greater means that the circuit is overcompensated for small load capacitances, undercompensated
for high load capacitances, or both. The previous choice settings,
along with the suggested capacitor values, is a compromise
between both. By compromising phase margin into the largest
load capacitors, the system bandwidth can be increased, which
means better performance under load current transient conditions. The disadvantage is that there is more overshoot during a
large DAC step. To reduce this at the expense of settling time, it
may be desirable to temporarily switch a capacitor range 5× or
10× larger before making a large DAC step.
OPTIMIZING PERFORMANCE FOR A KNOWN
CAPACITOR USING AUTOCOMPENSATION MODE
The autocompensation mode decides what values of gmx, CCx
CFx, RZ, and RP should be chosen for good performance in a
particular capacitor. Both the capacitance and its ESR need to
be known. To avoid creating an oscillator, the capacitance should
not be overestimated and the ESR should not be underestimated. Use the following steps to determine compensation
Use CR (the load capacitance with a series ESR) and RC (the
ESR of that load capacitance) as inputs.
Assume that CR has not been overestimated and that RC has
not been underestimated. (Although, when the ESR RC is
shown to have a frequency dependence, the lowest RC that
occurs near the resonant frequency is probably a better
guide. However, do not underestimate this ESR).
a. CC0 is the suggested 100 pF.
b. CFx capacitor values are as suggested, and they extend
up to 2.2 µF (CF4). For faster settling into small
capacitive loads, include smaller CFx values such as CF3
and CF2. If a capacitor is not included, then short the
corresponding CFx pin to one that is.
c. There is approximately 1 Ω of parasitic resistance, RC,
from the AD5560 to the DUT (for example, the cable);
RC = 1 Ω.
Select gm[1:0] = 2, CC[3:1] = 000. This makes the input stage of
the force amplifier; have gmx = 300 µA/V; deselect the
compensation capacitors, CC1, CC2, CC3, so that only CC0 is
active.
Choose a CF[2:0] value from 0 to 4 to select the largest CFx
capacitor that is smaller than CR.
If CR < 100 nF, then set RZ[2:0] = 0, RP[2:0] = 0. This ends the
algorithm.
Calculate R0, the resistive impedance to the DUT, using the
following steps:
a. Calculate RS, the sense resistor, from the selected
current range using RS = 0.5 V/IRANGE.
b. Calculate RF, the output impedance, through the CFx
capacitor, by using
RF = 1.2 Ω + (ESR of CFx capacitor)
c.
Calculate RFM, a modified version of RF, which takes
account of frequency dependent peaking, through the
CFx buffers into a large capacitive load, by using
RFM = RF/(1 + [2 × (CFx/2.2 μF)])
That is, RFM is up to 3× smaller than RF, when the
selected CFx capacitor is large compared to 2.2 μF.
Then calculate
R0 = RC + (RS ||RFM)
7.
8.
9.
Rev. D | Page 38 of 68
where RC takes its value from the assumptions in Step 2.
If RC > (R0/5), then the ESR is large enough to make the
DUT look resistive. Choose RZ[2:0] = 0, RP[2:0] = 0. This ends
the algorithm
Calculate the unity gain frequency (Fug), the ideal unity
gain frequency of the force amplifier, from Fug =
gmx/2πCC0. Using the previously suggested values (gm[1:0] = 2
gives gmx = 300 µA/V and CC0 = 100 pF), Fug calculates to
480 kHz.
Calculate FP, the load pole frequency, using FP =
1/(2πR0CC0).
Data Sheet
AD5560
10. Calculate FZ, the ESR zero frequency, using FZ =
1/(2πRcCr).
11. If FP > Fug, the load pole is above the bandwidth of the
AD5560. Ignore it with RZ[2:0] = 0, RP[2:0] = 0. This ends the
algorithm
12. If RC < (R0/25), then the ESR is negligible. Attempt to
cancel the load pole with RZ zero. Choose an ideal zero
frequency of 2 × FP for some safety margin and then
choose the RZ[2:0] value that gives the closest frequency on a
logarithmic scale. This ends the algorithm
13. Otherwise, this is a troublesome window in which a load
pole and a load zero can’t be ignored. Use the following
steps:
• To cancel the load pole at FP, choose an ideal zero
frequency of 6 × FP (this is more conservative than the
2 × FP suggested earlier, but there is more that can go
wrong with miscalculation). Then choose the RZ[2:0]
value that gives the closest zero to this ideal frequency
of 6 × FP on a logarithmic scale.
• To cancel the ESR zero at FZ, choose an ideal pole
frequency of 2 × FZ.
• Then choose the RP[2:0] value that gives the closest pole
to this ideal frequency of 2 × FZ on a logarithmic scale.
This ends the algorithm
ADJUSTING THE AUTOCOMPENSATION MODE
A more complex alternative is to calculate the overall impedance
at the expected unity gain bandwidth and use this to calculate
an equivalent series CR and RC that have the same complex
impedance at that particular frequency.
DAC LEVELS
This device contains all the dedicated DAC levels necessary
for operation: a 16-bit DAC for the force amplifier, two 16-bit
DACs for the clamp high and low levels, two 16-bit DACs for
the comparator high and low levels, a 16-bit DAC to set a
programmable open sense voltage, and a 16-bit offset DAC
to bias or offset a number of DACs on chip (FORCE, CLL,
CLH, CPL, CPH).
FORCE AND COMPARATOR DACS
The architecture of the main force amplifier DAC consists of
a 16-bit R-2R DAC, whereas the comparator DACs are resistorstring DACs followed by an output buffer amplifier. This
resistor-string architecture guarantees DAC monotonicity.
The 16-bit binary digital code loaded to the DAC register
determines at what node on the string the voltage is tapped
off before being fed to the output amplifier.
The comparator DAC is similarly arranged. The force and
comparator DACs have a 25.62 V span, including overrange
to enable offset and gain errors to be calibrated out.
The transfer function for these 16-bit DACs is
The autocompensation algorithm assumes that there is 1 Ω of
resistance (RC) from the AD5560 to the DUT. If a particular
application has resistance that differs greatly from this, then
it is likely that the autocompensation algorithm is nonoptimal.
If using the autocompensation algorithm as a starting point,
consider that overstating the CR capacitance and understating
the ESR RC is likely to give a faster response but could cause
oscillations. Understating CR and overstating RC is more likely
to slow things down and reduce phase margin but not create
an oscillator.
It is often advisable to err on the side of simplicity. Rather than
insert a pole and zero at similar frequencies, it may be better to
add none at all. Set RP[2:0] = RZ[2:0] = 0 to push them beyond the
AD5560 bandwidth.
DEALING WITH PARALLEL LOAD CAPACITORS
In the event that the load capacitance consists of two parallel
capacitors with different ESRs, it is highly likely that the overall
complex impedance at the unity gain bandwidth is dominated
by the larger capacitor and its ESR. Assuming that the smaller
capacitor does not exist normally is a safer simplifying assumption.
 DAC CODE 
VOUT = 5.125 × VREF × 
 − 5.125 × VREF ×
216


 OFFSET _ DAC _ CODE 
 + DUTGND

216


where DAC CODE is X2 (see the Offset and Gain Registers
section).
CLAMP DACS
The architecture of the clamp DAC consists of a 16-bit resistorstring DAC followed by an output buffer amplifier. This resistorstring architecture guarantees DAC monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier.
The clamp DACs have a 25.62 V span, including overrange, to
enable offset and gain errors to be calibrated out.
Rev. D | Page 39 of 68
AD5560
Data Sheet
Table 15. Offset DAC Relationship with Other DACs, VREF = 5 V
The transfer function for these 16-bit DACs is
 DAC CODE 
VCLH , VCLL = 5.125 × VREF × 
 − 5.125 × VREF ×
216


 OFFSET _ DAC _ CODE  + DUTGND


216


The transfer function for the clamp current value is
 DAC CODE − 32768 
5.125 × VREF × 

216


ICLL, ICLH =
RSENSE × MI _ AMP _ GAIN
where:
RSENSE is the sense resistor.
MI_AMP_GAIN is the gain of the MI amp (either 10 or 20).
OSD DAC
The OSD DAC is a 16-bit DAC function, again a resistor string
DAC guaranteeing monotonicity. The 16-bit binary digital
code loaded to the DAC register determines at what node on
the string the voltage is tapped off before being fed to the
output amplifier. The OSD function is used to program the
voltage difference needed between the force and sense lines
before the alarm circuit flags an error. The OSD DAC has a
range of 0.62 V to 5 V. The transfer function is as follows:
 DAC CODE 
VOUT = VREF × 

216


(1)
The offset DAC does not affect the OSD DAC output range.
DUTGND DAC
Similarly, the DUTGND DAC (DGS) is a 16-bit DAC and uses
a resistor string DAC to guarantee monotonicity. The 16-bit
binary digital code loaded to the DAC register determines at
what node on the string the voltage is tapped off before being
fed to the output amplifier. This function is used to program
the voltage difference needed between the DUTGND and
AGND lines before the alarm circuit flags an error.
The DUTGND DAC has a range of 0 V to 5 V. The transfer
function for this 16-bit DAC is shown in Equation 1.
The offset DAC does not affect the OSD DAC output range.
OFFSET DAC
Offset DAC Code
0
0
0
…
32,768
32,768
32,768
…
57,344
57,344
57,344
…
65,355
1
DAC Code1
0
32,768
65,535
…
0
32,768
65,535
…
0
32,768
65,535
…
…
DAC Output Voltage Range
0.00
12.81
25.62
…
−12.81
0.00
12.81
…
−22.42
−9.61
3.20
…
Footroom limitations
DAC code shown for 16-bit force DAC.
OFFSET AND GAIN REGISTERS
Each DAC level contains independent offset and gain control
registers that allow the user to digitally trim offset and gain.
These registers give the user the ability to calibrate out errors
in the complete signal chain (including the DAC) using the
internal m and c registers, which hold the correction factors.
The digital input transfer function for the DACs can be
represented as
x2 = [x1 × (m + 1)/2n] + (c – 2n – 1)
where:
x2 is the data-word loaded to the resistor string DAC.
x1 is the 16-bit data-word written to the DAC input register.
m is the code in the gain register (default code = 216 – 1).
n is the DAC resolution (n = 16).
c is the code in the offset register (default code = 215).
Offset and Gain Registers for the Force Amplifier DAC
The force amplifier input (FIN) DAC level contains independent
offset and gain control registers that allow the user to digitally
trim offset and gain. There is one set of registers for the force
voltage range: x1, m, and c.
Offset and Gain Registers for the Comparator DACs
In addition to the offset and gain trim, there is also a 16-bit
offset DAC that offsets the output of each DAC on chip. Therefore, depending on headroom available, the input to the force
amplifier can be arranged either symmetrically or asymmetrically
about DUTGND but always within a voltage span of 25 V. Some
extra gain is included to allow for system error correction using
the m (gain) and c (offset) registers.
The usable voltage range is −22 V to +25 V. Full scale loaded
to the offset DAC does not give a useful output voltage range
because the output amplifiers are limited by available footroom.
Table 15 shows the effect of the offset DAC on other DACs in
the device (clamp, comparator, and force DACs).
The comparator DAC levels contain independent offset and
gain control registers that allow the user to digitally trim offset
and gain. There are seven sets of registers consisting of a combination of x1, m, and c, one set each for the five internal force
current ranges and one set each for the two external high
current ranges.
Offset and Gain Registers for the Clamp DACs
The clamp DAC levels contain independent offset and gain
control registers that allow the user to digitally trim offset
and gain. One set of registers covers the VSENSE range, the five
internal force current ranges, and the two external high current
ranges. Both clamp DAC x1 registers and their associated offset
and gain registers are 16 bit.
Rev. D | Page 40 of 68
Data Sheet
AD5560
REFERENCE SELECTION
The voltage applied to the VREF pin determines the output
voltage range and span applied to the force amplifier, clamp,
and comparator inputs and the current ranges.
This device can be used with a reference input ranging from
2 V to 5 V. However, for most applications, a reference input
of 5 V is able to meet all voltage range requirements. The DAC
amplifier gain is 5.125, which gives a DAC output span of
25.625 V. The DACs have gain and offset registers that can
be used to calibrate out system errors. In addition, the gain
register can be used to reduce the DAC output range to the
desired force voltage range.
Using a 5 V reference and setting the m (gain) register to onefourth scale or 0x4000 gives an output voltage span of 6.25 V.
Because the force DAC has 18 bits of resolution even with only
one-fourth of the output voltage span, it is still possible to
achieve 16-bit resolution in this 6.25 V range.
The measure current amplifier has two gain settings, 10 and 20.
The two gain settings allow users to achieve the quoted/specified current ranges with large or small voltage swings. The 20
gain setting is intended for use with a 5 V reference, and the 10
gain setting is for use with a 2.5 V reference. Both combinations
ensure the specified current ranges. Other VREF/gain setting
combinations should be used only to achieve smaller current
ranges. See Table 27 for suggested references for use with the
AD5560.
CHOOSING AVDD/AVSS POWER SUPPLY RAILS
As noted in the Specifications section, the minimum supply
variation across the part is |AVDD − AVSS| ≥ 16 V and ≤ 33 V,
AVDD ≥ 8 V, and AVSS ≤ −5 V. For the AD5560 circuits to
operate correctly, the supply rails must take into account not
only the force voltage range but also the internal DAC
minimum voltage level, as well as headroom/footroom.
The DAC amplifier gains VREF by 5.125, and the offset DAC
centers that range about some chosen point. Because the DAC
minimum voltage (VMIN) is used in other parts of the circuit
(MEASOUT gain of 0.2), it is important that AVSS be chosen
based on the following:
AVSS ≤ −5.125 × (VREF × (OFFSET_DAC_CODE/216)) −
AVSS_Headroom − VDUTGND − (RCABLE × ILOAD)
where:
AVSS_Headroom is the 2.75 V headroom (includes the RSENSE
voltage drop).
VDUTGND is the voltage range anticipated at DUTGND.
RCABLE is the cable/path resistance.
ILOAD is the maximum load current.
When choosing AVDD, remember to take into account the
specified current ranges. The measure current block has either
a gain of 20 or 10 and must have sufficient headroom/
footroom to operate correctly.
As the nominal, VRSENSE is ±0.5 V for the full-scale specified
current flowing for all ranges. If this is gained by 20, the
measure current amplifier output (internal node) voltage
range is ±10 V with full-scale current and the default offset
DAC setting. The measure current block needs ±2.25 V
footroom/headroom for correct operation in addition to
the ±0.5 V VRSENSE.
For simplicity, when VREF = 5 V, minimum |AVDD − AVSS| =
31.125 V (VREF × 5.125 + headroom + footroom); otherwise,
there can be unanticipated effects resulting from headroom/
footroom issues. This does not take into account cable loss or
DUTGND contributions.
Similarly, when VREF = 2.5 V, minimum |AVDD − AVSS| = 18.3 V
and, when VREF = 2 V, minimum |AVDD − AVSS| = 16 V.
The AD5560 is designed to settle fast into large capacitive loads;
therefore, when slewing, the device draws 2× to 3× the current
range from the AVDD/AVSS supplies. When supply rails are
chosen, they should be capable of supplying each DPS channel
with sufficient current to slew.
CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS
Selection of HCAVSSx and HCAVDDx supplies is determined by
the EXTFORCE1 and EXTFORCE2 output ranges. The supply
rails chosen must take into account headroom and footroom,
DUTGND voltage range, cable loss, supply tolerance, and
VRSENSE. If diodes are used in series with the HCAVSSx and
HCAVDDx supplies pins (shown in Figure 59), the diode voltage
drop should also be factored into the supply rail calculation.
The AD5560 is designed to settle fast into large capacitive loads
in high current ranges; therefore, when slewing, the device draws
2× to 3× the current range from the HCAVSSx and HCAVDDx
supplies. When choosing supply rails, ensure that they are
capable of supplying each DPS channel with sufficient current
to slew.
All output stages of the AD5560 are symmetrical; they can
source and sink the rated current. Supply design/bypassing
should account for this.
POWER DISSIPATION
The maximum power dissipation allowed in the EXTFORCE1
stage is 10 W, whereas in the EXTFORCE2 stage, it is 5 W.
Take care to ensure that the device is adequately cooled to
remove the heat. The quiescent current is ~0.8 W with an
internal current range enabled and ~1 W with external current
ranges, EXTFORCE1 or EXTFORCE2, enabled. This device is
specified for performance up to 90°C junction temperature (TJ).
Rev. D | Page 41 of 68
AD5560
Data Sheet
PACKAGE COMPOSITION AND MAXIMUM
VERTICAL FORCE
The exposed pad and leads of the TQFP package have a 100%
tin finish. The exposed paddle is connected internally to AVSS.
The simulated maximum allowable force for a single lead is
0.18 lbs; total allowable force for the package is 11.5 lbs. The
quoted maximum force may cause permanent lead bending.
Other package failure (die, mold, board) may occur first at
lower forces.
SLEW RATE CONTROL
There are two methods of achieving different slew rates using
the AD5560. One method is using the programmable slew rate
feature that gives eight programmable rates. The second
method is using the ramp feature and an external clock.
Programmable Slew Rate
Eight programmable modes of slew rates are available to choose
from through the serial interface, enabling the user to choose
different rates to power up the DUT. The different slew rates
are achieved by variation in the internal compensation of the
force DAC output amplifier. The slew rates available are
1.000 V/µs, 0.875 V/µs, 0.750 V/µs, 0.625 V/µs, 0.5 V/µs,
0.4375 V/µs, 0.35V µs, and 0.313 V/µs.
Ramp Function
Included in the AD5560 is a ramp function that enables the
user to apply a rising or falling voltage ramp to the DUT. The
user supplies a clock, RCLK, to control the timing.
This function is controlled via the serial interface and requires
programming of a number of registers to determine the end
value, the ramp size, and the clock divider register to determine
the update rate.
The contents of the FIN DAC x1 register are the ramp start
value. The user must load the end code register and the step
size register. The sign is now generated from the difference
between the FIN DAC x1 register and the end code; then the
step size value is added to or subtracted from FIN DAC x1,
calibrated and stored. The user must supply a clock to the RCLK
pin to load the new code to the DAC. The output settles in 1.2 µs
for a step of 10 mV with CDUT in the lowest range of <0.2 µF.
While the output is settling, the next step is calculated to be
ready for the next ramp clock. The calibration engine is used
here; therefore, there is a calibration delay of 1.2 µs.
The ramp timing is controlled in two ways: by a user-supplied
clock (RCLK) and by a clock divider register. This gives the
user much flexibility over the frequency of the ramp steps. The
ramp typically starts after (2 × clock divider + 2) clocks,
although there can be a ±1 clock delay due to the asynchronous
nature of RCLK. The external clock can be a maximum of 833
kHz when using clock divider = 1. Faster RCLK speeds can be
used, but the fastest ramp rate is linked into the DAC
calibration engine.
For slower ramp rates, an even slower RCLK can be used.
The step sizes are in multiples of 16 LSBs. If the code previous
to the end code is not a multiple of this step size, the last step is
smaller. If the ramp function must be interrupted at any stage
during the ramp, write the interrupt ramp command. The FIN
DAC x1 stops ramping at the current value and returns to
normal operation.
The fastest ramp rate is 0.775 V/µs (for a 5 V reference and an
833 kHz clock using a 2032 LSB step size and divider = 1).
The slowest ramp rate is 24 µV/µs (for a 5 V reference and an
833 kHz clock using a 16 LSB step size and divider = 255).
Even slower ramps can be achieved with slower SCLK. The
ramp continues until any of the following occurs:
•
•
•
It reaches the end code.
An interrupt ramp is received from the user.
If any enabled alarm triggers, the ramp stops to allow
the user to service the activated alarm.
While the device is in ramp mode, the only command that the
interface accepts is an interrupt ramp. No other commands should
be written to the device while ramping because they are ignored.
Rev. D | Page 42 of 68
Data Sheet
AD5560
NEW RAMP
CHANGE
STEP SIZE?
YES
SELECT RAMP SIZE
NO
CHANGE
CLOCK
DIVISION?
YES
PROGRAM
CLOCK DIVIDER
YES
WRITE NEW
FIN ×1 DAC VALUE
NO
CHANGE RAM P
START?
NO
WRITE RAMP END CODE
RAMP MODE
ENABLE RAMP
UPDATE DAC
CODE?
YES
CALCULATE
NEXT DAC CODE
LOAD DAC
NO
INTERRUPT
RAMP?
ALARM?
YES
DO NOT LOAD DAC.
RETAIN PREVIOUS
VALUE
NO
RAMP
COMPLETE?
YES
RETURN TO
NORMAL MODE
TERMINATE RAMP
Figure 58. Flow Chart for Ramp Function
Rev. D | Page 43 of 68
07779-011
NO
AD5560
Data Sheet
SERIAL INTERFACE
The AD5560 contains an SPI-compatible interface operating at
clock frequencies of up to 50 MHz. To minimize both the
power consumption of the device and on-chip digital noise, the
interface powers up fully only when the device is being written
to, that is, on the falling edge of SYNC.
SPI INTERFACE
The serial interface is 2.5 V LVTTL-compatible when operating
from a 2.3 V to 3.6 V DVCC supply. It is controlled by the
following four pins:
•
•
•
•
SYNC (frame synchronization input)
SDI (serial data input pin)
SCLK (clocks data in and out of the device)
SDO (serial data output pin for data readback)
SPI WRITE MODE
The AD5560 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which
is all registers except the DAC registers.
The serial word is 24 bits long. The serial interface works with
both a continuous and a burst (gated) serial clock. Serial data
applied to SDI is clocked into the AD5560 by clock pulses applied
to SCLK. The first falling edge of SYNC starts the write cycle.
At least 24 falling clock edges must be applied to SCLK to clock
in 24 bits of data before SYNC is taken high again.
The input register addressed is updated on the rising edge of
SYNC. For another serial transfer to take place, SYNC must be
taken low again.
SDO OUTPUT
The SDO output in the AD5560 is a weak/slow output driver.
If using readback or the daisy-chain function, the frequency of
SCLK must be reduced so that SDO can operate properly. The
SCLK frequency is dependent on the DVCC supply voltage used;
see Table 2 for details and the following example:
BUSY FUNCTION
BUSY is a digital open-drain output that indicates the status of
the AD5560. All writes drive the BUSY output low for some
period of time; however, events that use the calibration engine,
such as all DAC x1 writes, drive it lower for a longer period of
time while the calculations are completed.
For the DACs, the value of the internal data (x2) loaded to the
DAC data register is calculated each time the user writes new
data to the corresponding x1 register. During the calculation
of x2, the BUSY output goes low and x2 writes are pipelined;
therefore, x2 writes can still be presented to the device while
BUSY is still low (see the Register Update Rates section). The
DAC outputs update immediately after BUSY goes high.
Writes to other registers must be handled differently and
should either watch the BUSY pin or be timed. While BUSY
is low, the user can continue writing new data to any control
register, m register, or c register but should not complete the
writing process (SYNC returning high) until the BUSY signal
has returned high.
BUSY also goes low during power-on reset, as well as when a
low level is detected on the RESET pin.
BUSY writes to the system control register, compensation
register, alarm register, and diagnostic register; m or c registers
do not involve the calibration engine, thus speeding up writing
to the device.
LOAD FUNCTION
The AD5560 device contains a function with which updates
to multiple devices can be synchronized using the LOAD
function. There is not a dedicated pin available for this
function; however, either the CLEN or HW_INH pin can
be used as a LOAD input (selection is made in the system
control register, Address 0x1, Bits[8:7]).
Maximum SCLK = 15 MHz, then DVCC = 2.7 V to 3.3 V
When selected as the LOAD function, the pin no longer
operates in its previous function (power-on default for each
of these pins is a CLEN or HW_INH function).
Maximum SCLK = 20 MHz, then DVCC = 4.5 V to 5.5 V
The LOAD function controls the following registers:
RESET FUNCTION
•
•
•
•
•
•
Maximum SCLK = 12 MHz, then DVCC = 2.3 V to 2.7 V
RESET is a level-sensitive input. Bringing the RESET line low
resets the contents of all internal registers to their power-on
reset state. The falling edge of RESET initiates the reset process;
BUSY goes low for the duration, returning high when the
RESET process is complete. This sequence takes 300 µs
maximum. Do not write to the serial interface while BUSY
is low handling a RESET command. When BUSY returns high,
normal operation resumes, and the status of the RESET pin is
ignored until it goes low again.
0x8 FIN DAC x2 register
0xD CLL DAC x2 register
0x10 CLH DAC x2 register
0x4 Compensation Register 1
0x5 Compensation Register2
0x2 DPS Register1 (only current ranges, Bits[13:11])
There is, however, an alternate method for updating and using
the CLEN and HW_INH pins in their normal function.
Rev. D | Page 44 of 68
Data Sheet
AD5560
If Bits[8:7] of the system control register (Address 0x1) are
high, then the CLEN and HW_INH operate as normal, and the
update waits until BUSY goes high (this way multiple channels
can still be synchronized by simply tying BUSY pins together).
REGISTER UPDATE RATES
As mentioned previously, the value of the x2 register is
calculated each time the user writes new data to the
corresponding x1 register. The calculation is performed by a
three stage process. The first two stages take 600 ns each, and
the third stage takes 300 ns. When the write to one of the x1
registers is complete, the calculation process begins. The user
is free to write to another register provided that the write
operation does not finish until the first stage calculation is
complete, that is, 600 ns after the completion of the first write
operation.
Rev. D | Page 45 of 68
AD5560
Data Sheet
CONTROL REGISTERS
DPS AND DAC ADDRESSING
A no operation (NOP) command performs no function within
the device. This code may be useful when performing a
readback function where a change of DAC or DPS register is
not required.
The serial word assignment consists of 24 bits, as shown in
Table 16. All write-to registers can be read back. There are
some read-only registers (Address 0x43 and Address 0x44).
DAC x2 registers are not available for readback.
Table 16. Serial Word Assignment
B23
R/W
[B22:B16]
Address bits
[B15:B0]
Data bits
Table 17. Read or Write Register Addressing
Address
0x0
0x1
Register
NOP
System
control
register
Default
0x0000
0x0000
Data Bits, MSB First
NOP command; performs no operation.
Bit Name
Function
15
14
TMP[1:0]
13
12
Gain[1:0]
11
FINGND
10
CPO
9
PD
8
7
LOAD
6:0
Unused
Thermal shutdown bits. TMP1, TMP0 allow the user to program the thermal
shutdown temperature of operation.
TMP
Action
0
Shutdown at a TJ of 130°C (power-on default)
1
Shutdown at a TJ of 120°C
2
Shutdown at a TJ of 110°C
3
Shutdown at a TJ of 100°C
MEASOUT output range. The MEASOUT range defaults to the voltage force span for
voltage and current measurements (this is ±12.81 V), which includes some overrange
to allow for error correction. The MEASOUT range can be reduced by using the gain
bits. This allows for use of asymmetrical supplies or for use of a smaller input range ADC.
MEASOUT gain settings do not translate the low voltage temperature sensor signal
(TSENSE).
Gain
MEASOUT Gain
MI Gain
0
1
20
1
1
10
2
0.2
20
3
0.2
10
To allow for system error correction, there is an additional gain of 0.125 for the force
function if this error correction is used as intended; then the output range on
MEASOUT scales accordingly (see Table 9).
Writing a 1 to FINGND switches the positive input of the force amplifier to GND; when
0, the input of the force amplifier is connected to the output of the force DAC.
Write a 1 to the CPO bit to enable a simple window comparator function. In this
mode, only one comparator output is available (CPOH/CPO). This provides two bits of
information. The compared value is either inside or outside the window and enables
the user to bring only one line back to the controller per DPS device.
This bit powers down the force amplifier block. Note that the amplifier must be
powered up but inhibited (SW-INH or HW_INH), to meet leakage specifications. A 0
powers this block down (default).
Updates to registers listed in the following LOAD function column do not occur until
the active LOAD pin is brought low (or in the case of LOAD 3, until BUSY goes high).
LOAD
0
LOAD Function
Default operation, CLEN and HW_INH function normally.
1
The CLEN pin is a LOAD input.
2
The HW_INH pin is a LOAD input.
3
The device senses the BUSY open-drain pin and doesn't update until that
goes high. No LOAD hardware pin. CLEN and HW_INH function normally.
Set to 0.
Rev. D | Page 46 of 68
Data Sheet
AD5560
Table 18. DPS Register 1
Address
0x2
Default
0x0000
Bit
15
Name
SW-INH
Data Bits, MSB First
Function
This bit enables the force amplifier when high and disables the amplifier when low. This bit is AND’d with the
HW_INH hardware inhibit pin.
14
13
12
11
Reserved
I[2:0]
Reserved, set to 0.
Current range addressing. These bits allow selection of the required current range.
10
CMP[1:0]
9
8
7
6
5
ME[3:0]
4
CLEN
3:0
Unused
I
Action
0
±5 µA current range.
1
±25 µA current range.
2
±250 µA current range.
3
±2.5 mA current range.
4
±25 mA current range.
5
External Range 2.
6
External Range 1.
7
Reserved.
Comparator function. CMP1 acts as a comparator output enable, whereas CMP0 selects between a
comparing DUT current or voltage; by default, the comparators are high-Z on power-on.
CMP
Action
0
Comparator outputs high-Z.
1
Comparator outputs high-Z.
2
Compare DUT current.
3
Compare DUT voltage.
Bits ME[3:0] allow selection of the required measure mode, allowing the MEASOUT line to be disabled;
connect to the temperature sensor or enable it for measurement. ME3 is MEASOUT enable/disable; when
high, MEASOUT is enabled, and ME[2:0] can be used to preselect the measuring parameter. Where a
number of MEASOUT lines are connected together and passed to a common ADC, this function can allow
for much faster measurement time between channels because the slew time of the measurement buffer is
reduced. For details on diagnostic functions, see Address 0x7, the diagnostic register.
ME[2:0]
Action
0
MEASOUT high-Z.
1
Connect MEASOUT to ISENSE.
2
Connect MEASOUT to VSENSE.
3
Connect MEASOUT to KSENSE.
4
Connect MEASOUT to TSENSE.
5
Connect MEASOUT to DUTGND SENSE.
6
Connect MEASOUT to diagnostic functions: DIAG A (see Address 0x7).
7
Connect MEASOUT to diagnostic functions: DIAG B (see Address 0x7).
Clamp enable; set high to enable the clamp; set low to disable the clamp. This bit is OR’d with the
hardware CLEN pin.
Set to 0.
Rev. D | Page 47 of 68
AD5560
Data Sheet
Table 19. DPS Register 2
Address
0x3
Default
0x0000
Bit
15
Name
SF0
14
13
12
SR[2:0]
11
GPO
10
9
SLAVE,
GANGIMODE
8
INT10K
7
Guard high-Z
6:0
Unused
Data Bits, MSB First
Function
System force and sense line addressing, SF0. Bit SF0 addresses each of the different
combinations of switching the system force and sense lines to the force and sense pins at the
DUT.
Guard High-Z
(Bit 7)
SFO
SYS_SENSE Pin SYS_FORCE Pin GUARD/SYS_DUTGND Pin
0
0
Open
Open
Guard
0
1
Sense
Force
Guard
1
0
Open
Open
Open
1
1
Sense
Force
DUTGND
Slew rate control, SR2, SR1, SR0. Selects the slew rate for the main DAC output amp.
SR
Action
0
1 V/μs
1
0.875 V/μs
2
0.75 V/μs
3
0.62 V/μs
4
0.5 V/μs
5
0.43 V/μs
6
0.35 V/μs
7
0.3125 V/μs
General purpose output bit. The GPO bit can be used for any function, such as disconnecting
the decoupling capacitor to help speed up low current testing.
Ganging multiple devices increases the current drive available. Use these bits to enable
selection of the ganging mode and place the device in slave or master mode. In default
operation, each device is a master (gang of one). Figure 54 shows how the device is configured
in this mode.
SLAVE
Action
0
Master: MASTER_OUT = internally connects to active EXTFORCE1/
EXTFORCE2 output
1
Master: MASTER_OUT = master MI
2
SLAVE FV to EXTFORCE1/EXTFORCE2 connected internally to close the
FVAMP loop
3
SLAVE FI
Setting this bit high allows the user to connect an internal sense short resistor of 10 kΩ
between the force and the sense lines (closes SW11). This resistor is actually made up of series
4 kΩ resistors followed by a 2 kΩ switch and another 4 kΩ resistor. There is a 10 kΩ resistor that
can be connected between the FORCE and SENSE pins by use of SW11. This 10 kΩ resistor is
intended to maintain a force/sense connection when a DUT is not in place. It is not intended
to be connected when measurements are being made because this defeats the purpose of the
OSD circuit in identifying an open circuit between FORCE and SENSE. In addition, the sense
path has a 2.5 kΩ resistor in series; therefore, if the 10 kΩ switch is closed, errors may become
apparent when in high current ranges.
Set this bit high to high-Z the guard amplifier. This is required if using the GUARD/
SYS_DUTGND pin in the SYS_DUTGND function.
Set to 0.
Rev. D | Page 48 of 68
Data Sheet
AD5560
The AD5560 has three compensation modes. The power-on default mode is SAFEMODE enabled. This ensures that the device is stable
into any load. Use Compensation Register 1 to configure the device for autocompensation, where the user inputs the CDUT and ESR
bits, and the AD5560 chooses the most appropriate compensation scheme for these load conditions.
Table 20. Compensation Register 1
Address
0x4
Default
0x0000
Bit
15
14
13
12
Name
CDUT[3:0]
11
10
9
8
ESR[3:0]
7
SAFEMODE
6:0
Reserved
Data Bits, MSB First
Function
Use these control bits to tell the device how much capacitive load there is so that the device can
optimize the compensation used. Do not overestimate CDUT because this can cause oscillations.
Underestimating CDUT gives suboptimal but stable performance.
CDUT
CDUT Min
CDUT Max
0
0 nF
50 nF
1
50 nF
83 nF
2
83 nF
138 nF
3
138 nF
229 nF
4
229 nF
380 nF
5
380 nF
630 nF
6
630 nF
1.1 µF
7
1.1 µF
1.7 µF
8
1.7 µF
2.9 µF
9
2.9 µF
4.8 µF
10
4.8 µF
7.9 µF
11
7.9 µF
13 µF
12
13 µF
22 µF
13
22 µF
36 µF
14
36 µF
60 µF
15
60 µF
160 µF
Use these control bits to tell the device how much ESR there is in series with CDUT so that the device can
optimize the compensation used. Do not underestimate ESR because this can cause oscillations.
Overestimating ESR gives suboptimal but stable performance.
ESR
ESR Min
ESR Max
0
0 mΩ
1 mΩ
1
1 mΩ
1.8 mΩ
2
1.8 mΩ
3.4 mΩ
3
3.4 mΩ
6.3 mΩ
4
6.3 mΩ
12 mΩ
5
12 mΩ
21 mΩ
6
21 mΩ
40 mΩ
7
40 mΩ
74 mΩ
8
74 mΩ
140 mΩ
9
140 mΩ
250 mΩ
10
250 mΩ
460 mΩ
11
460 mΩ
860 mΩ
12
860 mΩ
1500 mΩ
13
1500 mΩ
2900 mΩ
14
2900 mΩ
5400 mΩ
15
6400 mΩ
10,000 mΩ
SAFEMODE = 0 overrides values in Compensation Register 1 to make the force amplifier stable under
most load conditions. This mode is useful if it is unknown what the DPS is driving, but it does result in an
extremely slow response. The default operation on power-on or reset is SAFEMODE.
SAFEMODE settings are always gm[1:0] = 2, RP[2:0] = 0, RZ[2:0] = 0, CC[3:1] = 111, CF[2:0] = 5, and CC0 = 1.
Set this bit high to enable autocompensation.
Set to 0.
Rev. D | Page 49 of 68
AD5560
Data Sheet
Table 21. Compensation Register 2
Address
0x5
Default
0x0110
Bit
15
Name
Manual
compensation
14
13
12
RZ[2:0]
11
10
9
RP[2:0]
8
7
gm[1:0]
Data Bits, MSB First
Function
The AD5560 can be manually configured to compensate the force amplifier into a wide range of load
conditions. When this bit is high, manual compensation mode is active, and it overrides the settings of
Compensation Register 1. Readback when in manual compensation mode returns the compensation
settings loaded to the force amplifier and loaded to this register. Similarly, when in autocompensation
mode, readback of this register address returns the compensation settings of the force amplifier. However,
readback of this register address when in safe mode does not reflect SAFEMODE settings. SAFEMODE
settings are gm[1:0] = 2, RP[2:0] = 0, RZ[2:0] = 0, CC[3:1] = 111, CF[2:0] = 5, and CC0 = 1.
Set the value of RZ to add a zero at the following frequencies. This calculation assumes that CC0 = 100 pF.
RZ
RZx(Ω)
FZ (Hz)
01
500
3.2 M
1
1.6 k
1M
2
5k
320 k
3
16 k
100 k
4
50 k
32 k
5
160 k
10 k
6
500 k
3.2 k
7
1.6 M
1k
Set the value of RP to add an additional pole. There is an internal 8 pF capacitor to provide an RC filter,
creating a pole at one of the following frequencies.
RP[2:0]
RP (Ω)
FP (Hz)
200
100 M
01
1
675
29 M
2
2280
8.7 M
3
7700
2.6 M
4
26 k
760 k
5
88 k
220 k
6
296 k
67 k
7
1M
20 k
Set the transconductance of the force amplifiers input stage. The gain bandwidth (GBW) of the force
voltage loop is equal to gmx/CC0. The following values assume CC0 = 100 pF.
gmx
gmx (µA/V)
GBW (Hz)
0
40
64 k
1
80
130 k
300
480 k (default)
900
1.3 M
1
2
3
6
5
4
CF[2:0]
These bits determine which feedforward capacitor CFx is switched in.
CFx
0
1
2
3
4
Action
None
CF0
CF1
CF2
CF3
CF4
51
6
7
1
None
None
3
CC3
Connect CC3 in series with 100 kΩ1
2
CC2
Connect CC2 in series with 25 kΩ1
1
CC1
0
Reserved
Connect CC1 in series with 6 kΩ1
0
This item corresponds to a SAFEMODE setting (SAFEMODE is the power-on default setting).
Rev. D | Page 50 of 68
Data Sheet
AD5560
Register 0x6 allows the user to enable or disable any of the alarm flags that are not required. If disabled, that particular alarm no longer
flags on the appropriate open-drain pin; however, the alarm status is still available in both of the alarm status registers (Address 0x43 and
Address 0x44).
Table 22. Alarm Setup Register
Address
0x6
Default
0x0000
Data Bits, MSB First
Bit Name
Function
15 Latched
Set this latched bit high to program the open-drain TMPALM alarm pin as a latched output;
TMPALM
leave low for an unlatched alarm pin (default).
14 Disable
Set this bit high to disable the open-drain TMPALM alarm pin; leave low to leave enabled (default).
TMPALM
13
Latched
OSALM
12
Disable
OSALM
11
Latched
DUTALM
10
Disable
DUTALM
9
Latched
CLALM
Disable
CLALM
8
Set this latched bit high to program the OSALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
Set this bit high to disable the OSALM alarm function flagging the open-drain KELALM pin;
leave low to remain enabled (default). The disable GRDALM, DUTALM, and OSALM alarm
functions share one open-drain KELALM alarm pin. These bits allow users to choose if they wish
to have all or selected information flagged to the alarm pin.
Set this latched bit high to program the DUTALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
Set this bit high to disable the DUTALM alarm function flagging the open-drain KELALM pin.
Leave low to leave enabled (default). The disable GRDALM, DUTALM, and OSALM alarm
functions share one open drain KELALM alarm pin. These bits allow users to choose if they wish
to have all or any information flagged to the alarm pin. The DUTGND pin has a 50 µA pull-up to
allow for detection of an error in the DUTGND path. Setting this bit high also disables the 50 µA
pull-up.
Set this latched bit high to program the open-drain CLALM clamp alarm pin as a latched
output; leave low for an unlatched alarm pin (default).
Set this bit high to disable the open drain CLALM alarm pin; leave low to leave enabled (default).
7
Latched
GRDALM
6
Disable
GRDALM
Set this latched bit high to program the GRDALM as a latched alarm on the open-drain KELALM
pin; leave low for an unlatched alarm pin (default).
Set this bit high to disable the GRDALM alarm function flagging the open-drain KELALM pin;
leave low to leave enabled (default). The disable GRDALM, DUTALM and OSALM alarm functions
share one open-drain KELALM alarm pin. These bits allow users to choose if they wish to have
all or any information flagged to the KELALM alarm pin.
5:0
Unused
Set to 0.
Rev. D | Page 51 of 68
AD5560
Data Sheet
Table 23. Diagnostic Register
Address
0x7
Default
0x0000
Bit
15
14
13
12
Name
DIAG
select[3:0]
11
10
9
8
7
TSENSE
select[3:0]
Data Bits, MSB First
Function
DIAG select selects the set of diagnostic signals that can be made available on MEASOUT. First, use MEASOUT
addressing (DPS Register 1) to select either the DIAG A or the DIAG B node to be made available on MEASOUT.
Selected
DIAG Select
Measure Block
DIAG A
DIAG B
0:3
Disabled
Disabled
Disabled
4
Force amplifier
Disabled
Disabled
5
EXTFORCE1A
EXTFORCE2A
6
FINP
FINM
7
Output 2.5 mA
Output 25 mA
8
Measure block
VPTAT low
VPTAT high
VTSD low (ref V
9
VTSD high (ref V for +130°C)
for −273°C)
10
MI
VMID Code
11
MV
VMIN Code
12
DAC block
FORCE DAC
VOS DAC
13
CLL DAC
CLH DAC
14
CPL DAC
CPH DAC
15
OSD DAC
DGS DAC
VPTAT low/VPTAT high are temperature sensor devices in the middle of the enabled power stage, which gives a
voltage level that can be mapped back to the VTSD low and VTSD high reference points to get a temperature
value. These sensors are used in the thermal shutdown feature. See the Die Temperature Sensor and
Thermal Shutdown section.
VMID code is the midscale voltage of the DACs; the offset DAC has a direct effect on this voltage level.
VMIN code is the zero-scale voltage of the DACs; again the offset DAC has a direct effect.
The following codes allow selection of one of three sets of eight thermal diodes. The D+ of the selected thermal
diode is available on the GPO pin; the D− is on the AGND.
These thermal diodes are located across the die, in the cool parts and in the power stages. Diodes [16:23] are located
in the force amplifier NPNs (power output devices for supplying current). Similarly, Diodes [24:31] are located in
the force amplifier PNP devices (output devices for sinking current).
TSENSE Select
0:7
8
Selected
Thermal Block
N/A—normal
GPO operation
Cool block
9
10
11
12
13
14
15
16
17
18
Force amplifier
PNPs
19
20
21
22
23
Rev. D | Page 52 of 68
Connected Sensor
No sensor connected
Cool end of high current drivers, hot side of digital
block
25 mA output stage
Hottest part of sensitive measurement circuitry
and cool part of force amplifier
Coolest end of force amplifier block
Coolest end of DACs
Beside TSENSE available on MEASOUT
Hottest part of DACs
Cool side of digital block
1A-1
1A-2
2A (similar location to VPTAT low for EXTFORCE2
range)
1B-1 (similar location to VPTAT low for EXTFORCE1
range)
1B-2
2B
1C-1
1C-2
Data Sheet
Address
0x7
Default
0x0000
AD5560
Data Bits, MSB First
Bit
Name
6
5
Test Force
AMP[1:0]
4:0
Reserved
Function
24
25
26
Force amplifier
NPNs
1A-1
1A-2
2A (similar location to VPTAT high for EXTFORCE2
range)
1B-1 (similar location to VPTAT high for EXTFORCE1
27
range)
28
1B-2
29
2B
30
1C-1
31
1C-2
These register bits allow disabling of stages of the force amplifier. They can be used to ensure connectivity in
each parallel stage. The enabled stage depends also on which current range is selected.
Test Force
Current Range
Amplifier
Enabled Stage
EXTFORCE1
0
All stages
EXTFORCE1
1
EXTFORCE1C
EXTFORCE1
2
EXTFORCE1B
EXTFORCE1
3
EXTFORCE1A
EXTFORCE2
0
All stages
EXTFORCE2
1
Reserved
EXTFORCE2
2
EXTFORCE2B
EXTFORCE2
3
EXTFORCE2A
Set to 0.
Rev. D | Page 53 of 68
AD5560
Data Sheet
Table 24. Other Registers
Address
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
Register
FIN DAC x1
FIN DAC m
FIN DAC c
Offset DAC x
OSD DAC x
CLL DAC x1
CLL DAC m
CLL DAC c
CLH DAC x1
CLH DAC m
CLH DAC c
CPL DAC x1 5 μA range
CPL DAC m 5 μA range
CPL DAC c 5 μA range
CPL DAC x1 25 μA range
CPL DAC m 25 μA range
CPL DAC c 25 μA range
CPL DAC x1 250 μA range
CPL DAC m 250 μA range
CPL DAC c 250 μA range
CPL DAC x1 2.5 mA range
CPL DAC m 2.5 mA range
CPL DAC c 2.5 mA range
CPL DAC x1 25 mA range
CPL DAC m 25 mA range
CPL DAC c 25 mA range
CPL DAC x1 EXT Range 2
CPL DAC m EXT Range 2
CPL DAC c EXT Range 2
CPL DAC x1 EXT Range 1
CPL DAC m EXT Range 1
CPL DAC c EXT Range 1
CPH DAC x 1 5 μA range
CPH DAC m 5 μA range
CPH DAC c 5 μA range
CPH DAC x1 25 μA range
CPH DAC m 25 mA range
CPH DAC c 25 μA range
CPH DAC x1 250 μA range
CPH DAC m 250 μA range
CPH DAC c 250 μA range
CPH DAC x1 2.5 mA range
CPH DAC m 2.5 mA range
CPH DAC c 2.5 mA range
CPH DAC x1 25 mA range
CPH DAC m 25 mA range
CPH DAC c 25 mA range
CPH DAC x1 EXT Range 2
CPH DAC m EXT Range 2
CPH DAC c EXT Range 2
CPH DAC x1 EXT Range 1
CPH DAC m EXT Range 1
Default
0x8000
0xFFFF
0x8000
0x8000
0x1FFF
0x0000
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0x0000
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
0xFFFF
0xFFFF
Data Bits, MSB First
x1 DAC register; D15 to D0, MSB first.
m register; D15 to D0, MSB first.
c register; D15 to D0, MSB first.
D15 to D0.
D15 to D0.
D15 to D0; the low clamp level can only be negative; the MSB is always 0 to ensure this.
D15 to D0.
D15 to D0.
D15 to D0; the high clamp level can only be positive; the MSB is always 1 to ensure this.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
Rev. D | Page 54 of 68
Data Sheet
AD5560
Address
0x3C
0x3D
0x3E
Register
CPH DAC c EXT Range 1
DGS DAC
Ramp end code
Default
0x8000
0x3333
0x0000
0x3F
Ramp step size
0x0001
0x40
RCLK divider
0x0001
0x41
0x42
Enable ramp
Interrupt ramp
0x0000
0x0000
Data Bits, MSB First
D15 to D0.
D15 to D0 DUTGND SENSE DAC, 0 V to 5 V range.
D15 to D0; this is the ramp end code. The ramp start code is the code that is in the FIN
DAC register.
0000 0000 D6 to D0.
D6:D0 set the ramp step size in increments of 16 LSB per code, with a 5 V reference,
16 LSB = 6.1 mV.
For example,
000 0000 = 16 LSBs (6.1 mV) step
000 0001 = 16 LSBs (6.1 mV) step
…
111 1111 = 2032 LSBs (775 mV) step.
0000 0000 D7 to D0.
D7:D0 set the RCLK divider.
0000 0000 = ÷ 1
0000 0001 = ÷ 1
0000 0010 = ÷ 2
0000 0011 = ÷ 3
…
1111 1111 = ÷ 255
0xFFFF to enable.
0x0000 to interrupt.
Rev. D | Page 55 of 68
AD5560
Data Sheet
Table 25. Alarm Status and Clear Alarm Status Register
Address
0x43
Register
Alarm status
Default
0x0000
0x44
Alarm status
and clear alarm
0x0000
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B to
0x7F
CPL DAC x1
CPL DAC m
CPL DAC c
CPH DAC x1
CPH DAC m
CPH DAC c
Reserved
0x0000
0xFFFF
0x8000
0xFFFF
0xFFFF
0x8000
Data Bits, MSB first
This register is a read-only register providing information on the status of the alarm functions and
the comparator outputs.
Bit
Name
Function
15
LTMPALM Latched temperature alarm bit; if low, this bit indicates that an alarm event has
occurred.
14
Unlatched alarm bit; if low, these bit indicates that an alarm event is still
TMPALM
present.
13
Latched open-sense alarm bit; if low, indicates that an alarm event has
LOSALM
occurred.
12
Unlatched open-sense alarm bit; if low, indicates that an alarm event is still
OSALM
present.
11
LDUTALM Latched DUTGND Kelvin sense alarm; if low, indicates that an alarm event has
occurred.
10
Unlatched DUTGND Kelvin sense alarm; if low, indicates that an alarm event is still
DUTALM
present.
9
Latched clamp alarm; if low, indicates that an alarm event has occurred.
LCLALM
8
Unlatched clamp alarm; if low, indicates that an alarm event is still present.
CLALM
7
LGRDALM Latched guard alarm; if low, indicates that an alarm event has occurred.
6
Unlatched guard alarm; if low, indicates that an alarm event is still present.
GRDALM
5
CPOL
Comparator output low condition as per the comparator output pin.
4
CPOH
Comparator output high condition as per the comparator output pin.
3:0
Unused
Must be zeros.
This register is a read-only register providing information on the status of the alarm functions and
the comparator outputs. Reading this register also automatically clears any latched alarm pins or bits.
Bit
Name
Function
15
LTMPALM Latched temperature alarm bit; if low, this bit indicates that an alarm event has
occurred.
14
Unlatched alarm bit; if low, these bit indicates that an alarm event is still
TMPALM
present.
13
Latched open-sense alarm bit; if low, indicates that an alarm event has
LOSALM
occurred.
12
Unlatched open-sense alarm bit; if low, indicates that an alarm event is still
OSALM
present.
11
LDUTALM Latched DUTGND Kelvin sense alarm; if low, indicates that an alarm event has
occurred.
10
Unlatched DUTGND Kelvin sense alarm; if low, indicates that an alarm event is still
DUTALM
present.
9
Latched clamp alarm; if low, indicates that an alarm event has occurred.
LCLALM
8
Unlatched clamp alarm; if low, indicates that an alarm event is still present.
CLALM
7
LGRDALM Latched guard alarm; if low, indicates that an alarm event has occurred.
6
Unlatched guard alarm; if low, indicates that an alarm event is still present.
GRDALM
5
CPOL
Comparator output low condition as per the comparator output pin.
4
CPOH
Comparator output high condition as per the comparator output pin.
3:0
Unused
Must be zeros.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
D15 to D0.
Reserved.
Rev. D | Page 56 of 68
Data Sheet
AD5560
READBACK MODE
DAC READBACK
The AD5560 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the DAC register (x2 calibrated register). To
read back contents of a register, it is necessary to write a 1 to
the R/W bit, address the appropriate register, and fill the data
bits with all zeros.
The DAC x1, DAC m, and DAC c registers are available to read
back via the serial interface. Access to the calibrated x2 register
is not available.
After the write command has been written, data from the
selected register is loaded to the internal shift register and is
available on the SDO pin during the next SPI operation.
Address 0x43 and Address 0x44 are the only registers that are
read only. The read function gives the user details of the alarm
status and the comparator output result.
Alarm flags on latched alarm pins (Pin 1, Pin 2, Pin 3) and bits
are cleared after a read command of Register 0x44 (alarm status
and clear alarm register (see Table 25)).
SCLK frequency for readback does not operate at the full speed
of the SPI interface. See the Timing Characteristics section for
further details.
POWER-ON DEFAULT
During power-on, the power-on state machine resets all internal
registers to their default values, and BUSY goes low. A rising
edge on BUSY indicates that the power-on event is complete
and that the interface is enabled. The RESET pin has no
function in the power-on event.
During power-on, all DAC x1 registers corresponding to 0 V
are cleared; the calibration register default corresponds to m at
full scale and to c at zero scale.
The default conditions of the DPS and the system control
registers are as shown in the relevant tables (see Table 17
through Table 26).
During a RESET function, all registers are reset to the power-on
default.
Rev. D | Page 57 of 68
AD5560
Data Sheet
Table 26. AD5560 Truth Table of Switches 1
Reg
System
Control
Register
DPS Register 1
Bit Name
Gain0,
Gain1
Bit
SW1
X
SW2
X
SW3
X
SW4
X
SW7
X
SW13
X
SW14
X
SW15
X
SW5
X
SW6
X
SW8
X
SW9
X
SW11
X
SW16
X
FINGND
0
B
X
X
X
X
X
X
X
X
X
X
X
X
X
1
A
X
X
X
X
X
X
X
X
X
X
X
X
X
CPO
X
X
X
X
X
X
X
X
X
X
X
X
X
X
PD 2, 3
X
X
X
X
X
X
X
X
X
X
X
X
X
On
04
15
000
X
X
X
c
a
X
X
X
X
X
X
On
X
X
On
X
X
Off
X
X
Off
X
X
Off
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
001
X
X
X
On
On
Off
Off
Off
X
X
X
X
X
X
010
X
X
X
On
On
Off
Off
Off
X
X
X
X
X
X
011
X
X
X
On
On
Off
Off
Off
X
X
X
X
X
X
100
X
X
X
On
On
Off
Off
Off
X
X
X
X
X
X
101
X
X
X
Off
Off
Off
On
On
X
X
X
X
X
X
110
X
X
X
Off
Off
On
Off
On
X
X
X
X
X
X
00
X
X
X
X
X
X
X
X
X
X
X
X
X
X
01
X
X
X
X
X
X
X
X
X
X
X
X
X
X
10
X
X
a
X
X
X
X
X
X
X
X
X
X
X
11
X
X
b
X
X
X
X
X
X
X
X
X
X
X
000
X
X
X
X
X
X
X
X
X
X
X
X
X
Off
001
X
X
X
X
X
X
X
X
X
X
X
X
X
On
010
X
X
X
X
X
X
X
X
X
X
X
X
X
On
011
X
X
X
X
X
X
X
X
X
X
X
X
X
On
100
X
X
X
X
X
X
X
X
X
X
X
X
X
On
101
X
X
X
X
X
X
X
X
X
X
X
X
X
On
110
X
X
X
X
X
X
X
X
X
X
X
X
X
On
111
X
X
X
X
X
X
X
X
X
X
X
X
X
On
SW-INH2
I2, I1, I0
CMP1, CMP0
ME3, ME2,
ME1, ME0
DPS Register 2
SF0
Slave,
GANGIMODE
0
X
X
X
X
X
X
X
X
X
X
Off
Off
X
X
1
X
X
X
X
X
X
X
X
X
X
On
On
X
X
00 6
b
a
X
X
X
X
X
X
a
Off
X
X
X
X
01 7
b
a
X
X
X
X
X
X
b
Off
X
X
X
X
8
c
c
X
X
X
X
X
X
Off
On
X
X
X
X
11 9
0
c
X
b
X
X
X
X
X
X
X
X
X
X
X
X
X
Off
X
On
X
X
X
X
X
X
Off
X
X
1
X
10
INT10K
Hardware Pins
1
2
3
4
5
X
X
X
X
X
X
X
X
X
X
X
X
On
HW_INH2
X
c
X
X
X
X
X
X
X
X
X
X
X
X
CLEN
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X = don’t care; the switch is unaffected by the particular bit condition.
Active low.
Power-down mode; used for low power consumption.
Force amplifier outputs tristate, low leakage mode; feedback made around amplifier.
FV mode.
Master: MASTER_OUT = internally connects to active EXTFORCE1/EXTFORCE2/25 mA output.
Master: MASTER_OUT = master MI.
8
Slave FV: EXTFORCE1/EXTFORCE2/25 mA connected internally to close the FVAMP loop.
9
Slave FI.
6
7
Rev. D | Page 58 of 68
Data Sheet
AD5560
USING THE HCAVDDx AND HCAVSSx SUPPLIES
internal pull-up resistors between the supplies (see Figure 59).
Using diodes here allows a more flexible use of supplies and
can minimize the amount of supply switching required. In the
example, the AVDD and AVSS supplies can support the high
voltage needs, whereas the HCAVDDx and HCAVSSx supplies
support the low voltage, higher current ranges. Diode selection
should take into account the current carrying requirements.
Supply selection for HCAVDDx and HCAVSSx supplies must
allow for this extra voltage drop.
The first set of power supplies, AVDD and AVSS, provide power
to the DAC levels and associated circuitry. They also supply the
force amplifier stage for the low current ranges (ranges using
internal sense resistors up to 25 mA maximum).
The second set of power supplies, HCAVSS1 and HCAVDD1,
are intended to be used to minimize power consumption in
the AD5560 device for the EXTFORCE1 range (up to ±1.2 A).
Similarly, the HCAVSS2 and HCAVDD2 supplies are used for the
EXTFORCE2 range (up to ±500 mA). These supplies must be
less than or equal to the AVDD and AVSS supplies. When driving
high currents at low voltages, power can be greatly minimized
by ensuring that the supplies are at the lowest voltages.
POWER SUPPLY SEQUENCING
When the supplies are connected to the AD5560, it is important
that the AGND and DGND pins be connected to the relevant
ground plane before the positive or negative supplies are applied.
In most applications, this is not an issue because the ground
pins for the power supplies are connected to the ground pins of
the AD5560 via ground planes. The AVDD and AVSS supplies
must be applied to the device either before or at the same time
as the HCAVDDx and HCAVSSx supplies, as indicated in Table 3.
There are no known supply sequences surrounding the DVCC
supply, although it is recommended that it be applied as
indicated by the absolute maximum ratings (see Table 3).
Therefore, HCAVSSx and HCAVDDx can be switched externally
to different power rails as required by the set voltage range.
However, the design of the high current output stage means
that these supplies always have to be at a higher voltage than
the forced voltage, irrespective of the current range being used.
Therefore, depending on the level of supply switching, external
diodes may be required in series with each of the HCAVDDx
and HCAVSSx supplies, as shown in Figure 59. There are
DVCC = 3V/5V
10µF
10µF
10µF
10µF
+
+
+
+
10µF
HCAV DD2 = +9V
HCAV DD1 = +6V
+
10µF
HCAV SS2 = –5V
HCAV SS1 = –5V
AVDD = +28V
+
AVSS = –5V
+
0.1µF
100kΩ
33kΩ
0.1µF
0.1µF
0.1µF
+
+
+
+
0.1µF
+
0.1µF
+
0.1µF
100kΩ
33kΩ
3. MIDCURRENT
RANGE
500mA
RANGE
ALLOW ±0.5V
FOR EXT RSENSE
EXTFORCE2
DUT RANGE
0V TO +6V
2. HIGHEST CURRENT
RANGE
OUTPUT RANGE
–0.2V TO +6.5V
1200mA
RANGE
1. LOW CURRENT,
HIGH VOLTAGE
ALLOW ±0.5V FOR EXT RSENSE
EXTFORCE1
DUT RANGE
–2V TO +3V
OUTPUT RANGE
–2.5V TO +3.5V
INTERNAL RANGE SELECT
(5µA, 25µA, 250µA, 2.5mA, 25mA)
AD5560
Figure 59. Example of Using the Extra Supply Rails Within the AD5560 to Achieve Multiple Voltage/Current Ranges
Rev. D | Page 59 of 68
FORCE
DUT RANGE
0V TO +25V
07779-012
INTERNAL RSENSE
±0.5V AT FULL CURRENT
OUTPUT RANGE
0V TO +25V
AD5560
Data Sheet
five feedforward capacitor input pins, all capacitor inputs may
be used only if the user intends to drive large variations of DUT
load capacitances. If the DUT load capacitance is known and
doesn’t change for all combinations of voltage ranges and test
conditions, then it is possible only one set of CCx and CFx is
required.
REQUIRED EXTERNAL COMPONENTS
The minimum required external components are shown in the
block diagram in Figure 60. Decoupling is very dependent on
the type of supplies used, the board layout, and the noise in the
system. It is possible that less decoupling may be required as a
result. Although there are four compensation input pins and
HCAV DD1
+
10µF
0.1µF
0.1µF
0.1µF
+
+
+
0.1µF
+
+
+
DVCC
0.1µF
+
AVDD
0.1µF
+
+
AVSS
10µF
+
+
0.1µF
10µF
HCAV DD2
REF
DVCC
0.1µF
10µF
+
SHARED
REFERENCE
10µF
10µF
DVCC OR
OTHER
DIGITAL
SUPPLY
HCAV SS2
HCAV SS1
AVDD
+
AVSS
CC0 CC1 CC2 CC3
VREF
RPULLUP
EXTFORCE1
EXTFORCE2
CLALM
KELALM
CF0
TMPALM
CF1
CF2
DVCC OR
OTHER
DIGITAL
SUPPLY
CF3
CF4
RPULLUP
RESET
FORCE
SENSE
EXTMEASHI1
EXTMEASHI2
RSENSE 1
EXTMEASIL
RSENSE 2
VREF
ADC
ADC
DRIVER
MEASOUT
DUT
DUTGND
07779-013
SHARED
ADC
Figure 60. External Components Required for Use with the DPS
Table 27. References Suggested for Use with the AD5560 1
Part No.
ADR431
ADR435
ADR441
ADR445
1
Voltage (V)
2.5
5
2.5
5
Initial
Accuracy %
±0.04
±0.04
±0.04
±0.04
Ref Out Tempco
(ppm/°C max)
A/B Grade
10/3
10/3
10/3
10/3
Ref Output
Current (mA)
30
30
10
10
Supply Voltage
Range (V)
4.5 to 18
7 to 18
3 to 18
5.5 to 18
Subset of the possible references suitable for use with the AD5560. See www.analog.com/references for more options.
Rev. D | Page 60 of 68
Package
MSOP, SOIC
MSOP, SOIC
MSOP, SOIC
MSOP, SOIC
Data Sheet
AD5560
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps
to ensure the rated performance. The printed circuit board
on which the AD5560 is mounted should be designed so that
the analog and digital sections are separated and confined to
certain areas of the board. If the AD5560 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
The DGND connection in the AD5560 should be treated as
AGND and returned to the AGND plane. For more detail on
decoupling for mixed signal applications, refer to Analog
Devices Tutorial MT 031.
For supplies with multiple pins (AVSS, AVDD, DVCC), it is
recommended to tie these pins together and to decouple
each supply once.
The AD5560 should have ample supply decoupling of 10 µF
in parallel with 0.1 µF on each supply located as close to the
part as possible, ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and effective
series inductance (ESL), such as the common ceramic capacitors that provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
Digital lines running under the device should be avoided because
these couple noise onto the device. The analog ground plane
should be allowed to run under the AD5560 to avoid noise
coupling. The power supply lines of the AD5560 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching digital signals should be shielded with digital ground
to avoid radiating noise to other parts of the board and should
never be run near the reference inputs. It is essential to
minimize noise on all VREF lines. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feedthrough throughout the board. As is the case for all thin
packages, care must be taken to avoid flexing the package and
to avoid a point load on the surface of this package during the
assembly process.
Also note that the exposed paddle of the AD5560 is internally
connected to the negative supply AVSS.
Rev. D | Page 61 of 68
AD5560
Data Sheet
APPLICATIONS INFORMATION
THERMAL CONSIDERATIONS
Table 28. Thermal Resistance for TQFP_EP1
Cooling
No Heat Sink
Heat Sink7
Cold Plate8
Airflow (LFPM)
0
200
500
0
200
500
N/A
θJA2
39
37.2
35.7
12.2
11.1
9.5
N/A
θJC (Uniform)3
θJC (Local)4
Ideal TIM6
θJC (Local)
w/TIM6
1.0
2.8
4.91
1.0
2.8
4.91
θJCP
w/TIM5
N/A
N/A
7.5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
All numbers are simulated and assume a JEDEC 4-layer test board.
θJA is the thermal resistance from hottest junction to ambient air.
3
θJC (Uniform) is the thermal resistance from junction to the package top, assuming total power is uniformly distributed.
4
θJC (Local) is the thermal resistance from junction to the center of package top, assuming total power = 8.5 W (1 W uniformly distributed, 7.5 W in power stages—local
heating).
5
θJCP is the thermal resistance from hottest junction to infinite cold plate with consideration of thermal interface material (TIM).
6
Ideal TIM is assuming top of package in perfect contact with an infinite cold plate. w/TIM is assuming TIM is 0.5 mm thick, with thermal conductivity of 2.56 W/m/k.
7
Heat sink with a rated performance of θCA ~5.3°C/W under forced convection, gives ~TJ = 111°C at 500 LFM. Thermal performance of the package depends on the heat
sink and environmental conditions.
8
Attached infinite cold plate should be ≤26°C to maintain TJ < 90°C, given total power = 8.5 W. Thermal performance of the package depends on the heat sink and
environmental conditions.
9
To estimate junction temperature, the following equations can be used:
TJ = Tamb + θJA × Power
TJ = Tcold plate + θJCP × Power
TJ = Ttop + θJC × Power
2
Table 29. Thermal Resistance for Flip Chip BGA1
Cooling
No Heat Sink
Heat Sink8
Cold Plate9
Airflow (LFPM)
0
200
500
0
200
500
N/A
2
JA
θ
40.8
38.1
36
18
11.8
9
N/A
θJC (Local)4
Ideal TIM6
θJC (Local)
w/TIM6
0.05
1.6
4.6
0.05
1.6
4.6
θ
3
JC (Uniform)
θJCP5
w/TIM
N/A
N/A
1
6.5
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
All numbers are simulated and assume a JEDEC 4-layer test board.
θJA is the thermal resistance from hottest junction to ambient air.
θJC (Uniform) is the thermal resistance from junction to the package top, assuming total power is uniformly distributed.
4
θJC (Local) is the thermal resistance from junction to the center of package top, assuming total power = 8.5 W (1 W uniformly distributed, 7.5 W in power stages—local
heating).
5
θJCP is the thermal resistance from hottest junction to infinite cold plate with consideration of thermal interface material (TIM).
6
Ideal TIM is assuming top of package in perfect contact with an infinite cold plate. w/TIM is assuming TIM is 0.4 mm thick, with thermal conductivity of 3.57 W/m/k.
7
Heat sink with a rated performance of θCA ~4.9°C/W under forced convection, gives ~TJ = 112°C at 500 LFM. Thermal performance of the package depends on the heat
sink and environmental conditions.
8
Attached infinite cold plate should be ≤30°C to maintain TJ < 90°C, given total power = 8.5 W. Thermal performance of the package depends on the heat sink and
environmental conditions.
9
To estimate junction temperature, the following equations can be used:
TJ = Tamb + θJA × Power
TJ = Tcold plate + θJCP × Power
TJ = Ttop + θJC × Power
2
3
Rev. D | Page 62 of 68
Data Sheet
AD5560
TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE
BGA Package
Due to localized heating, temperature at the top surface of
the package has steep gradient. Thus, the θJC value is highly
dependent on where the case temperature is measured.
Figure 61 shows the top of the die temperature contour map
for the TQFP_EP.
Due to localized heating, temperature at the top surface of
the package has steep gradient. Thus, the θJC value is highly
dependent on where the case temperature is measured.
Figure 62 shows the top of the die temperature contour map
for the flip chip BGA.
07779-064
TQFP_EP Package
07779-065
Figure 61. Temperature Contour Map for 64-Lead TQFP_EP
Figure 62. Temperature Contour Map for the Flip Chip BGA
Rev. D | Page 63 of 68
AD5560
Data Sheet
OUTLINE DIMENSIONS
1.20
MAX
0.75
0.60
0.45
12.20
12.00 SQ
11.80
0.675
0.872
5.95 BSC
64
49
1
1.00 REF
49
48
64
1
48
SEATING
PLANE
EXPOSED
PAD
5.95
BSC
10.20
10.00 SQ
9.80
7.85
BSC
TOP VIEW
(PINS DOWN)
0.15
0.05
0.08
COPLANARITY
BOTTOM VIEW
16
0.20
0.09
33
17
7°
3.5°
0°
VIEW A
32
16
17
32
7.85
BSC
0.27
0.22
0.17
0.50
BSC
LEAD PITCH
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
VIEW A
(PINS UP)
33
10-19-2011-C
1.05
1.00
0.95
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ACD-HU
Figure 63. 64-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-64-3)
Dimensions shown in millimeters
8.10
8.00 SQ
7.90
5.720 REF
A1 BALL
CORNER
0.40 REF
A1 BALL
CORNER
(DIE OFFSET)
9
8
7
6
5
4
3
2
1
A
B
C
6.865 REF
6.40
BSC SQ
D
E
F
G
0.80
BSC
H
J
0.80
REF
*1.20
1.08
1.00
BOTTOM VIEW
DETAIL A
DETAIL A
0.36
REF
0.39
0.34
0.29
SEATING
PLANE
0.50
0.45
0.40
BALL DIAMETER
*COMPLIANT TO JEDEC STANDARDS MO-225 WITH
EXCEPTION TO PACKAGE HEIGHT.
Figure 64. 72-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-72-2)
Dimensions shown in millimeters
Rev. D | Page 64 of 68
0.81
0.76
0.71
COPLANARITY
0.12
04-19-2012-B
TOP VIEW
Data Sheet
AD5560
ORDERING GUIDE
Model 1
AD5560JSVUZ
AD5560JSVUZ-REEL
AD5560JBCZ
AD5560JBCZ-REEL
EVAL-AD5560EBUZ
1
2
Temperature Range 2
TJ = 25°C to +90oC
TJ = 25°C to +90oC
TJ = 25°C to +90oC
TJ = 25°C to +90oC
Package Description
64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP)
64-Lead Thin Quad Flat Pack with Exposed Pad (TQFP_EP)
72-Ball Chip Scale Package Ball Grid Array (CSP-BGA)
72-Ball Chip Scale Package Ball Grid Array (CSP-BGA)
Evaluation Kit
Z = RoHS Compliant Part.
TJ = junction temperature.
Rev. D | Page 65 of 68
Package Option
SV-64-3
SV-64-3
BC-72-2
BC-72-2
AD5560
Data Sheet
NOTES
Rev. D | Page 66 of 68
Data Sheet
AD5560
NOTES
Rev. D | Page 67 of 68
AD5560
Data Sheet
NOTES
©2008-2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07779-0-8/12(D)
Rev. D | Page 68 of 68