M ICROWAVE A Division of Crystek Corporation CPLL58-4160-4380 0.582" × 0.800" SMD Features 4.160GHz-4.380GHz Standard 3 Wire Interface Small layout 0.582" × 0.8" Applications Digital Radio Equipment Fixed Wireless Access Satellite Communications Systems Base Stations Personal Communications Systems Portable Radios Test Instruments Wireless Infrastructure The CPLL58 is a complete PLL/Synthesizer needing only an external frequency reference and supply voltages for the internal PLL (phase lock loop) and VCO (voltage controlled oscillator). The Crystek CPLL58 is programmed using a standard three line interface (Data, Clock and Load Enable). The CPLL58 family has been initially released to cover 1GHz to 5GHz in bands. It is housed in a compact 0.582-in. × 0.8-in. × 0.15-in. SMD package which saves board space. Typical phase noise at 4GHz is -90dBc/Hz at 10KHz offset with 0dBm minimum output power. Rev A Page 1 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M ICROWAVE A Division of Crystek Corporation PERFORMANCE SPECIFICATION Frequency Range: Step Size: Settling Time, to within ± 1kHz (Freq. step < 25MHz): Output Power: Output Phase Noise: (See Plot Below) @1KHz offset @10KHz offset @100KHz offset @1MHz offset Power Supply: V1=VCO Supply V2=PLL Supply Supply Current: I1=VCO Input Current I2=PLL Input Current Spurious Suppression PFDSpur Reference Feedthru Harmonic Suppression (2nd Harmonic): 2nd Reference Frequency RF Output Level Input Impedance RF Output Impedance Operating Temperature Range: CPLL58-4160-4380 0.582" × 0.800" SMD MIN 4.160 0 4.75 2.7 TYP MAX 4.380 2500 1 +3.0 +6.0 UNITS GHz KHz msec dBm -80 -90 -90 -125 -75 -85 -85 -130 dBc/Hz dBc/Hz dBc/Hz dBc/Hz 5.0 3.0 5.25 3.3 Volts Volts -70 -80 -60 -70 mA mA dBc dBc dBc -15 10 0 100K 50 -10 50 25 -5 -40 +5 +85 dBc MHz dBm Ohm Ohm °C Page 2 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M ICROWAVE A Division of Crystek Corporation 0.582" × 0.800" SMD GND V1 GND REF GND 0.00 V2 [Pin1] BOTTOM VIEW 0.200 0.280 0.360 0.440 0.520 0.600 0.00 GND 0.331 GND GND 0.411 GND GND CLK LE 0.582 LE = Load Enable, CMOS Input DATA = Serial Data Input CLK = Clock LD = Lock Detect REF = Reference Input V1 = Analog Supply Input (VCO) V2 = Digital Supply Input (PLL) RF = RF Output RF GND GND GND GND 0.251 LD 0.171 DATA CRYSTEK CPLL58 4160-4380 YYWW TOP ORIENTATION MARK 0.052 0.150 0.000 0.052 0.000 0.000 Pad Detail RECOMMENDED REFLOW SOLDERING PROFILE Ramp-Up 3°C/Sec Max. Critical Temperature Zone 260°C TEMPERATURE 0.600 TOP VIEW CPLL58-4160-4380 Ramp-Down 6°C/Sec. 217°C 200°C 150°C Preheat 180 Secs. Max. 90 Secs. Max. 8 Minutes Max. 260°C for 10 Secs. Max. Page 3 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M ICROWAVE A Division of Crystek Corporation CPLL58-4160-4380 0.582" × 0.800" SMD ENVIRONMENTAL COMPLIANCE Parameter Conditions Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 1014 Resistance to Solvents MIL-STD-883, Method 2016 Programming Guide for CPLL58-XXXX Introduction The CPLL58 uses a simple 3 wire interface to program four internal registers. See Figure 1. t3 t4 CLOCK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1(CONTROL BIT C2) DB0(LSB) (CONTROL BIT C1) t6 LE t5 LE Figure 1. Timing Diagram There are four 24 bit registers that need to be programmed. Which register is written into is simply controlled by Control Bits C1 and C2. Table I summarizes the Truth Table for Control Bits C1 and C2. Control Bits C2 C1 Data Latch 0 0 R Counter 0 1 N Counter (A and B) 1 0 Function Latch (Including Prescaler) 1 1 Initialization Latch Table I. C2, C1 Truth Table Page 4 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M ICROWAVE A Division of Crystek Corporation CPLL58-4160-4380 0.582" × 0.800" SMD Table II shows the details of the four 24 bit registers. LOCK DETECT PRECISION REFERENCE COUNTER LATCH RESERVED TEST MODE BITS ANTIBACKLASH WIDTH CONTROL BITS 14-BIT REFERENCE COUNTER DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X 0 0 LDP T2 T1 ABP2 ABP1 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 C2(0) C1(0) CP GAIN N COUNTER LATCH RESERVED DB23 DB22 13-BIT COUNTER CONTROL BITS 6-BIT COUNTER DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 G1 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 A6 A5 A4 A3 A2 A1 C2(0) C1(1) MUXOUT CONTROL FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PD POLARITY POWER-DOWN 1 COUNTER RESET POWER-DOWN 2 FUNCTION LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P2 P1 PD2 CP16 CP15 CP14 CP13 CP12 CP11 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2(1) C1(0) PRESCALER VALUE CURRENT SETTING2 CURRENT SETTING 1 TIMER COUNTER CONTROL CONTROL BITS FASTLOCK MODE FASTLOCK ENABLE CP THREESTATE PD POLARITY POWER-DOWN 1 COUNTER RESET POWER-DOWN 2 INITIALIZATION LATCH DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 P2 P1 PD2 CP16 CP15 CP14 CP13 CP12 CP11 TC4 TC3 TC2 TC1 F5 F4 F3 F2 M3 M2 M1 PD1 F1 C2(1) C1(1) PRESCALER VALUE CURRENT SETTING2 CURRENT SETTING 1 TIMER COUNTER CONTROL MUXOUT CONTROL CONTROL BITS Table II. Latch Summary When using the CPLL58 family in a synthesizer application, all four 24 bit registers need to be written into after power-up. After writing all four latches the first time, subsequent frequency step changes can be accomplished by changing the N Counter Latch only. Specifications subject to change without notice. Page 5 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com M ICROWAVE A Division of Crystek Corporation CPLL58-4160-4380 0.582" × 0.800" SMD Programming Crystek p/n: CPLL58-4160-4380 The following is specific programming for CPLL58-4160-4380 (4.160GHz-4.380GHz with 2500KHz Step Size and 10MHz input reference frequency). Program all four registers with the following: R Counter Latch: 000010 H N Counter Latch: 003401 H Function Latch: 9F8083 H The above values will set the CPLL58-4160-4380 to 4.160GHz Page 6 of 6 CRYSTEK CORPORATION 12730 Commonwealth Drive • Fort Myers, Florida 33913 Phone: 239-561-3311 • 800-237-3061 Fax: 239-561-1025 • www.crystek.com