ON MC74VHC14DT Hex schmitt inverter Datasheet

MC74VHC14
Hex Schmitt Inverter
The MC74VHC14 is an advanced high speed CMOS Schmitt
inverter fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
Pin configuration and function are the same as the MC74VHC04 but
the inputs have hysteresis and, with its Schmitt trigger function, the
VHC14 can be used as a line receiver which will receive slow input
signals.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
•
•
•
•
•
•
•
•
•
•
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MARKING
DIAGRAMS
14
SOIC−14
D SUFFIX
CASE 751A
VHC14G
AWLYWW
1
High Speed: tPD = 5.5 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2.0 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
14
Power Down Protection Provided on Inputs
VHC
14
ALYW TSSOP
DT SUFFIX
CASE 948G
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
1
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
A
= Assembly Location
WL, L = Wafer Lot
Y
= Year
WW, W = Work Week
G or = Pb−Free Package
(Note: Microdot may be in either location)
Latchup Performance Exceeds 300 mA
ESD Performance: Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 60 FETs or 15 Equivalent Gates
•
• Pb−Free Packages are Available
FUNCTION TABLE
VCC
A6
Y6
A5
Y5
A4
Y4
Inputs
Outputs
14
13
12
11
10
9
8
A
Y
L
H
H
L
1
2
3
4
5
6
7
ORDERING INFORMATION
A1
Y1
A2
Y2
A3
Y3
GND
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 1. 14−Lead Pinout (Top View)
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 9
1
Publication Order Number:
MC74VHC14/D
MC74VHC14
A1
A2
A3
1
2
3
4
5
6
9
8
11
10
13
12
Y1
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
Y2
Y3
Y=A
A4
A5
A6
Y4
Y5
Y6
Figure 2. Logic Diagram
MAXIMUM RATINGS
Symbol
Parameter
VCC
Positive DC Supply Voltage
Value
Unit
−0.5 to +7.0
V
VIN
Digital Input Voltage
−0.5 to +7.0
V
VOUT
DC Output Voltage
−0.5 to VCC +0.5
V
IIK
Input Diode Current
−20
mA
IOK
Output Diode Current
$20
mA
IOUT
DC Output Current, per Pin
$25
mA
ICC
DC Supply Current, VCC and GND Pins
$75
mA
PD
Power Dissipation in Still Air
200
180
mW
TSTG
Storage Temperature Range
−65 to +150
°C
VESD
ESD Withstand Voltage
Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>2000
>200
N/A
V
Above VCC and Below GND at 125°C (Note 4)
$300
mA
143
164
°C/W
ILATCHUP
qJA
SOIC
TSSOP
Latchup Performance
Thermal Resistance, Junction−to−Ambient
SOIC
TSSOP
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
1. Tested to EIA/JESD22−A114−A.
2. Tested to EIA/JESD22−A115−A.
3. Tested to JESD22−C101−A.
4. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Characteristics
Min
Max
Unit
VCC
DC Supply Voltage
2.0
5.5
V
VIN
DC Input Voltage
0
5.5
V
DC Output Voltage
0
VCC
V
VOUT
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise or Fall Time
VCC = 3.3 V + 0.3 V
VCC = 5.0 V + 0.5 V
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2
−55
125
°C
−
−
No limit
No limit
ns/V
MC74VHC14
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DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VCC
V
Test Conditions
VT+
Positive Threshold
Voltage (Figure 5)
3.0
4.5
5.5
VT−
Negative Threshold
Voltage (Figure 5)
3.0
4.5
6.0
0.9
1.35
1.65
VH
Hysteresis Voltage
(Figure 5)
3.0
4.5
5.5
0.30
0.40
0.50
2.0
3.0
4.5
1.9
2.9
4.4
3.0
4.5
2.58
3.94
VOH
Minimum High−Level
Output Voltage
Vin = VIH or VIL
IOH = − 50 mA
−55°C ≤ TA ≤ 125°C
TA = 25°C
Min
Typ
Max
Min
2.20
3.15
3.85
Max
Unit
2.20
3.15
3.85
V
0.90
1.35
1.65
1.20
1.40
1.60
V
0.30
0.40
0.50
2.0
3.0
4.5
1.20
1.40
1.60
V
V
1.9
2.9
4.4
Vin = VIH or VIL
IOH = − 4 mA
IOH = − 8 mA
VOL
Maximum Low−Level
Output Voltage
Vin = VIH or VIL
IOL = 50 mA
2.48
3.80
2.0
3.0
4.5
0.0
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
3.0
4.5
0.36
0.36
0.44
0.44
V
Vin = VIH or VIL
IOL = 4 mA
IOL = 8 mA
Iin
Maximum Input
Leakage Current
Vin = 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
mA
ICC
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
2.0
20.0
mA
AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
−55°C ≤ TA ≤ 125°C
TA = 25°C
Symbol
Parameter
tPLH,
tPHL
Maximum Propagation
Delay,
A or B to Y
Cin
Min
Test Conditions
Typ
Max
Min
Max
Unit
ns
VCC = 3.3 ± 0.3 V
CL = 15 pF
CL = 50 pF
8.3
10.8
12.8
16.3
1.0
1.0
15.0
18.5
VCC = 5.0 ± 0.5 V
CL = 15 pF
CL = 50 pF
5.5
7.0
8.6
10.6
1.0
1.0
10.0
12.0
4
10
Maximum Input
Capacitance
10
pF
Typical @ 25°C, VCC = 5.0 V
CPD
21
Power Dissipation Capacitance (Note 5)
pF
5. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 6 (per buffer). CPD is used to determine the
no−load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
NOISE CHARACTERISTICS (Input tr = tf = 3.0 ns, CL = 50 pF, VCC = 5.0 V)
TA = 25°C
Typ
Max
Unit
VOLP
Quiet Output Maximum Dynamic VOL
0.4
0.8
V
VOLV
Quiet Output Minimum Dynamic VOL
−0.4
−0.8
V
VIHD
Minimum High Level Dynamic Input Voltage
3.5
V
VILD
Maximum Low Level Dynamic Input Voltage
1.5
V
Symbol
Characteristic
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3
MC74VHC14
TEST POINT
VCC
A
OUTPUT
50%
DEVICE
UNDER
TEST
GND
tPLH
tPHL
CL*
50% VCC
Y
*Includes all probe and jig capacitance
V T , TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS)
Figure 3. Switching Waveforms
Figure 4. Test Circuit
4
3
(VT+)
VHtyp
2
(VT−)
1
2
3
4
5
6
VCC, POWER SUPPLY VOLTAGE (VOLTS)
VHtyp = (VT+ typ) − (VT− typ)
Figure 5. Typical Input Threshold, VT+, VT− versus Power Supply Voltage
VCC
VH
VT+
VT−
Vin
VCC
VH
VT+
VT−
Vin
GND
GND
VOH
VOH
Vout
Vout
VOL
VOL
(a) A Schmitt−Trigger Squares Up
Inputs With Slow Rise and Fall Times
(b) A Schmitt−Trigger Offers Maximum
Noise Immunity
Figure 6. Typical Schmitt−Trigger Applications
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4
MC74VHC14
ORDERING INFORMATION
Package
Shipping †
MC74VHC14D
SOIC−14
55 Units / Rail
MC74VHC14DG
SOIC−14
(Pb−Free)
55 Units / Rail
MC74VHC14DR2
SOIC−14
2500 / Tape & Reel
MC74VHC14DR2G
SOIC−14
(Pb−Free)
2500 / Tape & Reel
MC74VHC14DT
TSSOP−14*
96 Units / Rail
MC74VHC14DTG
TSSOP−14*
96 Units / Rail
MC74VHC14DTR2
TSSOP−14*
2500 / Tape & Reel
MC74VHC14DTR2G
TSSOP−14*
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb−Free.
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5
MC74VHC14
PACKAGE DIMENSIONS
SOIC−14
D SUFFIX
CASE 751A−03
ISSUE G
−A−
14
8
−B−
P 7 PL
0.25 (0.010)
M
B
M
7
1
G
F
R X 45 C
−T−
SEATING
PLANE
D 14 PL
0.25 (0.010)
M
T B
J
M
K
S
A
S
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6
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
7
0.228 0.244
0.010 0.019
MC74VHC14
PACKAGE DIMENSIONS
TSSOP−14
DT SUFFIX
CASE 948G−01
ISSUE A
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K1
J J1
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
G
H
DETAIL E
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0
8
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC14/D
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