Holtek HT37B50 Ht37b90 Datasheet

HT37B90/HT37B70/HT37B50/HT37B30
8-Channel Music Synthesizer 8-Bit MCU MCU
Note that the HT37B70/HT37B50/HT37B30 devices, although mentioned in this
datasheet, have already been phased out and are presently no longer available.
Features
· Integrated 2-ch stereo 16-bit DAC converter
· Operating voltage:
2.4V~5.5V for HT37B50/30
3.0V~5.5V for HT37B90/70
· 12-level subroutine nesting
· Integrated power amplifier
· Operating frequency: 12.8MHz
· Integrated 8-channel 12-bit A/D converter
· Oscillation modes for the oscillator clock
· 16 channel polyphonic synthesizer
fOSC: crystal (12.8MHz)
1-pin RC oscillation typ. 12.8MHz
· Low voltage reset (Tolerance ±5%)
· External interrupt INT
· Built-in 8-bit MCU (HT-8) with 640´8 or
· External 2 Timer clock input
1280´8 (HT37B90) bits RAM
· 8 touch switch input
· Built-in 64K´16-bits to 512K´16-bits ROM for
·
·
·
·
·
· ADPCM decoder
program/data shared
Two 8 bit timer and one 16 bit timer
Watchdog timer
Power-down and Wake-up features for power saving
operation
16-bit table read instructions for any bank/page read
Support 32 to 40 bidirectional I/O lines
· IIS function for HT37B90/70
· UART function for HT37B90/70
· SPI function for HT37B90/70
· Bit manipulation instructions
· 63 powerful instructions
· All instructions in 1 or 2 machine cycles
General Description
The device is an 8-bit high performance RISC architecture microcontroller specifically designed for various
Music and ADPCM applications. It provides an 8-bit
MCU and 16-channel wavetable synthesizer. It has a in-
tegrated 8-bit micro controller which controls the synthesizer to generate the melody by setting the special
register. A Power-down function is included to reduce
power consumption.
Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O
count, A/D resolution, DAC output, R2F input and package types. The following table summarizes the main features of
each device.
Part No.
VDD
Channel OSC
HT37B30
Program
ROM
RAM
64K´16
D/A
32
2chStereo
Ö
8
32
2chStereo
Ö
8
2.4V~
5.5V
HT37B50
128K´16
14+2
HT37B70
640´8
12.8
MHz
Rev. 1.00
ADC
IIS
UART
SPI
Package
Types
¾
¾
¾
80LQFP
¾
¾
¾
80LQFP
12-bit´8
256K´16
40
2chStereo
Ö
8
Ö
Ö
Ö
80LQFP
512K´16 1280´8
40
2chStereo
Ö
8
Ö
Ö
Ö
100LQFP
3.0V~
5.5V
HT37B90
Power
CR/F
AMP
I/O
1
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Block Diagram
R O M P ro g ra m
M e m o ry
R A M D a ta
M e m o ry
A /D
C o n v e rts
M id i
E n g in e
C o d e
D /A
C o n v e rts
S ta c k
A D P C M
C o d e
8 - b it
R IS C C o re
S P I
U A R T
I/O
P o rts
IIS
In te g ra te d
P o w e r A m p lifie r
1 6 /8 - b it
T im e r s
R C /C ry s ta l
O s c illa to r
C R /F
W a tc h d o g T im e r
O s c illa to r
W a tc h d o g
T im e r
L o w V o lta g e
R e s e t
In te rru p t
C o n tr o lle r
Pin Assignment
P C 7 /K 7
P D 0 /R C O U T
P D 1 /R R
P D 2 /R C
P D 3 /C C
P D 4 /W A S
P D 5 /D T
P D 6 /C K
P D 7
P B 0 /A D 0
P B 1 /A D 1
P B 2 /A D 2
P B 3 /A D 3
P B 4 /A D 4
P B 5 /A D 5
P B 6 /A D 6
P B 7 /A D 7
V D D _ A D C
V S S _ A D C
N C
P
P
P
P D 0 /R
P D
P
P
P
P
P
P
P
P
V D
V S
P
P
P
B 0
B 1
B 2
B 3
B 4
B 5
B 6
B 7
D _
S _
C 7 /K
C O U
D 1 /R
D 2 /R
D 3 /C
4 /W A
D 5 /D
D 6 /C
P D
/A D
/A D
/A D
/A D
/A D
/A D
/A D
/A D
A D
A D
N
C
C
C
R
C
C
K
S
T
T
0
1
2
3
4
5
6
7
7
7
O S C
O S C
N
N
N
N
N
N
N
N
N
N
N
R E
V S
V D
V S S _ D A
V D D _ D A
L C
R C
8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1
2
1
1
C
2
5 9
3
5 8
C
4
5 7
C
5
5 6
C
6
5 5
C
7
C
1 1
C
1 2
C
S
S
5 2
H T 3 7 B 3 0 /5 0
8 0 L Q F P -A
1 0
C
C
5 3
9
C
D
5 4
8
C
5 1
4 0
4 9
1 3
4 8
4 7
1 4
4 6
1 5
4 5
1 6
4 4
1 7
C
H
H
P C 6
P C 5
P C 4
P C 3
P C 2
P C 1
P C 0
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
N C
N C
N C
N C
N C
6 0
4 3
1 8
4 2
1 9
2 0
2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0
4 1
/K
/K
/K
/K
/K
/K
/K
/T
/T
/IN
6
O S C 2
O S C 1
N C
N C
N C
P E 0 /M in
P E 1 /M o u t
P E 2 /M th
P E 3 /S D O
P E 4 /S D I
P E 5 /S C S
P E 6 /S C K
P E 7
R E S
V S S
V D D
V S S _ D A C
V D D _ D A C
L C H
R C H
4
5
3
2
1
0
M R 1
M R 0
T
8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1
1
2
6 0
5 9
3
5 8
4
5 7
5
5 6
6
5 5
7
5 4
8
5 3
9
5 2
H T 3 7 B 7 0
8 0 L Q F P -A
1 0
1 1
1 2
5 1
4 0
4 9
1 3
4 8
4 7
1 4
4 6
1 5
4 5
1 6
4 4
1 7
4 3
1 8
4 2
1 9
2 0
2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0
4 1
P C 6
P C 5
P C 4
P C 3
P C 2
P C 1
P C 0
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
N C
N C
N C
N C
N C
/K
/K
/K
/K
/K
/K
/K
/T
/T
/IN
6
5
4
3
2
1
0
M R 1
M R 0
T
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
S P 0
V D D
V S S
S P 1
V B IA
A U D
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
S P 0
V D D
V S S
S P 1
V B IA
A U D
_ A M P
_ A M P
S
_ IN
_ A M P
_ A M P
S
_ IN
P
P
P D 0 /R
P
P D
P
P
P
P
P
P
P
P
P
P
N
N
C 0 /K
C 1 /K
C 2 /K
C 3 /K
C 4 /K
C 5 /K
C 6 /K
C 7 /K
C O U
D 1 /R
D 2 /R
D 3 /C
4 /W A
D 5 /D
D 6 /C
P D
/A D
/A D
/A D
/A D
/A D
/A D
/A D
P B 0
P B 1
P B 2
P B 3
P B 4
P B 5
P B 6
R
C
C
C
C
K
S
T
T
0
1
2
3
4
5
6
7
0
1
2
3
4
1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 3 9 2 9 1 9 0 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6
1
7 5
N C
7 3
6 5
N C
P A
P A
P A
P A
P A
P A
P A
P A
6 3
N C
7 4
2
3
7 2
4
7 1
5
7 0
6
6 9
7
6 8
8
6 7
9
6 6
1 0
1 1
1 2
6 4
H T 3 7 B 9 0
1 0 0 L Q F P -A
1 3
1 4
6 2
6 1
1 5
6 0
1 6
5 9
1 7
5 8
1 8
5 7
1 9
5 6
2 0
5 5
2 1
5 4
2 2
5 3
2 3
5 2
2 4
2 5
2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
5 1
N C
N C
7 /T M R 1
6 /T M R 0
5 /IN T
4
3
2
1
0
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
S P
V D
V S
S P
V B
A U
N C
N C
N C
N C
N C
0
D _ A M P
S _ A M P
1
IA S
D _ IN
Rev. 1.00
5
6
7
P B 7 /A D 7
V D D _ A D C
V S S _ A D C
O S C 2
O S C 1
P E 0 /M in
P E 1 /M o u t
P E 2 /M th
P E 3 /S D O
P E 4 /S D I
P E 5 /S C S
P E 6 /S C K
P E 7
R E S
V S S
V D D
V S S _ D A C
V D D _ D A C
L C H
R C H
N C
N C
N C
N C
N C
2
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Pad Description
HT37B90, HT37B70
I/O
Configuration
Option
VDD
¾
¾
Positive digital power supply
VDD_DAC
¾
¾
Positive DAC circuit power supply
VDD_AMP
¾
¾
Positive power Amp. power supply
VDD_ADC
¾
¾
Positive ADC circuit power supply
VSS
¾
¾
Negative digital power supply, ground
VSS_DAC
¾
¾
Negative DAC power supply, ground
VSS_AMP
¾
¾
Negative AMP power supply, ground
VSS_ADC
¾
¾
Negative ADC power supply, ground
PA0~PA4
PA5/INT
PA6/TMR0
PA7/TMR1
I/O
Wake-up,
Pull-high
or None
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up
input by configuration option. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine if all
pins on this port have pull-high resistors. Pins PA5, PA6 and PA7 are
pin-shared with INT, TMR0 and TMR1, respectively.
PB0/AD0~
PB7/AD7
I/O
Pull-high
or None
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
if all pins on this port have pull-high resistors. Pins PB0 ~ PB7 are pin-shared
with AD0 and AD7, respectively.
I/O
Pull-high
or None
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
if all pins on this port have pull-high resistors. Pins PC0 ~ PC7 are pin-shared
with K0 and K7, respectively (K0~K7 are CR/F function).
Pull-high
or None
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
if all pins on this port have pull-high resistors. Pins PD0~PD3 are pin-shared
with R/F OSC input pins RCOUT, RR, RC and CC. PD4~PD6 are pin-shared
with IIS interface pins WAS, DT and CK. PD7 is normal I/O port.
RCOUT: Capacitor or resistor connection pin to RC OSC
RR: Oscillation input pin
RC: Reference resistor connection pin
CC: Reference capacitor connection pin
WAS, DT and CK control pin for IIS function
WAS: IIS word select output
DT: IIS data transmit output
CK: IIS serial clock output
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
if all pins on this port have pull-high resistors. Pins PE0~PE2 are pin-shared
with UART interface pins Min, Mout and Mth. Pins PE3~PE6 are pin-shared
with SPI interface pins SDO, SDI, SCS and SCK. PE7 is normal I/O port.
Min, Mout and Mth control pin for UART Function
Min: MIDI input
Mout: MIDI output
Mth: MIDI through
SDO, SDI, SCS and SCK control pin for SPI Function
SDO: SPI data output pin
SDI: SPI data input pin
SCS: SPI slave select signal.
SCK: SPI clock
Pad Name
PC0/K0~
PC7/K7
PD0/RCOUT
PD1/RR
PD2/RC
PD3/CC
PD4/WAS
PD5/DT
PD6/CK
PD7
I/O
PE0/Min
PE1/Mout
PE2/Mth
PE3/SDO
PE4/SDI
PE5/SCS
PE6/SCK
PE7
I/O
Pull-high
or None
RCH
O
¾
Rev. 1.00
Function
Audio right channel output
3
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
I/O
Configuration
Option
LCH
O
¾
Audio left channel output
SP1, SP0
O
¾
Power Amp. output pins
AUD_IN
I
¾
Power Amp. input pin
VBIAS
O
¾
Power Amp. voltage bias reference pin.
RES
I
¾
Schmitt Trigger reset input, active low
OSC1
OSC2
I
O
Pad Name
Note:
Crystal or RC
Function
OSC1, OSC2 are connected to an external RC network or external crystal,
determined by configuration option, for the internal system clock. If the RC
system clock option is selected, pin OSC2 can be used to measure the system clock at 1/8 frequency.
1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have pull-high resistors.
3. Because the two timers are used by MIDI the external timer pin functions are disabled.
HT37B50, HT37B30
I/O
Configuration
Option
VDD
¾
¾
Positive digital power supply
VDD_DAC
¾
¾
Positive DAC circuit power supply
VDD_AMP
¾
¾
Positive power Amp. power supply
VDD_ADC
¾
¾
Positive ADC circuit power supply
VSS
¾
¾
Negative digital power supply, ground
VSS_DAC
¾
¾
Negative DAC power supply, ground
VSS_AMP
¾
¾
Negative AMP power supply, ground
VSS_ADC
¾
¾
Negative ADC power supply, ground
Pad Name
PA0~PA4
PA5/INT
PA6/TMR0
PA7/TMR1
PB0/AD0~
PB7/AD7
PC0/K0~
PC7/K7
I/O
I/O
I/O
Function
Pull-high
Wake-up
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up
input by configuration option. Software instructions determine if the pin is a
CMOS output or Schmitt Trigger input. Configuration options determine if all
pins on this port have pull-high resistors. Pins PA5, PA6 and PA7 are
pin-shared with INT, TMR0 and TMR1, respectively.
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
if all pins on this port have pull-high resistors. Pins PB0 ~ PB7 are pin-shared
with AD0 and AD7, respectively.
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
if all pins on this port have pull-high resistors. Pins PC0 ~ PC7 are pin-shared
with K0 and K7, respectively (K0~K7 are CR/F function).
Bi-directional 4-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by pull-high option:
by option). Pins PD0~PD3 are pin-shared with CR/F OSC input pins
RCOUT, RR, RC and CC. RCOUT, RR, RC and CC control pin for CR/F
Function. Pins PD4, PD5, PD6 and PD7 are normal IO.
PD0/RCOUT
PD1/RR
PD2/RC
PD3/CC
PD4~PD7
I/O
Pull-high
RCH
O
¾
Audio right channel output
LCH
O
¾
Audio left channel output
SP1, SP0
O
¾
Power Amp. output pins
Rev. 1.00
4
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
I/O
Configuration
Option
AUD_IN
I
¾
Power Amp. input pin
VBIAS
O
¾
Power Amp. voltage bias reference pin.
RES
I
¾
Schmitt Trigger reset input, active low
OSC1
OSC2
I
O
Pad Name
Note:
Crystal or RC
Function
OSC1, OSC2 are connected to an external RC network or external crystal,
determined by configuration option, for the internal system clock. If the RC
system clock option is selected, pin OSC2 can be used to measure the system clock at 1/8 frequency.
1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins can be selected to have pull-high resistors.
3. Because the two timers are used by MIDI the external timer pin functions are disabled.
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V
Storage Temperature ...........................-50°C to 125°C
Input Voltage .............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature ..........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
fOSC=12.8MHz (37B50/30)
2.4
3.0
5.5
V
fOSC=12.8MHz (37B90/70)
3.0
¾
5.5
V
No load,
fOSC=8MHz~12.8MHz,
DAC disable
¾
8
12
mA
¾
20
30
mA
¾
¾
1
mA
¾
¾
2
mA
¾
¾
5
mA
¾
¾
10
mA
¾
0.3VDD
V
VDD
VDD
Operating Voltage
IDD
Operating Current
(Crystal OSC or RC OSC)
ISTB1
¾
3V
5V
3V
Standby Current (WDT Disable)
5V
ISTB2
3V
Standby Current (WDT Enable)
5V
Conditions
No load, system HALT,
WDT disable
No load, system HALT,
WDT enable
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
IOL
I/O Port Segment Logic Output
Sink Current
3V
6
12
¾
mA
10
25
¾
mA
I/O Port Segment Logic Output
Source Current
3V
-2
-4
¾
mA
-5
-8
¾
mA
IOH
Rev. 1.00
VOL=0.1VDD
5V
VOH=0.9VDD
5V
5
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Test Conditions
Symbol
RPH
Parameter
Typ.
Max.
Unit
¾
20
60
100
kW
¾
10
30
50
kW
2.28
2.40
2.52
V
Conditions
3V
5V
Pull-high Resistance of I/O Ports
VLVR
Min.
VDD
3V
LVR 2.4V option
5V
LVR 3.0V option
2.85
3.00
3.15
V
3V
LVD 2.5V option
2.375
2.500
2.625
V
5V
LVD 3.1V option
2.945
3.100
3.255
V
VOH=0.9VDD
¾
-3
¾
mA
¾
0.5
1
mA
¾
1.5
3
mA
(THD+N)/S£1%, RL=8W
VIN=1kHz Sinewave
¾
90
¾
mW
(THD+N)/S£10%, RL=8W
VIN=1kHz Sinewave
¾
125
¾
mW
(THD+N)/S£1%, RL=8W
VIN=1kHz Sinewave
¾
385
¾
mW
(THD+N)/S£10%, RL=8W
VIN=1kHz Sinewave
¾
490
¾
mW
Low Voltage Reset Voltage
VLVD
Low Voltage Detector Voltage
IO
AUD Current Source
¾
IADC
Additional Power Consumption if
A/D Converter is Used
3V
5V
3V
PO
¾
Internal AMP Output Power
5V
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
fOSC
Oscillator Clock
(Crystal OSC/RC OSC)
tWDTOSC
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
¾
2.4V~5.5V
Typ.
Max.
Unit
8000
11059
12800
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
¾
¾
1
¾
¾
ms
¾
1024
¾
tSYS
0.25
1.00
2.00
ms
tSST
System Start-up Timer Period
¾
Power-up or wake-up from
HALT
tLVR
Low Voltage Width to Reset
¾
¾
Note:
Min.
Conditions
tSYS= 1/fSYS
fSYS=fOSC/2
Rev. 1.00
6
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Characteristics Curves
R v s . F C h a rt
1 6
F re q u e n c y (M H z )
1 4
1 2
1 0
8
4 .5 V
6
4
8 2
9 1
1 0 0
1 1 5
1 2 0
3 .0 V
1 5 0
1 8 0
(k W )
R
V v s . F C h a r t (F o r 3 .0 V & 4 .5 V )
1 6
F re q u e n c y (M H z )
1 5
1 4
1 3
1 1 .0 5 9 M H z /1 0 0 k W
1 2
1 1
1 1 .0 5 9 M H z /1 1 5 k W
1 0
(4 .5 V )
(3 V )
9
8
Rev. 1.00
2 .4
2 .6
2 .8
3 .0
3 .2
3 .4
3 .6
V
7
3 .8
D D
(V )
4 .0
4 .2
4 .4
4 .6
4 .8
5 .0
5 .2
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
(THD+N) vs. Output Power
RLOAD=8W, VIN=1kHz Sinewave for 3.0V
%
1 0 0
5 0
2 0
1 0
5
2
1
0 .5
0 .2
0 .1
0 .0 5
0 .0 2
0 .0 1
1 m
2 m
5 m
1 0 m
2 0 m
5 0 m
1 0 0 m
2 0 0 m
5 0 m
1 0 0 m
2 0 0 m
5 0 0 m
1
2
5
O u tp u t P o w e r (W )
RLOAD=8W, VIN=1kHz Sinewave for 5.0V
%
1 0 0
5 0
2 0
1 0
5
2
1
0 .5
0 .2
0 .1
0 .0 5
0 .0 2
0 .0 1
1 m
Rev. 1.00
2 m
5 m
1 0 m
2 0 m
8
5 0 0 m
1
2
5
O u tp u t P o w e r (W )
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
System Architecture
instruction cycle. Although the fetching and execution of
instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions
where the contents of the Program Counter are
changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle
to execute. When the RC oscillator is used, OSC2 is
freed for use as a T1 phase clock synchronizing pin.
This T1 phase clock has a frequency of fOSC/8 with a 1:3
high/low duty cycle. For instructions involving branches,
such as jump or call instructions, two machine cycles
are required to complete instruction execution. An extra
cycle is required as the program takes one cycle to first
obtain the actual jump or call address and then another
cycle to actually execute the branch. The requirement
for this extra cycle should be taken into account by programmers in timing sensitive applications.
A key factor in the high-performance features of the
Holtek range of Music Type microcontrollers is attributed to the internal system architecture. The range of
devices take advantage of the usual features found
within RISC microcontrollers providing increased speed
of operation and enhanced performance. The pipelining
scheme is implemented in such a way that instruction
fetching and instruction execution are overlapped,
hence instructions are effectively executed in one cycle,
with the exception of branch or call instructions. An 8-bit
wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic
operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain
internal registers are implemented in the Data Memory
and can be directly or indirectly addressed. The simple
addressing methods of these registers along with additional architectural features ensure that a minimum of
external components is required to provide a functional
I/O and A/D control system with maximum reliability and
flexibility.
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL², that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator. The oscillator frequency
divided by 2 is subdivided into four internally generated
non-overlapping clocks, T1~T4. The Program Counter
is incremented at the beginning of the T1 clock during
which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution
functions. In this way, one T1~T4 clock cycle forms one
S y s te m
C lo c k o f M C U
(fS Y S = fO S C /2 )
P ro g ra m
T 1
C o u n te r
P ip e lin in g
T 2
T 3
T 4
T 1
T 2
P C
T 3
T 4
T 1
T 2
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
T 3
T 4
P C + 2
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1
M O V A ,[1 2 H ]
3
C P L [1 2 H ]
2
C A L L D E L A Y
4
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
5
:
6
D E L A Y :
E x e c u te In s t. 2
F e tc h In s t. 3
:
N O P
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
Instruction Fetching
Rev. 1.00
9
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack can have 12 levels depending upon which option
is selected and is neither part of the data nor part of the
program space, and is neither readable nor writable.
The activated level is indexed by the Stack Pointer, SP,
and is neither readable nor writable. At a subroutine call
or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a
subroutine or an interrupt routine, signaled by a return
instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the
stack.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be inserted.
Program Counter
Mode
b18~b13
b12 b11 b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
000000
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer/Event Counter 0
Overflow
000000
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1
Overflow
000000
0
0
0
0
0
0
0
0
0
1
1
0
0
Timer Counter 2
Overflow (UART)
000000
0
0
0
0
0
0
0
0
1
0
0
0
0
ERCOCI Interrupt
000000
0
0
0
0
0
0
0
0
1
0
1
0
0
ADPCM Interrupt
000000
0
0
0
0
0
0
0
0
1
1
0
0
0
Skip
Program Counter + 2 (Within Current Bank)
Loading PCL
Jump, Call Branch
P18~P13
P12 P11 P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
BP1.5~BP1.0 #12 #11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Return from Subroutine
S18~S13
S12 S11 S10
Program Counter
Note:
P18~P8: Program Counter bits
@7~@0: PCL bits
#12~#0: Instruction code address bits
BP1.5~BP1.0: ROM bank pointer
S18~S0: Stack register bits
For the HT37B90, the Program Counter is 19 bits wide, i.e. from b18~b0.
For the HT37B70, the Program Counter is 18 bits wide, i.e. from b17~b0, therefore the b18 column in the
table is not applicable.
For the HT37B50, the Program Counter is 17 bits wide, i.e. from b16~b0, therefore the b17 and b18 column in
the table is not applicable.
For the HT37B30, the Program Counter is 16 bits wide, i.e. from b15~b0, therefore the b18, b17 and b16 the
columns in the table are not applicable.
Rev. 1.00
10
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
P ro g ra m
T o p o f S ta c k
B o tto m
S ta c k L e v e l 3
o f S ta c k
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
C o u n te r
· Location 000H
This vector is reserved for use by the device reset for
program initialization. After a device reset is initiated,
the program will jump to this location and begin execution.
P ro g ra m
M e m o ry
S ta c k L e v e l 1 2
· Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
full.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
· Location 008H
This vector is reserved for the Timer/Event Counter 0
interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 008H.
· Location 00CH
This vector is reserved for the Timer/Event Counter 1
interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 00CH.
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
· Location 010H
This vector is reserved for the Timer Counter 2 interrupt service program. If a timer interrupt results from a
Timer Counter 2 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 0010H. Timer 2 Counter overflow
interrupt share with UART interrupt require. Using the
UART interrupt require is defined by enabled UART
function enable configuration option.
· Arithmetic operations: ADD, ADDM, ADC, ADCM,
· Location 014H
SUB, SUBM, SBC, SBCM, DAA
This vector is reserved for the ERCOCI interrupt service program. If an external RC oscillation converter
interrupt results from an external RC oscillation converter interrupt is activated, and the stack is not full,
the program begins execution at location 0014H.
· Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
· Increment and Decrement INCA, INC, DECA, DEC
· Location 018H
This vector is reserved for the Adpcm interrupt service
program. If a Adpcm interrupt results, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 0018H.
· Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user
code or program is stored. The type of memory is the
mask ROM memory. It offer the most cost effective solutions for high volume products.
Structure
The Program Memory has a capacity of 512K by 16,
256K by 16, 128K by 16 or 64K by 16 bits depending
upon which device is selected.
Rev. 1.00
11
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
0 0 0 H
0 0 4 H
0 0 8 H
0 0 C H
0 1 0 H
0 1 4 H
0 1 8 H
0 1 C H
H T 3 7 B 9 0
0 0 0 H
In itia lis a tio n
V e c to r
0 0 4 H
E x te rn a l
In te rru p t V e c to r
0 0 8 H
T im e r /E v e n t C o u n te r 0
In te rru p t V e c to r
0 0 C H
T im e r /E v e n t C o u n te r 1
In te rru p t V e c to r
0 1 0 H
T im e r C o u n te r 2
In te rru p t V e c to r (U A R T )
0 1 4 H
E R C O C I
In te rru p t V e c to r
0 1 8 H
A D P C M
In te rru p t V e c to r
0 1 C H
1 F F F H
H T 3 7 B 7 0
0 0 0 H
In itia lis a tio n
V e c to r
0 0 4 H
E x te rn a l
In te rru p t V e c to r
0 0 8 H
T im e r /E v e n t C o u n te r 0
In te rru p t V e c to r
0 0 C H
T im e r /E v e n t C o u n te r 1
In te rru p t V e c to r
0 1 0 H
T im e r C o u n te r 2
In te rru p t V e c to r (U A R T )
0 1 4 H
E R C O C I
In te rru p t V e c to r
0 1 8 H
A D P C M
In te rru p t V e c to r
0 1 C H
1 F F F H
7 F F F F H
3 F F F F H
1 6 b its
E x te rn a l
In te rru p t V e c to r
T im e r /E v e n t C o u n te r 0
In te rru p t V e c to r
T im e r /E v e n t C o u n te r 1
In te rru p t V e c to r
T im e r C o u n te r 2
In te rru p t V e c to r
E R C O C I
In te rru p t V e c to r
A D P C M
In te rru p t V e c to r
1 F F F H
B a n k 1 ~ 3 1
(B P 1 [4 :0 ]= [1 ]~ [1 F H ])
B a n k 1 ~ 6 3
(B P 1 [5 :0 ]= [1 ]~ [3 F H ])
H T 3 7 B 5 0
In itia lis a tio n
V e c to r
1 F F F F H
1 6 b its
0 0 0 H
0 0 4 H
0 0 8 H
0 0 C H
0 1 0 H
0 1 4 H
0 1 8 H
0 1 C H
1 F F F H
B a n k 1 ~ 1 5
(B P 1 [3 :0 ]= [1 ]~ [0 F H ])
1 6 b its
F F F F H
H T 3 7 B 3 0
In itia lis a tio n
V e c to r
E x te rn a l
In te rru p t V e c to r
T im e r /E v e n t C o u n te r 0
In te rru p t V e c to r
T im e r /E v e n t C o u n te r 1
In te rru p t V e c to r
T im e r C o u n te r 2
In te rru p t V e c to r
E R C O C I
In te rru p t V e c to r
A D P C M
In te rru p t V e c to r
B a n k 1 ~ 7
(B P 1 [2 :0 ]= [1 ]~ [7 ])
1 6 b its
Program Memory Structure
Look-up Table
Table Program Example
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the address of the look up data
to be retrieved in the three table pointer registers, TBLP,
TBMP and TBHP. This three registers define the address of the look-up table. After setting up the table
pointer, the table data can be retrieved from the current
Program Memory or last Program Memory page in the
specific bank which defined by bank point register as
BP1 using the ²TABRDC[m]² or ²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from the Program
Memory will be transferred to the user defined Data
Memory register [m] as specified in the instruction. The
higher order table data byte from the Program Memory
will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will have
uncertain values.
The following example shows how the table pointer and
table data is defined and retrieved from the
HT37B90/70/50/30 microcontroller. This example uses
raw table data located in the last page of ROM Bank 1
which is stored there using the ORG and ROMbank
statement. The location at program ROM ²3F00H²
which refers to the start address of the last page within
the Program Memory of the HT37B90/70/50/30
microcontroller. The table pointer is setup here to have
an initial value of ²06H². This will ensure that the first
data read from the data table will be at the Program
Memory address ²3F06H² or 6 locations after the start
of the last page in selected ROMbank. The high byte of
the table data which in this case is equal to zero will be
transferred to the TBLH register automatically when the
²TABRDL [m]² instruction is executed. Because the
TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if
both the main routine and Interrupt Service Routine use
table read instructions. If using the table read instructions, the Interrupt Service Routines may change the
value of the TBLH and subsequently cause errors if
used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where
simultaneous use cannot be avoided, the interrupts
should be disabled prior to the execution of any main
routine table-read instructions. Note that all table related
instructions require two instruction cycles to complete
their operation.
The following diagram illustrates the addressing/data
flow of the look-up table:
T B H P 1
P ro g ra m
M e m o ry
T B M P 1
T B L P 1
T B L H
H ig h B y te o f T a b le C o n te n ts
Rev. 1.00
S p e c ifie d b y [m ]
L o w
B y te o f T a b le C o n te n ts
12
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Instruction
Table Location Bits
b18~b13
b12~b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m] TBHP1_2~TBMP1_5 TBMP1_4~TBMP1_0 @7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
@6
@5
@4
@3
@2
@1
@0
BP1_5~BP1_0
11111
@7
Table Location
Note:
@7~@0: Table pointer lower-order bits are TBLP1 [7:0]
b17~b0: Current program ROM table address A [18:0]
TBMP1_4~TBMP1_0: TBMP1 bit 4 ~0
TBHP1_2~TBMP1_5: TBHP1 (bit 2 ~0) to TBMP1 (bit7 ~5)
BP1_5 ~BP1_0: Bits of bank BP1 bit0~5
For the HT37B90, the Table address location is 19 bits wide, i.e. from b18~b0.
For the HT37B70, the Table address location is 18 bits wide, i.e. from b17~b0.
For the HT37B50, the Table address location is 17 bits wide, i.e. from b16~b0.
For the HT37B30, the Table address location is 16 bits wide, i.e. from b15~b0.
tempreg1
tempreg2
tempreg3
tempreg4
mov
mov
mov
mov
clr
clr
db
db
db
db
?
?
?
?
:
:
a,01h
bp1,a
a,06h
tblp1,a
tbmpl
tbhpl
;
;
;
;
temporary
temporary
temporary
temporary
register
register
register
register
#1
#2
#3
#4
; set ROM bank 1 point
; initialise table pointer
; to the last page
:
:
tabrdl
tempreg1
;
;
;
;
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²3F06H² transferred to
tempreg1 and TBLH
dec tblp1
; reduce value of table pointer by one
tabrdl
;
;
;
;
;
;
;
;
tempreg2
:
:
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²3F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
the value ²00H² will be transferred to the high byte
register TBLH
mov a,04h
mov tblp1,a
mov a,3Fh
; initialise table pointer low byte
;
; initialise table pointer middle byte
mov tbmp1,a
mov a,00h
; initialise table pointer high byte
mov tbhp1,a
tabrdc
tempreg3
;
:
:
rombank 1 romsumvalue1; sets rombank 1 initial address of last page
;(for HT37B90/70/50/30)
romsumvalue1 .section at 1F00h ¢code¢
dc
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.00
13
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
ROM Bank Pointer (2DH)
The program memory is organized into 64/32/16/8 banks for HT37B90/70/50/30 and each bank into 8K´16 bits of program ROM. BP1.7~BP1.0 is used as the bank pointer. After an instruction has been executed to write data to the BP1
register to select a different bank, note that the new bank will not be selected immediately. It is until the instruction
²JMP² or ²CALL² or interrupt has completed execution that the bank will be actually selected.
Register
Bit No.
BP1 (2DH)
Note:
0~7
Function
00000000b= Select ROM Bank0 (0000h~1FFFh)
00000001b= Select ROM Bank1 (2000h~3FFFh)
00000010b= Select ROM Bank2 (4000h~5FFFh)
00000011b= Select ROM Bank3 (6000h~7FFFh)
:
00011110b= Select ROM Bank30 (3C000h~3DFFFh)
00011111b= Select ROM Bank31 (3E000h~3FFFFh)
00111110b= Select ROM Bank62 (7C000h~7DFFFh)
00111111b= Select ROM Bank63 (7E000h~7FFFFh)
For the HT37B90, the ROM bank point register is 6 bits wide effectively, i.e. from b5~b0.
For the HT37B70, the ROM bank point register is 5 bits wide effectively, i.e. from b4~b0.
For the HT37B50, the ROM bank point register is 4 bits wide effectively, i.e. from b3~b0.
For the HT37B30, the ROM bank point register is 3 bits wide effectively, i.e. from b2~b0.
RAM Data Memory
protected from user manipulation. The second area of
RAM Data Memory is reserved for general purpose use.
All locations within this area are read and write accessible under program control.
The RAM Data Memory is a volatile area of 8-bit wide
RAM internal memory and is the location where
temporary information is stored. Divided into two
sections, the first of these is an area of RAM where
special function registers are located. These registers
have fixed locations and are necessary for correct
operation of the device.
Structure
The RAM Data Memory is subdivided into 4 or 8 banks,
known as Bank 0 to Bank 3 or Bank 7, all of which are
implemented in 8-bit wide RAM. Most of the RAM Data
Memory is located in Bank 0 which is also subdivided
into two sections, the Special Purpose Data Memory
and the General Purpose Data Memory. The start address of the Data Memory is the address ²00H². Registers which are common to all microcontrollers, such as
ACC, PCL, etc., have the same Data Memory address.
Bank 1 of the RAM Data Memory is located at address
²60H².
Many of these registers can be read from and written to
directly under program control, however, some remain
0 0 H
5 F H
6 0 H
0 F F H
S p e c ia l P u r p o s e
D a ta M e m o ry
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
B a n k 0
B a n k 3
The RAM data memory is designed with 640´8 bits or
1280´8 bits with 4 or 8 RAM banks. There are two RAM
BANK pointers (RBP1 and RBP2 ) control Bank 0~7.
Bank 0~Bank 3 RAM Data Memory Structure HT37B70/50/30
0 0 H
5 F H
6 0 H
0 F F H
The data memory is designed with 256 bytes and divided into five functional groups: special function registers (00H~1FH), music synthesis controller registers
(20H~2FH), ADPCM decoder controller register
(30H~35H), the other function (35H~5FH) and general
purpose data memory (60H~FFH).
S p e c ia l P u r p o s e
D a ta M e m o ry
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
B a n k 0
B a n k 7
They are also indirectly accessible through Memory
Bank 0~Bank 7 RAM Data Memory Structure HT37B90
Rev. 1.00
14
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
IA R 0
2 E H
H T 3 7 B 9 0 /7 0
M P 2
0 0 H
0 2 H
IA R 1
3 0 H
A D R
0 2 H
IA R 1
0 4 H
R B P 1
0 4 H
R B P 1
0 0 H
0 1 H
0 3 H
0 5 H
0 6 H
H T 3 7 B 9 0 /7 0
M P 0
M P 1
A C C
P C L
0 7 H
T B L P 1
0 9 H
W D T S
0 8 H
T B L H
0 A H
S T A T U S
0 C H
T M R 0 H
0 E H
1 0 H
0 B H
0 D H
0 F H
3 6 H
3 7 H
3 8 H
3 E H
D A C C
2 1 H
F re q N H
2 3 H
A d d rH
3 9 H
3 F H
P B
4 2 H
P D
P E
D A L
C H A N
F re q N L
A d d rL
R e p H
R e p L
E N V
L V C
R V C
T B M P 1
2 D H
B P 1
T B H P 1
0 D H
3 D H
4 0 H
P C
0 B H
3 B H
P A
2 B H
2 C H
T M R 2 C
T B L H
T M R 1 L
1 F H
2 9 H
W D T S
0 F H
L V D C
A S C R
4 1 H
T M R A H
4 3 H
R C O C C R
4 5 H
T M R B L
4 4 H
T M R 1 C
1 3 H
P A C
1 5 H
P B C
1 7 H
P C C
1 9 H
P D C
1 4 H
T M R B H
1 6 H
4 6 H
R C O C R
4 8 H
A D R H
1 A H
4 A H
A C S R
1 C H
S B D R
1 E H
4 7 H
4 9 H
4 B H
4 C H
A D C R
S B C R
R S 2 3 2 C
4 F H
R X D
5 0 H
T X D
5 1 H
5 2 H
5 3 H
5 4 H
5 5 H
5 F H
6 0 H
F F H
: U n u s e d , re a d a s "0 0 "
1 F H
D A C C
2 1 H
F re q N H
2 3 H
A d d rH
2 4 H
2 5 H
B R G R
G e n
P u rp
D a ta M
(1 2 8 0
1 6 0 B y
B a n
2 6 H
2 7 H
2 8 H
2 9 H
e ra l
o s e
e m o ry
B y te s :
te s ´ 8
k s )
2 A H
D A L
C H A N
F re q N L
A d d rL
R e p H
R e p L
E N V
L V C
R V C
2 B H
T B M P 1
2 D H
B P 1
2 C H
T B H P 1
L V D C
A S C R
4 1 H
T M R A H
4 3 H
R C O C C R
4 4 H
4 5 H
T M R A L
T M R B H
T M R B L
4 6 H
R C O C R
4 8 H
A D R H
4 A H
A C S R
4 7 H
4 9 H
D A H
2 2 H
3 F H
4 2 H
P D
T M R 2 L
T M R 2 C
3 D H
P B
P C
A D P S
3 B H
4 0 H
1 D H
2 0 H
3 9 H
P A
1 B H
4 D H
4 E H
1 8 H
A D R L
T M R 0 L
1 1 H
1 2 H
T M R A L
IN T C
X S P H
IN T C H
1 0 H
D A H
2 A H
0 9 H
0 8 H
A D R
X S P L
3 5 H
3 4 H
3 E H
1 D H
2 7 H
2 8 H
T B L P 1
T M R 1 L
P E C
2 6 H
3 8 H
P C L
0 7 H
R B P 2
A D P C
3 C H
1 B H
2 5 H
T M R 2 L
0 6 H
H T 3 7 B 5 0 /3 0
M P 2
3 3 H
T M R 0 C
P D C
2 4 H
3 7 H
3 6 H
A D P S
3 2 H
0 E H
1 9 H
2 2 H
IN T C H
A C C
3 C H
T M R 0 L
P C C
2 0 H
3 5 H
3 4 H
0 5 H
T M R 0 C
1 7 H
1 E H
A D P C
3 1 H
3 A H
P B C
1 C H
X S P H
3 3 H
M P 1
3 0 H
T M R 0 H
1 5 H
1 A H
0 3 H
2 F H
0 C H
P A C
1 8 H
X S P L
M P 0
3 A H
IN T C
1 3 H
1 6 H
3 2 H
0 1 H
2 E H
S T A T U S
T M R 1 C
1 4 H
3 1 H
R B P 2
IA R 0
0 A H
1 1 H
1 2 H
2 F H
H T 3 7 B 5 0 /3 0
4 B H
A D R L
A D C R
4 C H
4 D H
4 E H
4 F H
5 0 H
5 1 H
5 2 H
5 3 H
5 4 H
5 5 H
5 F H
6 0 H
F F H
G e n
P u rp
D a ta M
(6 4 0 B
1 6 0 B y
B a n
e ra l
o s e
e m o ry
y te s :
te s ´ 4
k s )
Data Memory Structure
Rev. 1.00
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June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Indirect Addressing Register - IAR0, IAR1
pointer registers MP0, MP1and MP2, where MP1/MP2
can deal with all banks of data memory but MP0 deal
with Bank0 data memory only.
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1/MP2. Acting as
a pair, IAR0 and MP0 can together only access data
from Bank 0, while the IAR1 and MP1/MP2 register can
access data form Bank 0 to Bank 7. Using MP1 or MP2
are selected by DACC.7. As the Indirect Addressing
Registers are not physically implemented, reading the
Indirect Addressing Registers indirectly will return a result of ²00H² and writing to the registers indirectly will result in no operation.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. The bank 0
data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. By using the ²SET [m].i² and ²CLR [m].i² instructions
individual bits can be set or reset under program control
giving the user a large range of flexibility for bit manipulation in the Data Memory.
Special Purpose Data Memory
This area of Data Memory is where registers, necessary
for the correct operation of the microcontroller, are
stored. such as timers, interrupts, etc., as well as external functions such as I/O data control and A/D converter
operation. Most of the registers are both readable and
writable but some are protected and are readable only,
the details of which are located under the relevant Special Function Register section. Note that for locations
that are unused, any read instruction to these addresses
will return the value ²00H². Although the Special Purpose Data Memory registers are located in Bank 0, they
will still be accessible even if the Bank Pointer has selected Bank 1.
Memory Pointer - MP0, MP1, MP2
Three Memory Pointers, known as MP0, MP1 and MP2
are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated
in the same way as normal registers providing a convenient way with which to address and track data. When
any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the
microcontroller is directed to, is the address specified by
the related Memory Pointer. MP0, together with Indirect
Addressing Register, IAR0, are used to access data
from Bank 0 only, while MP1/MP2 and IAR1 are used to
access data form Bank 0 to Bank 7. Using MP1 or MP2
are selected by DACC.7.
Special Function Registers
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the RAM
Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts,
watchdog, etc., as well as external functions such as I/O
data control. The location of these registers within the
RAM Data Memory begins at the address ²00H².
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HT37B90/HT37B70/HT37B50/HT37B30
Example
The following example shows how to clear General Purpose Data Memory of bank0 by using MP0 and bank0~bank1
by using MP1 and MP2
code .section at 0 code
org 00h
RAM0TEST:
MOV A,60H
MOV MP0,A
; loaded with first RAM address
LOOP0:
CLR IAR0
; clear the data at address defined by MP0
CLR WDT
SIZ MP0
; increase MP0, and skip out if MP0 is ²0²
JMP LOOP0
:
RAM1TEST:
CLR DACC.7
; access data to iar1 by MP1
CLR rBP1
; clear RAM bank pointer 1
RAM1_MP1:
MOV A,rBP1
; load rBP1 data, and check if rBP1 is ²25²
XOR A,25
SZ
ZERO
; jump to exit loop if rBP1 is ²2²
JMP RAM1TEST_Exit
MOV A,60H
; loaded with first RAM address to MP1
MOV MP1,A
LOOP1:
CLR WDT
CLR IAR1
; clear the data at address defined by MP1
SIZ MP1
; increase MP1, and skip out if MP1 is ²0²
JMP LOOP1
INC rBP1
; increase rBP1
JMP RAM1_MP1
RAM1TEST_Exit:
:
RAM2TEST:
Set dacc.7
; access data to iar1 by MP2
CLR rBP2
; clear RAM bank pointer 2
RAM1MP2:
MOV A,RBP2
XOR A,25
SZ
ZERO
JMP RAM2TEST_Exit
MOV A,60H
MOV MP2,A
LOOP2:
CLR WDT
CLR IAR1
SIZ MP2
JMP LOOP2
INC rBP2
JMP RAM1MP2
RAM2TEST_Exit:
:
Rev. 1.00
; jump to exit loop if rBP2 is ²2²
; loaded with first RAM address to MP2
; clear the data at address defined by MP2
; increase MP2, and skip out if MP2 is ²0²
; increase rBP2
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June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Bank Pointer - RBP1, RBP2
Accumulator - ACC
The RAM Data Memory is divided into 8 Banks, known as
Bank 0 to Bank 7. Selecting the required Data Memory
area is achieved using the RAM Bank Pointers which are
RBP1 and RBP2. The RBP1 and RBP2 match up with
MP1 and MP2 respectively. If data in Bank 0 is to be accessed, then the RBP registers must be loaded with the
value ²00², while if data in Bank 1 is to be accessed, then
the RBP registers must be loaded with the value ²01².
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank Pointer. The RBP1 and
RBP2 register is located at memory location 60H in
Bank 0 to Bank 7 and can only be accessed indirectly
using two memory pointers MP1 and MP2 and the indirect addressing register IAR1 will always access data
from Bank 0 to Bank 7.
Program Counter Low Register - PCL
The Data Memory is initialized to Bank 0 after a reset,
except for the WDT time-out reset in the Power Down
Mode, in which case, the Data Memory bank remains
unaffected. It should be noted that Special Function
Data Memory is not affected by the bank selection,
which means that the Special Function Registers can be
accessed from within Bank 0 to Bank 7. Directly addressing the Data Memory will always result in Bank 0
being accessed irrespective of the value of the Bank
Pointer.
Register
Bit No.
Function
0~2
RAM Bank Point 1 Select
000= Select RAM Bank0
001= Select RAM Bank1
010= Select RAM Bank2
011= Select RAM Bank3
100= Select RAM Bank4
101= Select RAM Bank5
110= Select RAM Bank6
111= Select RAM Bank7
3~4
General bits. Can write and
read.
5~7
Unused bit
RBP1
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
Look-up Table Registers - TBLP1, TBMP1, TBHP1,
TBLH
These seven special function registers are used to control operation of the look-up table which is stored in the
Program Memory. TBLP1, TBMP1 and TBHP1 are the
table pointer and indicate the location where the table
data is located. Their value must be setup before any table read commands are executed. Their value can be
changed, for example using the ²INC² or ²DEC² instructions, allowing for easy table data pointing and reading.
TBLH is the location where the high order byte of the table data is stored after a table read data instruction has
been executed. Note that the lower order table data byte
is transferred to a user defined location.
RBP1 (04H)
Register
Bit No.
Function
0~2
RAM Bank Point 2 Select
000= Select RAM Bank0
001= Select RAM Bank1
010= Select RAM Bank2
011= Select RAM Bank3
100= Select RAM Bank4
101= Select RAM Bank5
110= Select RAM Bank6
111= Select RAM Bank7
3~4
General bits. Can write and
read.
5~7
Unused bit
RBP2
Watchdog Timer Register - WDTS
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be
RBP2 (2FH)
Note: Using MP1 or MP2 are selected by DACC.7.
Rev. 1.00
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June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
Status Register - STATUS
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
Interrupt Control Registers - INTC, INTCH
The two 8-bit registers, known as the INTC and INTCH
register which control the operation of both external and
internal timer, UART, CR/F and ADPCM interrupts, and
By setting various bits within this register using standard
bit manipulation instructions, the enable/disable function of the external and timer, UART, CR/F and ADPCM
interrupts can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a
global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and
is set by executing the ²RETI² instruction.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Note:
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
In situations where other interrupts may require
servicing within present interrupt service routines, the EMI bit can be manually set by the
program after the present interrupt service routine has been entered.
· AC is set if an operation results in a carry out of the
Timer/Event Counter Registers - TMR0H, TMR0L,
TMR1L, TMR2L, TMR0C, TMR1C, TMR2C
· C is set if an operation results in a carry during an ad-
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
HT37B90/70/50/30 contains two 8-bit and a 16-bit
Timer/Event Counters which has an associated register
known as TMR0H and TMR0L. are the location where
the timer¢s 16-bit value is located.TMR1L and TMR2L
are the location where the timer¢s 8-bit value is located.
An associated control register, known as TMR0C,
TMR1C and TMR2C contains the setup information for
the timer.
· Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
· TO is cleared by a system power-up or executing the
b 7
T O
P D F
O V
Z
A C
b 0
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev. 1.00
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June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Input/Output Ports and Control Registers PA, PB, PC, PD, PE, PAC, PBC, PCC, PDC, PEC
the end code (80H) until the volume become close. It
provides the left and right volume control independently.
The 10-bit left and right volume are controlled by ENL,
LVC and RVC respectively. The ENV contain both left
and right volume some bit of high byte.
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC, PD and PE.
These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data
Memory table, which are used to transfer the appropriate output or input data on that port. with each I/O port
there is an associated control register labeled PAC,
PBC, PCC, PDC and PEC, also mapped to specific addresses with the Data Memory. The control register
specifies which pins of that port are set as inputs and
which are set as outputs. To setup a pin as an input, the
corresponding bit of the control register must be set
high, for an output it must be set low. During program initialization, it is important to first setup the control registers to specify which pins are outputs and which are
inputs before reading data from or writing data to the I/O
ports. One flexible feature of these registers is the ability
to directly program single bits using the ²SET [m].i² and
²CLR [m].i² instructions. The ability to change I/O pins
from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.
ADPCM Function Registers ADR, XSPL, XSPH, ADPC, ADPS
HT37B90/70/50/30 contains ADPCM Decoder Function. The must set initial value of register known as
XSPL and XSPH before implementing ADPCM Decoder
procedure. There are two 4-bit ADPCM encode data of
ADR. The data of ADR implement via ADPCM Decoder,
and output 8-bit PCM data which is synthesized by MIDI
synthesizer.
The ADPC is the control register for the ADPCM Decoder. The ADPS is the status register for the ADPCM
Decoder.
CR/F Converter Registers - ASCR, TMRAH, TMRAL,
RCOCCR, TMRBH, TMRBL, RCOCR
There are 8 analog switch lines in the microcontroller for
K0~K7 for HT37B90/70/50/30 Analog Switch control
registers known as ASCR. The RC oscillation converter
contains two 16-bit programmable count-up counters
and the Timer A clock source may come from the system clock (fSYS=fOSC/2) or system clock/4 (fOSC/8). There
are two data registers, a high byte data register known
as TMRAH, and a low byte data register known as
TMRAL. The timer B clock source may come from the
external RC oscillator. There are two data registers, a
high byte data register known as TMRBH, and a low
byte data register known as TMRBL. There are two control and status registers known as RCOCCR and
RCOCR.
D/A Converter Registers - DAH, DAL, DACC
HT37B90/70/50/30 provide two 16-bit D/A converters,
which can select stereo or mono output. The correct operation of the D/A requires the use of two data registers,
and a control register. It contain a 16-bit D/A converter,
there are two data registers, a high byte data register
known as DAH, and a low byte data register known as
DAL. These are the register locations where the digital
value is placed before the completion of a digital to analog conversion cycle. The configuration of the D/A converter is setup via the control register DACC.
A/D Converter Registers ADRL, ADRH, ADCR, ACSR
HT37B90/70/50/30 contains a 8-channel 12-bit A/D
converter. The correct operation of the A/D requires the
use of two data registers, a control register and a clock
source register. It contain a 12-bit A/D converter, there
are two data registers, a high byte data register known
as ADRH, and a low byte data register known as ADRL.
These are the register locations where the digital value
is placed after the completion of an analog to digital conversion cycle. The channel selection and configuration
of the A/D converter is setup via the control register
ADCR while the A/D clock frequency is defined by the
clock source register, ACSR.
Wavetable Function Registers - CHAN, FreqNH,
FreqNL, RepH, RepL, ENV, LVC, RVC
HT37B90/70/50/30 contains Wavetable synthesizer
Function. The HT37B90/70/50/30 has a built-in 16 output channels. CHAN is channel number selection.
FreqNH and FreqNL are used to define the output
speed of the PCM file.
AddrH and AddrL is setup for the start address of the
PCM code before Wavetable function implement. The
repeat number register as known RepH and RepL are
used to define the address which is the repeat point of
the sample. When the repeat number is defined, it will
be output from the start code to the end code once and
always output the range between the repeat address to
Rev. 1.00
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June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
SPI Registers - SBCR, SBDR
Various methods exist to wake-up the microcontroller,
one of which is to change the logic condition on one of
the PA0~PA7 pins from high to low. After a HALT instruction forces the microcontroller into entering the Power
Down Mode, the processor will remain idle or in a
low-power state until the logic condition of the selected
wake-up pin on Port A changes from high to low. This
function is especially suitable for applications that can
be woken up via external switches. Note that pins PA0 to
PA7 can be selected individually to have this wake-up
feature using an PA wake up option, located in the configuration.
The device contain an internal SPI function which is
controlled via these two registers. The SBCR is the status and control register for the SPI function. The actual
data that is to be transmitted or that is received on the
serial interface is stored in the SBDR register.
UART Registers - RS232C, TXD, RXD, BRGR
The device contain an internal UART function which is
controlled via these four registers. The RS232C is the
status and control register for the UART .The actual data
that is to be transmitted or that is received on the serial
interface is stored in the TXD/RXD register. The BRGR
register set to generates UART baud rate clock
31.25kHz according to fOSC.
I/O Port Control Registers
Each I/O port have their own control register, known as
PAC, PBC, PCC, PDC and PEC, which control the input/output configuration. With this control register, each
PA~PE I/O pin with or without pull-high resistors can be
reconfigured by pull-hi option control. Pins PA~PE ports
are directly mapped to a bit in its associated port control
register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a
²1². This will then allow the logic state of the input pin to
be directly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O
pin will be setup as a CMOS output. If the pin is currently
setup as an output, instructions can still be used to read
the output register.
Input/Output Ports
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities. Depending upon which device or package is chosen, the
microcontroller range provides from 32 to 40
bidirectional input/output lines labeled with port names
PA, PB, PC, PD and PE. These I/O ports are mapped to
the RAM Data Memory with specific addresses as
shown in the Special Purpose Data Memory table. All of
these I/O ports can be used for input and output operations. For input operation, these ports are non-latching,
which means the inputs must be ready at the T2 rising
edge of instruction ²MOV A,[m]², where m denotes the
port address.
However, it should be noted that the program will in fact
only read the status of the output data latch and not the
actual logic status of the output pin.
· Pin-shared Functions
The flexibility of the microcontroller range is greatly
enhanced by the use of pins that have more than one
function. Limited numbers of pins can force serious
design constraints on designers but by supplying pins
with multi-functions, many of these difficulties can be
overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins PA~PE, when configured as an input
have the capability of being connected to an internal
pull-high resistor. These pull-high resistors are
selectable via PA~PE option respectively, located in the
configuration. The pull-high resistors are implemented
using weak PMOS transistors.
· External Interrupt Input
The external interrupt pin, INT, is pin-shared with the
I/O pin PA5. To use the pin as an external interrupt input the correct bits in the PA share pin option must be
selected. The pin must also be setup as an input by
setting the appropriate bit in the Port Control Register.
A pull-high resistor can also be selected via the appropriate port pull-high option.
Port A Wake-up
If the HALT instruction is executed, the device will enter
the Power Down Mode, where the system clock will stop
resulting in power being conserved, a feature that is important for battery and other low-power applications.
Rev. 1.00
21
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
· A/D Inputs
I/O Pin Structures
The HT37B90/70/50/30 have 8 A/D converter channel
inputs. All of these analog inputs are pin-shared with
PB0 to PB7. If these pins are to be used as A/D inputs
and not as normal I/O pins then the corresponding bits
in the A/D Converter Control Register, ADCR.3~5 and
ADSR.4, must be properly set. There are no configuration options associated with the A/D function. If
used as I/O pins, then full pull-high resistor selections
remain, however if used as A/D inputs then any
pull-high resistor selections associated with these
pins will be automatically disconnected.
The diagrams illustrate the I/O pin internal structures. As
the exact logical construction of the I/O pin may differ
from these drawings, they are supplied as a guide only
to assist with the functional understanding of the I/O
pins.
Programming Considerations
Within the user program, one of the first things to consider is port initialization. After a reset, the PA~PE data
register and PAC~PEC port control register will be set
high. This means that all I/O pins will default to an input
state, the level of which depends on the other connected
circuitry and whether pull-high options have been selected. If the PAC port control register, is then programmed to setup some pins as outputs, these output
pins will have an initial high output value unless the associated PA port data register is first programmed. Selecting which pins are inputs and which are outputs can
be achieved byte-wide by loading the correct value into
the port control register or by programming individual
bits in the port control register using the ²SET [m].i² and
²CLR [m].i² instructions.
· CR/F analog switch Inputs
The HT37B90/70/50/30 have 8 CR/F converter inputs. All of these analog inputs are pin-shared with
PC0 to PC7. If these pins are to be used as CR/F analog switch Inputs and not as normal I/O pins then the
corresponding bits in the Option, ²PC0~7 share pin
configuration². All of these analog inputs are
pin-shared with PC0 to PC7. If these pins are to be
used as CR/F analog switch Inputs and not as normal
I/O pins then the corresponding bits in the configuration, ²PC0~7 share pin configuration².
· CR/F oscillator pin
The HT37B90/70/50/30 have 4 CR/F oscillator pins. All
of these CR/F oscillator pin are pin-shared with PD0 to
PD3. If these pins are to be used as CR/F oscillator
pins and not as normal I/O pins then the corresponding
bits in the Option, ²PD0~3 share pin Option².
Note that when using these bit control instructions, a
read-modify-write operation takes place. The
microcontroller must first read in the data on the entire
port, modify it to the required new bit values and then rewrite this data back to the output ports.
· UART pin
The device have 3 UART pins. All of these UART pins
are pin-shared with PE0 to PE2. If these pins are to be
used as UART pins and not as normal I/O pins then
the corresponding bits in the PE share pin configuration option.
S y s te m
T 1
C lo c k
T 2
T 3
T 4
T 1
W r ite to P o r t
The device have 4 SPI pins. All of these SPI pins are
pin-shared with PE3 to PE6. If these pins are to be
used as SPI pins and not as normal I/O pins then the
corresponding bits in the PE share pin configuration
option.
W r ite C o n tr o l R e g is te r
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite I/O
V
Q
V
S
D a ta B it
Q
D
P o rt
D D
D D
W e a k
P u ll- u p
C K
S
I/O
L in e
Q
M
W a k e -U p
R e a d fro m
M a s k O p tio n
R e a d I/O
S y s te m
T 4
Read/Write Timing
C o n tr o l B it
Q
D
C K
T 3
P o rt D a ta
· SPI pin
D a ta B u s
T 2
U
X
M a s k O p tio n
Input/Output Port
Rev. 1.00
22
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Timer/Event Counters
initial value can be preloaded. Reading from this register
retrieves the contents of the Timer/Event Counter. The
second type of associated register is the Timer Control
Register which defines the timer options and determines how the timer is to be used. The Timer/Event
Counter 0 can have the timer clock configured to come
from the internal clock source. The clock source is
fOSC/8.In addition, the timer clock source of Timer/Event
Counter 0 can also be configured to come from an internal RC 12kHz.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. The devices contain two
count-up timers 8-bit capacity and one count-up timers
16-bit capacity. As the timer 0/1 has three different operating modes, they can be configured to operate as a
general timer, an external event counter or as a pulse
width measurement device. But the timer 2 only be configured to operate as a general timer. The provision of an
internal prescaler to the clock circuitry of some of the
timer/event counters gives added range to the timer 1/2.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on the external timer pin, known as TMR0 or TMR1.
These external timer pins are pin-shared with other I/O
pins. Depending upon the condition of PA share pin option, each high to low, or low to high transition on the external timer input pin will increment the counter by one.
There are three types of registers related to the
Timer/Event Counters 0. The first two register contain
the actual high and low byte value of the timer and into
which an initial value can be preloaded.
There are two types of registers related to the
Timer/Event Counters 1/2. The first is the register that
contains the actual value of the timer and into which an
D a ta B u s
L o w B y te
B u ffe r
fO
S C
M
/8
R C 1 2 K
T M R 0
U
T 0 M 1
X
T 0 S
1 6 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
T 0 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T 0 O N
H ig h B y te
L o w
R e lo a d
O v e r flo w
to In te rru p t
B y te
1 6 - B it T im e r /E v e n t C o u n te r
T 0 E
16-bit Timer/Event Counter 0 Structure
D a ta B u s
P r e lo a d R e g is te r
T 1 M 1
T 1 P S C 2 ~ T 1 P S C 0
(1 /1 6 ~ 1 /2 0 4 8 )
fO
S C
8 - S ta g e P r e s c a le r
T M R 1
R e lo a d
T 1 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
O v e r flo w
to In te rru p t
T im e r /E v e n t C o u n te r
T 1 O N
T 1 E
8-bit Timer/Event Counter 1 Structure
D a ta B u s
P r e lo a d R e g is te r
T 2 M 1
T 2 P S C 2 ~ T 2 P S C 0
(1 /1 6 ~ 1 /2 0 4 8 )
fO
S C
8 - S ta g e P r e s c a le r
R e lo a d
T 2 M 0
T im e r C o u n te r
M o d e C o n tro l
T im e r C o u n te r
T 2 O N
O v e r flo w
to In te rru p t
8-bit Timer Counter 2 Structure
Rev. 1.00
23
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Configuring the Timer/Event Counter Input Clock
Source
generated. The timer value will then be reset with the initial preload register value and continue counting.
The internal timer¢s clock can originate from various
sources, depending upon timer is chosen. The system
clock input timer source is used when the timer is in the
timer mode or in the pulse width measurement mode.
Note that to achieve a maximum full range count of FFH
for the 8-bit timer or FFFFH for the 16-bit timers, the
preload registers must first be cleared to all zeros. It
should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the
Timer/Event Counters are in an OFF condition and data
is written to their preload registers, this data will be immediately written into the actual counter. However, if the
counter is enabled and counting, any new data written
into the preload data register during this period will remain in the preload register and will only be written into
the actual counter the next time an overflow occurs.
Note also that when the timer registers are read, the
timer clock will be blocked to avoid errors, however, as
this may result in certain timing errors, programmers
must take this into account.
For Timer/Event Counter 0, these system clock timer
source is selected by TMR0C.5.
For Timer/Event Counter 1, 2 this system clock timer
source is first divided by a prescaler, the division ratio of
which is conditioned by the Timer Control Register bits
T1PSC0~T1PSC2.
An external clock source is used when the timer is in the
event counting mode, the clock source being provided
on the external timer pin, known as TMR0 or TMR1.
These external timer pins are pin-shared with other I/O
pins. Depending upon the condition of PA share pin option, each high to low, or low to high transition on the external timer input pin will increment the counter by one.
The 16-bit Timer/Event Counter have contained both
low byte and high byte timer registers, accessing these
registers is carried out in a specific way. It must be noted
that when using instructions to preload data into the low
byte register, namely TMR0L, the data will only be
placed in a low byte buffer and not directly into the low
byte register. The actual transfer of the data into the low
byte register is only carried out when a write to its associated high byte register, namely TMR0H, is executed.
On the other hand, using instructions to preload data
into the high byte timer register will result in the data being directly written to the high byte register. At the same
time the data in the low byte buffer will be transferred
into its associated low byte register. For this reason,
when preloading data into the 16-bit timer registers, the
low byte should be written first. It must also be noted that
to read the contents of the low byte register, a read to the
Timer Registers - TMR0H/TMR0L, TMR1, TMR2
The timer registers are special function registers located
in the special purpose Data Memory and is the place
where the actual timer value is stored. For the 8-bit timer,
this register is known as Timer/Event Counter 1/2. In the
case of the 16-bit timer, a pair of 8-bit registers are required to store the 16-bit timer values. These are known
as TMR1L/TMR1H. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external
timer pin. The timer will count from the initial value loaded
by the preload register to the full count of FFH for the 8-bit
timer or FFFFH for the 16-bit timers, at which point the
timer overflows and a timer internal interrupt signal is
b 7
T 0 M 1 T 0 M 0
T 0 S
T 0 O N
T 0 E
b 0
T M R 0 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
E v e n t C
1 : c o u n
0 : c o u n
P u ls e W
1 : s ta rt
0 : s ta rt
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
T im e r C lo c k S o u r c e
1 : R C 1 2 K
0 : fO S C /8
O p e r a tin g M o d e S e le c
T 0 M 0
T 0 M 1
n o
0
0
e v
1
0
tim
0
1
1
p u
1
t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
Rev. 1.00
24
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
b 7
T 1 M 1 T 1 M 0
T 1 O N
T 1 E
b 0
T 1 P S C 2 T 1 P S C 1 T 1 P S C 0
T M R 1 C
R e g is te r
T im e r P r e s c a le r R a te S e le c t
T 1 P S C 2 T 1 P S C 1 T 1 P S C 0 T im e r
1 :1
0
0
0
1 :3
1
0
0
1 :6
0
1
0
1 :1
1
1
0
1 :2
0
0
1
1 :5
1
0
1
1 :1
0
1
1
1 :2
1
1
1
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
R a te
6
2
4
2 8
5 6
1 2
0 2 4
0 4 8
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g M o d e S e le c
T 1 M 0
T 1 M 1
n o
0
0
e v
1
0
tim
0
1
1
1
p u
t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
b 7
T 2 M 1 T 2 M 0
T 2 O N
T 2 E
b 0
T 2 P S C 2 T 2 P S C 1 T 2 P S C 0
T M R 2 C
R e g is te r
T im e r P r e s c a le r R a te S e le c t
T 2 P S C 2 T 2 P S C 1 T 2 P S C 0 T im e r
1 :1
0
0
0
1 :3
1
0
0
1 :6
0
1
0
1 :1
1
1
0
1 :2
0
0
1
1 :5
1
0
1
1 :1
0
1
1
1 :2
1
1
1
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
R a te
6
2
4
2 8
5 6
1 2
0 2 4
0 4 8
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g M o d e S e le c
T 2 M 0
T 2 M 1
n o
0
0
n o
1
0
tim
0
1
1
1
n o
t
m o d
m o d
e r m
m o d
e a v a ila b le
e a v a ila b le
o d e
e a v a ila b le
Timer Counter 2 Control Register
Rev. 1.00
25
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
determined by bits PSC0~PSC2 of the TMR1C~
TMR2C register. The timer-on bit, TON must be set high
to enable the timer to run. Each time an internal clock
high to low transition occurs, the timer increments by
one. When the timer is full and overflows, the timer will
be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The
timer interrupt can be disabled by ensuring that the
ET0I~ET2I bit in the INTC and INTCH registers is
cleared to zero. It should be noted that a timer overflow
is one of the wake-up sources.
high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte
register. After this has been done, the low byte register
can be read in the normal way. Note that reading the low
byte timer register will only result in reading the previously latched contents of the low byte buffer and not the
actual contents of the low byte timer register.
Timer Control Registers - TMR0C, TMR1C, TMR2C
The Timer/Event Counters0/1 enable them to operate in
three different modes. the options of which are determined by the contents of their respective control register. There are four timer control registers, known as
TMR0C, TMR1C and TMR2C. It is the timer control register together with its corresponding timer registers that
control the full operation of the Timer/Event Counters.
Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with
the right data to ensure its correct operation, a process
that is normally carried out during program initialization.
To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode
or the pulse width measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
pair T0M1/T0M0, T1M1/T1M0 respectively, depending
upon which timer is used, must be set to the required
logic levels. The timer-on bit, which is bit 4 of the Timer
Control Register and known as T0ON, T1ON or T2ON,
depending upon which timer is used, provides the basic
on/off control of the respective timer. Setting the bit high
allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode, the active transition edge level type is
selected by the logic level of bit 3 of the Timer Control
Register which is known as T0E, T1E or T2E, depending upon which timer is used.
Configuring the Event Counter Mode
In this mode, two number of externally changing logic
events, occurring on external pin PA6/TMR0 or
PA7/TMR1, can be recorded by the internal timer. For
the timer to operate in the event counting mode, bits
TM1 and TM0 of the TMR0C or TMR1C registers must
be set to 0 and 1 respectively. The timer-on bit, TON
must be set high to enable the timer to count. With TE
low, the counter will increment each time the PA6/TMR0
or PA7/TMR1 pin receives a low to high transition. If the
TE bit is high, the counter will increment each time
PA6/TMR0 or PA7/TMR1 pin receives a high to low transition. As in the case of the other two modes, when the
counter is full and overflows, the timer will be reset to the
value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated.
The timer interrupt can be disabled by ensuring that the
ETI bit in the INTC and INTCH registers is cleared to
zero. To ensure that the external pin PA6/TMR0 or
PA7/TMR1 is configured to operate as an event counter
input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event
counter in the event counting mode, the second is to ensure that the share pin TMR0 or TMR1 are selected by
option. It should be noted that a timer overflow is one of
the wake-up sources. Also in the Event Counting mode,
the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if
the microcontroller is in the Power Down Mode. As a result when the timer overflows it will generate a wake-up
and if the interrupts are enabled also generate a timer
interrupt signal.
Configuring the Timer Mode
In this mode, the timer can be utilized to measure fixed
time intervals, providing an internal interrupt signal each
time the counter overflows. To operate in this mode, bits
TM1 and TM0 of the TMR0C~TMR2C register must be
set to 1 and 0 respectively. In this mode, the internal
clock is used as the timer clock. The input clock frequency of 16 bit timer to the timer is fOSC/8 and RC12K,
selected by TMR0C.5. The input clock frequency of 8 bit
timer to the timer is Fosc divided by the value programmed into the timer prescaler, the value of which is
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+ 1
Timer Mode Timing Diagram
Rev. 1.00
26
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
E x te r n a l T im e r
P in In p u t
T 0 E o r T 1 E = 1
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Diagram
Configuring the Pulse Width Measurement Mode
Prescaler
In this mode, the width of external pulses applied to the
pin-shared external pin PA6/TMR0 or PA7/TMR1 can be
measured. In the Pulse Width Measurement Mode, the
timer clock source is supplied by the internal clock. For
the timer to operate in this mode, bits TM0 and TM1
must both be set high. If the TE bit is low, once a high to
low transition has been received on the PA6/TMR0 or
PA7/TMR1 pin, the timer will start counting until the
PA6/TMR0 or PA7/TMR1 pin returns to its original high
level. At this point the TON bit will be automatically reset
to zero and the timer will stop counting. If the TE bit is
high, the timer will begin counting once a low to high
transition has been received on the PA6/TMR0 or
PA7/TMR1 pin and stop counting when the PA6/TMR0
or PA7/TMR1 pin returns to its original low level. As before, the TON bit will be automatically reset to zero and
the timer will stop counting. It is important to note that in
the Pulse Width Measurement Mode, the TON bit is automatically reset to zero when the external control signal
on the external timer pin returns to its original level,
whereas in the other two modes the TON bit can only be
reset to zero under program control. The residual value
in the timer, which can now be read by the program,
therefore represents the length of the pulse received on
pin PA6/TMR0 or PA7/TMR1. As the TON bit has now
been reset any further transitions on the PA6/TMR0 or
PA7/TMR1 pin will be ignored. Not until the TON bit is
again set high by the program can the timer begin further pulse width measurements. In this way single shot
pulse measurements can be easily made. It should be
noted that in this mode the counter is controlled by logical transitions on the PA6/TMR0 or PA7/TMR1 pin and
not by the logic level.
Bits PSC0~PSC2 of the TMRC1~ TMRC2 registers can
be used to define the pre-scaling stages of the internal
clock sources of the Timer/Event Counter.
Note: Because the two timers are used by MIDI the external timer pin functions are disabled.
I/O Interfacing
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, require the use of the external PA6/TMR0 or PA7/TMR1
pin for correct operation. As this pin is a shared pin it
must be configured correctly to ensure it is setup for use
as a Timer/Event Counter input and not as a normal I/O
pin. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width
measurement mode. Additionally the PA share pin option must be selected to ensure that the pin is setup as
an TMR0 and TMR1 input.
Programming Considerations
When configured to run in the timer mode, the internal
system clock fOSC/8 is used as the timer clock source
and is therefore synchronized with the overall operation
of the microcontroller. In this mode when the appropriate
timer register is full, the microcontroller will generate an
internal interrupt signal directing the program flow to the
respective internal interrupt vector. For the pulse width
measurement mode, the internal system clock is also
used as the timer clock source but the timer will only run
when the correct logic condition appears on the external
timer input pin. As this is an external event and not synchr oniz ed w ith the int erna l tim er c loc k, the
microcontroller will only see this external event when the
next timer clock pulse arrives. As a result, there may be
E x te r n a l T im e r
P in In p u t
T O N
( w ith T E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
T im e r
+ 1
+ 2
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f fO
+ 3
S C
+ 4
/8 o r R C 1 2 K .
Pulse Width Measure Mode Timing Diagram
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June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
register. Note that setting the timer enable bit high to
turn the timer on, should only be executed after the timer
mode bits have been properly setup. Setting the timer
enable bit high together with a mode bit modification,
may lead to improper timer operation if executed as a
single timer control register byte write instruction. When
the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be
set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether
the interrupts are enabled or not, a Timer/Event counter
overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may
occur if the Timer/Event Counter is in the Event
Counting Mode and if the external signal continues to
change state. In such a case, the
small differences in measured values requiring programmers to take this into account during programming.
The same applies if the timer is configured to be in the
event counting mode, which again is an external event
and not synchronized with the internal system or timer
clock. When the Timer/Event Counter is read, or if data
is written to the preload register, the clock is inhibited to
avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are
properly initialized before using them for the first time.
The associated timer enable bits in the interrupt control
register must be properly set otherwise the internal interrupt associated with the timer will remain inactive.
The edge select, timer mode and clock source control
bits in timer control register must also be correctly set to
ensure the timer is properly configured for the required
application. It is also important to ensure that an initial
value is first loaded into the timer registers before the
timer is switched on; this is because after power-on the
initial values of the timer registers are unknown. After
the timer has been initialized the timer can be turned on
and off by controlling the enable bit in the timer control
Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
Timer Program Example
This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The
Timer/Event Counter can be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as
the clock source. Show how to counter TMR0=1kHz, TMR1=2kHz, TMR2=4kHz, if fOSC is 11.059MHz.
org 00h
; Reset
jmp begin
org 04h
; external interrupt vector
reti
org 08h
; Timer/Event Counter 0 interrupt vector
jmp tmr0int
; jump here when Timer0 overflows
org 0ch
; Timer/Event Counter 1 interrupt vector
jmp tmr1int
; jump here when Timer1 overflows
org 10h
; Timer Counter 2 interrupt vector
jmp tmr2int
; jump here when Timer2 overflows
org 20h
; main program
;internal Timer0,1,2 Counter interrupt routine
tmr0int:
; Timer/Event Counter 0 main program placed here
:
reti
tmr1int:
; Timer/Event Counter 1 main program placed here
:
reti
tmr2int:
; Timer Counter 2 main program placed here
:
reti
:
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HT37B90/HT37B70/HT37B50/HT37B30
begin:
; setup interrupt register
mov a, 0bh
; enable master interrupt, timer0 and timer1 interrupt
mov intc,a
mov a, 01h
; enable timer2 interrupt
mov intch,a
;setup Timer 0 registers
mov a, low (65536-1382)
mov TMR0L,a;
mov a, high (65536-1382)
mov TMR0H,a;
mov a,080h
mov tmr0c,a
set tmr0c.4
mov
mov
mov
mov
set
a, low (256-173)
TMR1,a;
a,080h
tmr1c,a
tmr1c.4
mov
mov
mov
mov
set
a, low (256-173)
TMR2,a;
a,080h
tmr2c,a
tmr2c.4
; setup Timer preload low byte value, interrupt in 1kHz
; setup Timer preload high byte value
; setup Timer 0 control register
; timer mode and clock source is fOSC/8 ® 0.7234ms
; start Timer - note mode bits must be previously setup
; setup Timer preload value, interrupt in 2kHz
; setup Timer 1control register
; timer mode and Prescaler output is fOSC/32 ® 2.89ms
; start Timer - note mode bits must be previously setup
; setup Timer preload value, interrupt in 4kHz
; setup Timer2 control register
; timer mode and Prescaler output is fOSC/16 ® 1.447ms
; start Timer - note mode bits must be previously setup
Interrupts
Interrupt Operation
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter 0/1/2 or ERCOCI require or an ADPCM empty requires microcontroller attention, their corresponding interrupt will enforce a
temporary suspension of the main program allowing the
microcontroller to direct attention to their respective
needs. Each device in this series contains a single external interrupt and two internal interrupts functions. The
external interrupt is controlled by the action of the external INT pin, while the internal interrupts are controlled by
the Timer/Event 0/1Counter overflow or ERCOCI require or the ADPCM empty interrupt. Timer 2 counter
overflow interrupt share with UART. Using the UART interrupt require is defined by enable UART function enable configuration option.
Timer/Event 0/1/2 Counter overflow, UART interrupt,
ERCOCI interrupt, ADPCM empty request or the external interrupt line being pulled low will all generate an interrupt request by setting their corresponding request
flag, if their appropriate interrupt enable bit is set. When
this happens, the Program Counter, which stores the
address of the next instruction to be executed, will be
transferred onto the stack. The Program Counter will
then be loaded with a new address which will be the
value of the corresponding interrupt vector. The
microcontroller will then fetch its next instruction from
this interrupt vector. The instruction at this vector will
usually be a JMP statement which will jump to another
section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be
terminated with a RETI statement, which retrieves the
original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred.
Interrupt Register
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by INTC and
INTCH registers, which are located in Data Memory. By
controlling the appropriate enable bits in this register
each individual interrupt can be enabled or disabled.
Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global
enable flag if cleared to zero will disable all interrupts.
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Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically.
Interrupt Source
This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
T 0 F
E IF
E T 1 I
E T 0 I
E E I
Reset
1
00H
External Interrupt
2
04H
Timer/Event Counter 0 Overflow
3
08H
Timer/Event Counter 1 Overflow
4
0CH
Timer Counter 2 overflow or UART
Interrupt
5
10H
ERCOCI Interrupt
6
14H
ADPCM Empty Interrupt
7
18H
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI,
must first be set. An actual external interrupt will take
place when the external interrupt request flag, EIF, is
set, a situation that will occur when a high to low transition appears on the INT line. The external interrupt pin is
pin-shared with the I/O pin PA5 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the INTC register has been
set. The pin must also be selected as by setting the corresponding PAC.5 bit in the port control register. When
the interrupt is enabled, the stack is not full and a high to
low transition appears on the external interrupt pin, a
subroutine call to the external interrupt vector at location
04H, will take place. When the interrupt is serviced, the
external interrupt request flag, EIF, will be automatically
reset and the EMI bit will be automatically cleared to disable other interrupts.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit. In cases where
both external and internal interrupts are enabled and
where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority
and will therefore be serviced first. Suitable masking of
the individual interrupts using the INTC register can prevent simultaneous occurrences.
T 1 F
Vector
External Interrupt
Interrupt Priority
b 7
Priority
b 0
E M I
IN T C
R e g is te r
M a s te r In te r r u p t G lo b a l E n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 0 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 1 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 0 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o im p le m e n te d , r e a d a s " 0 "
Interrupt Low Byte Control Register
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HT37B90/HT37B70/HT37B50/HT37B30
b 7
C H 1 F A D P C M F
R C O C F
T 2 F
C H 0 F E A D P C M
b 0
E R C O C I E T 2 I IN T C H R e g is te r
T im e r C o u n te r 2 In te r r u p t E n a b le
1 : e n a b le d
0 : d is a b le d
C /R to F In te r r u p t E n a b le
1 : e n a b le d
0 : d is a b le d
A D P C M E m p ty In te r r u p t E n a b le
1 : e n a b le d
0 : d is a b le d
A D P C M C h a n n e l 0 E m p ty In te r r u p t R e q u e s t F la g
1 : e n a b le d
0 : d is a b le d
T im e r C o u n te r 2 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
C /R to F In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
A D P C M E m p ty In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
A D P C M C h a n n e l 1 E m p ty In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
Interrupt High Byte Control Register
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
T im e r C o u n te r 2 ( U A R T )
In te r r u p t R e q u e s t F la g T 2 F
E T 2 I
E M I
P r io r ity
H ig h
In te rru p t
P o llin g
C /R to F (E R C O C I)
In te r r u p t R e q u e s t F la g R C O C F
R C O C F
A D P C M E m p ty In te rru p t
R e q u e s t F la g A D P C M F
E A D P C M
L o w
Interrupt Structure
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HT37B90/HT37B70/HT37B50/HT37B30
Timer/Event Counter Interrupts
RC/F Interrupt
For a timer generated internal interrupt to occur, the corresponding internal interrupt enable bit must be first set.
Each device have two internal Timer Counters, the
Timer/Event Counter 0 interrupt enable is bit 2 of the
INTC register and known as ET0I, the Timer/Event Counter 1 interrupt enable is bit 3 of the INTC register and
known as ET1I and the Timer Counter 2 interrupt enable
is bit 0 of the INTCH register and is known as ET2I. An
actual Timer/Event Counter interrupt will be initialized
when the Timer/Event Counter interrupt request flag is
set, caused by a timer overflow. Each device has two timers, the Timer/Event Counter 0 request flag is bit 5 of the
INTC register and known as T0F, the Timer/Event Counter 1 request flag is bit 6 of the INTC register and known
as T1F, and the Timer Counter 2 request flag is bit 4 of the
INTCH register and is known as T2F.
The external RC Oscillation Converter interrupt is initialized by setting the external RC Oscillation Converter interrupt request flag, RCOCF; bit 5 of INTCH. This is
caused by a Timer A or Timer B overflow. When the interrupt is enabled, and the stack is not full and the
RCOCF bit is set, a subroutine call to location ²14H² will
occur.
The related interrupt request flag, RCOCF, will be reset
and the EMI bit cleared to disable further interrupts.
ADPCM Interrupt
The internal ADPCM interrupt is initialized by setting the
ADPCM interrupt request flag (ADPCMF: bit 6, CH0F:
bit 3 and CH1F: bit 7 of INTCH).The CH0F and CH1F
set by ADR0 or ADR1 empty respectively. The
ADPCMF is set by ADR0 or ADR1 empty immediately.
When the interrupt is enabled, and the stack is not full
and the T0F bit is set, a subroutine call to location 18H
will occur. The related interrupt request ADPCMF and
CH0F/CH1F flag will be reset and the EMI bit cleared to
disable further interrupts.
When the master interrupt global enable bit is set, the
stack is not full and the corresponding timer interrupt enable bit is set, an internal interrupt will be generated
when the corresponding timer overflows. Each device
have two internal Timer/Event Counters, a subroutine
call to location 08H will occur for Timer/Event Counter 0,
a subroutine call to location 0CH for Timer/Event Counter 1, a subroutine call to location 10H for Timer Counter
2. After entering the timer interrupt execution routine,
the corresponding timer interrupt request flag, either,
T0F, T1F or T2F will be reset and the EMI bit will be
cleared to disable other interrupts.
Programming Considerations
The interrupt request flags T0F, T1F, T2F, ADPCMF,
CH0F, CH1F, together with the interrupt enable bits
ET0I, ET1I, ET2I, EADPCM, form the interrupt control
registers INTC, INTCH which are located in the Data
Memory. By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the INTC or INTCH register until
the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
UART Interrupt
The device contain an internal UART function share with
Timer Counter 2. It_s corresponding UART interrupt
work by enabled UART function enable configuration
option, which is bit 7 of the UART function enable configuration option. An actual UART interrupt will be initialized when the UART interrupt request flag T2F is set,
which is bit 0 of the INTCH register. When the master interrupt global bit is set, the stack is not full and the corresponding ET2I interrupt enable bit is set, a UART
internal interrupt will be generated when a UART interrupt request occurs. This will create a subroutine call to
its corresponding vector location 010H. When a UART
internal interrupt occurs, the interrupt request flag T2F
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode. Only the
Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the
interrupt service program, which may corrupt the desired control sequence, then the contents should be
saved in advance.
will be reset and the EMI bit cleared to disable other interrupts. There are various UART conditions, which can
generate a UART interrupt, such as certain data transmission and reception conditions, overrun errors as well
as an address detect condition. These conditions are reflected by various flags within the UART_s status register, known as the RS232C register. Various bits in the
UART_s setup register, BRGR, determine if these flags
can generate a UART interrupt signal. More details on
these two registers and how they influence the operation of the UART interrupt can be found in the UART
section of the datasheet.
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Reset and Initialisation
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
V D D
0 .9 V
R E S
tR
S S T T im e - o u t
S T D
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of
this is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
V D D
1 0 0 k W
R E S
0 .1 m F
V S S
Basic Reset Circuit
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
0 .0 1 m F
1 0 0 k W
Reset Functions
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
1 0 k W
0 .1 m F
· Power-on Reset
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
Rev. 1.00
D D
V D D
R E S
V S S
Enhanced Reset Circuit
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
· RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
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HT37B90/HT37B70/HT37B50/HT37B30
R E S
0 .4 V
0 .9 V
D D
tR
S S T T im e - o u t
D D
Reset Initial Conditions
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
S T D
In te rn a l R e s e t
RES Reset Timing Chart
TO PDF
· Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option and
The VLVR can select as 3.0V or 2.4V. If the supply
voltage of the device drops to within a range of
0.9V~VLVR such as might occur when changing the
battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a
voltage in the range between 0.9V~VLVR must exist for
greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed
1ms, the LVR will ignore it and will not perform a reset
function.
L V R
S S T T im e - o u t
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
0
1
RES Wake-up HALT
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
Item
tR
S T D
In te rn a l R e s e t
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer/Event
Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will
be cleared
Low Voltage Reset Timing Chart
· Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
S S T T im e - o u t
Input/Output Ports I/O ports will be setup as inputs
Stack Pointer
tR
Condition After RESET
Program Counter
S T D
Stack Pointer will point to the top
of the stack
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure
reliable continuation of normal program execution after
a reset occurs, it is important to know what condition the
microcontroller is in after a particular reset occurs. The
following table describes how each type of reset affects
each of the microcontroller internal registers.
In te rn a l R e s e t
WDT Time-out Reset during Normal Operation
Timing Chart
· Watchdog Time-out Reset during Power Down
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
W D T T im e - o u t
S S T T im e - o u t
tS
S T
WDT Time-out Reset during Power Down
Timing Chart
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HT37B90
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
TMR0H
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1---
0000 1---
0000 1---
uuuu u---
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR2L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RBP1
---- -000
---- -000
---- -000
---- -uuu
RBP2
---- -000
---- -000
---- -000
---- -uuu
Register
BP1
--00 0000
--00 0000
--00 0000
--uu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBMP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP1
---- -xxx
---- -uuu
---- -uuu
---- -uuu
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTCH
1000 1000
1000 1000
1000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
1111 1111
1111 1111
1111 1111
uuuu uuuu
DAC
0000 0000
0000 0000
0000 0000
uuuu uuuu
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
CHAN
00-- 0000
00-- 0000
00-- 0000
uu-- uuuu
FreqNH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
FreqNL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
AddrL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RepH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Rev. 1.00
35
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
RepL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ENV
x-xx xxxx
u-uu uuuu
u-uu uuuu
u-uu uuuu
LVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
RVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0uuu
ADR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
XSPL
0000 0000
0000 0000
0000 0000
uuuu uuuu
XSPH
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADPC
00-0 --00
00-0 --00
00-0 --00
uu-u --uu
ADPS
---- 1111
---- 1111
---- 1111
---- uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --uu
ADRL
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
u1uu uuuu
ASCR
---- 0000
---- 0000
---- 0000
---- uuuu
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCCR
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCR
---- --00
---- --00
---- --00
---- --uu
LVDC
---- --00
---- --00
---- --00
---- --uu
SBCR
0110 0000
0110 0000
0110 0000
uuuu uuuu
SBDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RS232C
--10 --10
--10 --10
--10 --10
--uu --uu
RXD
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TXD
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRGR
0000 0000
0000 0000
0000 0000
uuuu uuuu
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.00
36
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
HT37B70
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
TMR0H
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1---
0000 1---
0000 1---
uuuu u---
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR2L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RBP1
---- --00
---- --00
---- --00
---- --uu
RBP2
---- --00
---- --00
---- --00
---- --uu
BP1
---0 0000
---0 0000
---0 0000
---u uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBMP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP1
---- --xx
---- --uu
---- --uu
---- --uu
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTCH
1000 1000
1000 1000
1000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PE
1111 1111
1111 1111
1111 1111
uuuu uuuu
PEC
1111 1111
1111 1111
1111 1111
uuuu uuuu
DAC
0000 0000
0000 0000
0000 0000
uuuu uuuu
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
CHAN
00-- 0000
00-- 0000
00-- 0000
uu-- uuuu
FreqNH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
FreqNL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
AddrL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RepH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
Rev. 1.00
37
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
RepL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ENV
x-xx xxxx
u-uu uuuu
u-uu uuuu
u-uu uuuu
LVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
RVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0uuu
ADR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
XSPL
0000 0000
0000 0000
0000 0000
uuuu uuuu
XSPH
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADPC
00-0 --00
00-0 --00
00-0 --00
uu-u --uu
ADPS
---- 1111
---- 1111
---- 1111
---- uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --uu
ADRL
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
u1uu uuuu
ASCR
---- 0000
---- 0000
---- 0000
---- uuuu
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCCR
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCR
---- --00
---- --00
---- --00
---- --uu
LVDC
---- --00
---- --00
---- --00
---- --uu
SBCR
0110 0000
0110 0000
0110 0000
uuuu uuuu
SBDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RS232C
--10 --10
--10 --10
--10 --10
--uu --uu
RXD
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TXD
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BRGR
0000 0000
0000 0000
0000 0000
uuuu uuuu
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.00
38
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
HT37B50
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
TMR0H
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1---
0000 1---
0000 1---
uuuu u---
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR2L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RBP1
---- --00
---- --00
---- --00
---- --uu
RBP2
---- --00
---- --00
---- --00
---- --uu
Register
BP1
---- 0000
---- 0000
---- 0000
---- uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBMP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBHP1
---- ---x
---- ---u
---- ---u
---- ---u
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTCH
1000 1000
1000 1000
1000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
uuuu uuuu
DAC
0000 0000
0000 0000
0000 0000
uuuu uuuu
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
CHAN
00-- 0000
00-- 0000
00-- 0000
uu-- uuuu
FreqNH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
FreqNL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrH
---x xxxx
---u uuuu
---u uuuu
---u uuuu
AddrL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RepH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RepL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ENV
x-xx xxxx
u-uu uuuu
u-uu uuuu
u-uu uuuu
Rev. 1.00
39
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
LVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0uuu
ADR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
XSPL
0000 0000
0000 0000
0000 0000
uuuu uuuu
XSPH
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADPC
00-0 --00
00-0 --00
00-0 --00
uu-u --uu
ADPS
---- 1111
---- 1111
---- 1111
---- uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --uu
ADRL
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
u1uu uuuu
ASCR
---- 0000
---- 0000
---- 0000
---- uuuu
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
Register
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCCR
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCR
---- --00
---- --00
---- --00
---- --uu
LVDC
---- --00
---- --00
---- --00
---- --uu
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.00
40
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
HT37B30
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
TMR0H
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
0000 1---
0000 1---
0000 1---
uuuu u---
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR2L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR2C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RBP1
---- --00
---- --00
---- --00
---- --uu
RBP2
---- --00
---- --00
---- --00
---- --uu
BP1
---- -000
---- -000
---- -000
---- -uuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBMP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
STATUS
--00 xxxx
--uu uuuu
--1u uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTCH
1000 1000
1000 1000
1000 1000
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
uuuu uuuu
DAC
0000 0000
0000 0000
0000 0000
uuuu uuuu
DAH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
DAL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
CHAN
00-- 0000
00-- 0000
00-- 0000
uu-- uuuu
FreqNH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
FreqNL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
AddrH
---- xxxx
---- uuuu
---- uuuu
---- uuuu
AddrL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RepH
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
RepL
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
ENV
x-xx xxxx
u-uu uuuu
u-uu uuuu
u-uu uuuu
LVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Rev. 1.00
41
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Register
Reset
(Power-on)
RES or LVR
Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
RVC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0uuu
ADR
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
XSPL
0000 0000
0000 0000
0000 0000
uuuu uuuu
XSPH
0000 0000
0000 0000
0000 0000
uuuu uuuu
ADPC
00-0 --00
00-0 --00
00-0 --00
uu-u --uu
ADPS
---- 1111
---- 1111
---- 1111
---- uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --uu
ADRL
xxxx ----
xxxx ----
xxxx ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
u1uu uuuu
ASCR
---- 0000
---- 0000
---- 0000
---- uuuu
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCCR
0000 1---
0000 1---
0000 1---
uuuu u---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
RCOCR
---- --00
---- --00
---- --00
---- --uu
LVDC
---- --00
---- --00
---- --00
---- --uu
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.00
42
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application requirements. Two types of system clocks can be selected
while various clock source options for the Watchdog
Timer are provided for maximum flexibility. All oscillator
options are selected through the configuration options.
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
Ca
Cb
Rf
7pF~9pF
9pF~11pF
300kW
The two methods of generating the system clock are:
· External crystal/resonator oscillator
· External RC oscillator
Oscillator Internal Component Values
One of these two methods must be selected using the
configuration options.
External RC Oscillator
Using the external system RC oscillator requires that a
resistor, with a value between 82kW and 180kW, is connected between OSC1 and VSS. The generated system
clock divided by 8 will be provided on OSC2 as an output
which can be used for external synchronization purposes. Note that as the OSC2 output is an NMOS
open-drain type, a pull high resistor should be connected
if it to be used to monitor the internal frequency. Although
this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for
applications where timing is critical or where accurate oscillator frequencies are required. For the value of the external resistor. Note that it is the only microcontroller
internal circuitry together with the external resistor, that
determine the frequency of the oscillator. The external
capacitor shown on the diagram does not influence the
frequency of oscillation.
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
External Crystal/Resonator Oscillator
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most
resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
C 1
O S C 1
R p
C 2
R f
O S C 2
C a
C b
In te r n a l
O s c illa to r
C ir c u it
T o in te r n a l
c ir c u its
O S C 1
R
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
fO
Crystal/Resonator Oscillator
Rev. 1.00
S C
O S C
/8 N M O S O p e n D r a in
O S C 2
External RC Oscillator
43
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased current consumption. This also applies to devices which
have different package types, as there may be
undonbed pins, which must either be setup as outputs
or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which
are connected to I/O pins, which are setup as outputs.
These should be placed in a condition in which minimum
current is drawn or connected only to external circuits
that do not draw current, such as other CMOS inputs.
Also note that additional standby current will also be required if the configuration options have enabled the
Watchdog Timer internal oscillator.
Watchdog Timer Oscillator
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 65ms at 5V
requiring no external components. When the device enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
Power Down Mode and Wake-up
Power Down Mode
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode, also known as the HALT Mode or
Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely
low standby current level. This occurs because when
the device enters the Power Down Mode, the system
oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken
up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power
supply constantly maintained to keep the device in a
known condition but where the power supply capacity is
limited such as in battery applications.
Wake-up
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on Port A
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin
· The Data Memory contents and registers will maintain
their present condition.
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
oscillator. The WDT will stop if its clock source originates from the system clock.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
Rev. 1.00
44
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be
noted that when the system enters the Power Down
Mode, as the system clock is stopped, then the WDT
clock source will also be stopped. Therefore the WDT
will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate
in noisy environments, using the internal WDT oscillator
is therefore the recommended choice.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a
WDT time-out occurs, only the Program Counter and
Stack Pointer will be reset. Three methods can be
adopted to clear the contents of the WDT and the WDT
prescaler. The first is an external hardware reset, which
means a low level on the RES pin, the second is using
the watchdog software instructions and the third is via a
²HALT² instruction.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT
clock is supplied by one of two sources selected by configuration option: its own self contained dedicated internal WDT oscillator or fOSC/8. Note that if the WDT
configuration option has been disabled, then any instruction relating to its operation will result in no operation.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use
the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will
clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed to
successfully clear the WDT. Note that for this second
option, if ²CLR WDT1² is used to clear the WDT, successive executions of this instruction will have no effect,
only the execution of a ²CLR WDT2² instruction will
clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
The internal WDT oscillator has an approximate period
of 65ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal
period of 17ms. Note that this period can vary with VDD,
temperature and process variations. For longer WDT
time-out periods the WDT prescaler can be utilized. By
writing the required value to bits 0, 1 and 2 of the WDTS
register, known as WS0, WS1 and WS2, longer time-out
periods can be achieved. With WS0, WS1 and WS2 all
equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s.
A configuration option can select the instruction clock,
which is the system clock divided by 8, as the WDTclock
b 7
W S 2
W S 1
b 0
W S 0
W D T S R e g is te r
W D T p r e s c a le r r a te s e le c t
W D T
W S 0
W S 1
W S 2
1
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
1
1
1
:1
R a te
:2
:4
:8
:1 6
:3 2
:6 4
:1 2 8
N o t u s e d
Watchdog Timer Register
Rev. 1.00
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June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
C L R W D T 1 F la g
C L R W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fO
S C
/8
W D T O s c illa to r
C L R
W D T C lo c k S o u r c e
C o n fig u r a tio n O p tio n
C L R
8 - b it C o u n te r
(¸ 2 5 6 )
7 - b it P r e s c a le r
W D T C lo c k S o u r c e
W S 0 ~ W S 2
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
Digital to Analog Converter (DACC)
The two D/A converters of HT37B90/70/50/30 are 16-bit high-resolution with excellent frequency response characteristics and good power consumption for stereo audio output.
D7
D6
D5
D4
D3
D2
D1
D0
1Dh
DAC High Byte
B15
B14
B13
B12
B11
B10
B9
B8
1Eh
DAC Low Byte
B7
B6
B5
B4
B3
B2
B1
B0
1Fh
DAC Control (DACC)
DAC
SELWR
BP_R
SELACH1 SELACH0 AMP_M AMP_EN SELWL
Note: B15~B0 is D/A conversion result data bit MSB~LSB.
b 7
B P _ R
S E L A C H 1
S E L A C H 0
A M P _ M
A M P _ E N
S E L W L
D A C
b 0
S E L W R
D A C C
R e g is te r
T o s e le c t D A R d a ta fr o m
0 : fr o m M C U ( d e fa u lt)
1 : fr o m w a v e ta b le
M C U o r w a v e ta b le
T o s e le c t D A L d a ta fr o m
0 : fr o m M C U ( d e fa u lt)
1 : fr o m w a v e ta b le
M C U o r w a v e ta b le
E n a b le /d is a b le D A C fu n c tio n
0 : d is a b le
1 : e n a b le
E n a b le /d is a b le b u ild - in p o w e r A m p . fu n c tio n
0 : d is a b le
1 : e n a b le
M u te fu n c tio n in th e b u ild - in p o w e r A m p .
0 : n o n -m u te
1 : m u te
S e le c t c h 0 s o u r c e fr o m w a v e ta b le /A D P C M
0 : fr o m w a v e ta b le
1 : fro m A D P C M d e c o d e r
S e le c t c h 0 1 s o u r c e fr o m
0 : fr o m w a v e ta b le
1 : fro m a d p c m d e c o d e r
w a v e ta b le /A D P C M
* In d ir e c t m e m o r y a c c e s s s fr o m
0 : M P 1
1 : M P 2
d e c o d e r
d e c o d e r
M P 1 /M P 2
DACC (1FH) Register
Note:
*Switch MP1and MP2 memory pointer by BP_R
Rev. 1.00
46
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
The Integrated Power Amp.
SP0: Audio Negative output
The Power Amp. is an integrated class AB mono
speaker driver contained in HT37B90/70/50/30. It provides property of high S/N ratio, high slew rate, low distortion, large output voltage swing, excellent power
supply ripple rejection, low power consumption, low
standby current and power off control etc.
SP1: Audio Positive output
OUTP Rising Time (tR)
When AMP_EN enable, the Power Amp. need rising
time to output fully on OUTP pin. However, the rising
time depends on.
S P 0
S P K
L C H /R C H
C1. (*The C1 connects with VBIAS and Vss)
S P 1
0 .1 m F
1 0 R
R
A M P 1
A u d In
C 1
V
B IA S
B IA S
A M P _ E N
R
A M P 2
O U T P
R
A M P _ E N
tR
Aud In: Audio input
VBIAS: Speaker non-inverting input voltage reference
Capacitor
tR
0.1mF
1mF
4.7mF
10mF
2.2V
15ms
30ms
90ms
185ms
3V
15ms
30ms
90ms
185ms
4
15ms
30ms
90ms
185ms
Voltage
For battery based applications, power consumption is a key issue, therefore the amplifier should be turned off when in
the standby state. In order to eliminate any speaker sound bursts while turning the amplifier on, the application circuit,
which will incorporate a capacitance value of C1, should be adjusted in accordance with the speaker s audio frequency
response. A greater value of C1 will improve the noise burst while turning on the amplifier. The recommended operation
sequence is:
Turn On: audio signal standby (1/2VDD) ® enable amplifier ® wait tR for amplifier ready ® audio output
Turn Off: audio signal finished ® disable amplifier ® wait tR for amplifier off ® audio signal off
L C H /R C H
tR
tR
A M P _ E N
If the application is not powered by batteries and there is no problem with amplifier On/Off issue, a capacitor value of
0.1mF for C1 is recommended.
How to use integrated power Amp?
· Connect the ²Internal Power Amp Circuit², please refer to Application Circuits.
· Set DACC.3 to enable integrated power amp. Clear DACC.3 to disable integrated power amp.
· User can control it at ²PowerAmpDisable² and ²PowerAmpEnable² of HT-MDS.
Rev. 1.00
47
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Music Synthesis Controller - MSC
CH0~CH15 Channel Number Selection
Waveform Format Definition
Each devices with integrated 16 channels output is selected by 4bits option and CHAN[3:0] is used to define
which channel is selected. When this register is written
to, the wavetable synthesizer will automatically output
the dedicated PCM code. So this register is also used as
a start playing key and it has to be written to after all the
other wavetable function registers are already defined.
Each device accepts two waveform formats to ensure a
more economical data space. WBS is used to define the
sample format of each PCM code.
WBS=0 means the sample format is 8-bit (PCM8)
WBS=1 means the sample format is 12-bit (PCM12)
The 12-bit sample format allocates location to each
sample data. Please refer to the waveform format statement as shown below.
Change Parameter Selection
8 - B it
These two bits, VM and FR, are used to define which
register will be updated on this selected channel. There
are two modes that can be selected to reduce the process of setting the register. Please refer to the statements of the following table:
VM
FR
0
0
Update all the parameter
0
1
Only change the frequency parameter
1
0
Only change the volume parameter
1
1
Unused
1 2 - B it
3 B
4 B
5 B
6 B
7 B
8 B
1 H
1 M
1 L
2 L
2 H
2 M
3 H
3 M
3 L
A s a m p lin g d a ta c o d e
N o te : " 1 H " H ig h N ib b le
" 1 M " M id d le N ib b le
" 1 L " L o w N ib b le
Repeat Number Definition
The repeat number is used to define the address which
is the repeat point of the sample. When the repeat number is defined, it will be output from the start code to the
end code once and always output the range between
the repeat address to the end code (80H) until the volume become close. The RE14~RE0 is used to calculate
the repeat address of the PCM code. The process for
setting the RE14~RE0 is to write the 2¢s complement of
the repeat length to RE14~RE0, with the highest carry
ignored. The HT37 will get the repeat address by adding
the RE14~RE0 to the address of the end code, then
jump to the address to repeat this range.
Output Frequency Definition
The data on BL3~BL0 and FR11~FR0 are used to define the output speed of the PCM file, i.e. it can be used
to generate the tone scale. When the FR11~FR0 is
800H and BL3~BL0 is 6H, each sample data of the PCM
code will be sent out sequentially.
When the fOSC is 12.8MHz, the formula of a tone frequency is:
f / (16x16) FR11 ~ FR0
fOUT= fRECORD x osc
x (17 - BL3~BL0)
SR
2
where fOUT is the output signal frequency, fRECORD and SR
is the frequency and sampling rate on the sample code,
respectively.
Volume Control
Each device provides the volume control independently.
The volume are controlled by VR9~VR0 respectively.
The chip provides 1024 levels of controllable volume,
the 000H is the maximum and 3FFH is the minimum output volume. The PCM code definition Each device can
only solve the voice format of the signed 8-bit or 12-bit
raw PCM. And the MCU will take the voice code 80H as
the end code. So each PCM code section must be
ended with the end code 80H.
So if a voice code of C3 has been recorded which has
the fRECORD of 261Hz and the SR of 11025Hz, the tone
frequency (fOUT) of G3: fOUT=98Hz. Can be obtained by
using the formula: If FR=55h and BL=7, could get 98Hz.
50kHz
FR11 ~ FR0
x
11.025kHz 2 (17 - BL3~BL0)
BL3~BL0: range from 00h~0Bh
FR11~FR0: range from 000h~3FFh
Rev. 1.00
2 B
A s a m p lin g d a ta c o d e ; B m e a n s o n e d a ta b y te .
Function
98Hz= 261Hz x
1 B
48
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
D7
D6
D5
D4
D3
D2
D1
D0
20H
Name
Channel number selection (CHAN)
Function
VM
FR
¾
¾
CH3
CH2
CH1
CH0
21H
Frequency number high byte (FreqNH)
BL3
BL2
BL1
BL0
FR11 FR10
FR9
FR8
22H
Frequency number low byte (FreqNL)
FR7
FR6
FR5
FR4
FR3
FR2
FR1
FR0
23H
Start address high byte (AddrH)
¾
ST14
ST13
ST12
ST11
ST10
ST9
ST8
24H
Start address low byte (AddrL)
ST7
ST6
ST5
ST4
ST3
ST2
ST1
ST0
25H
Repeat number high byte (RepH)
WBS
RE14 RE13 RE12 RE11 RE10
RE9
RE8
26H
Repeat number low byte (RepL)
RE7
RE6
RE5
RE4
RE1
RE0
27H
Control register (ENV)
A_R
¾
VL9
VL8
VR9
VR8
29H
Left volume control (LVC)
VL7
VL6
VL5
VL4
VL3
VL2
VL1
VL0
2AH
Right volume control (RVC)
VR7
VR6
VR5
VR4
VR3
VR2
VR1
VR0
RE3
RE2
ENV1 ENV0
¾
28H
Wavetable Register Memory Map (20H~2AH)
ADPCM
Address Offset
Register Name
R/W
Default Value
Description
30H
ADR
W
xxxx xxxx
ADPCM Data Register
31H
XSPL
W
0000 0000
Xn + SP Initial Register Low Byte
32H
XSPH
W
0000 0000
Xn + SP Initial Register High Byte
33H
ADPC
R/W
00x0 xx00
ADPCM Decoder control register
34H
ADPS
R
0000 1111
ADPCM Decoder Status Register
HT-ADPCM Decoder Registers
b 7
W B R 1 _ E m p ty
W B R 0 _ E m p ty
A D R 1 _ E m p ty
b 0
A D R 0 _ E m p ty
A D P S R e g is te r
V o ic e c h a n n e l 0 , A D P C M
0 : n o n e m p ty
1 : e m p ty
V o ic e c h a n n e l 1 , A D P C M
0 : n o n e m p ty
1 : e m p ty
V o ic e c h a n n e l 0 , W B R
0 : n o n e m p ty
1 : e m p ty
V o
0 :
1 :
N o
D a ta E m p ty F la g
D a ta E m p ty F la g
D a ta E m p ty F la g
ic e c h a n n e l 1 , W B R D a ta E m p ty F la g
n o n e m p ty
e m p ty
t im p le m e n te d , r e a d a s " 0 "
ADPS (34H) - ADPCM Status Register
Rev. 1.00
49
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
External RC Oscillation Converter
ternal RC oscillator is the clock source input to TMRBH
and TMRBL. The OVB bit, which is bit 0 of the RCOCR
register, decides whether the timer interrupt is sourced
from either the Timer A overflows or Timer B overflow.
When a timer overflow occurs, the RCOCF bit is set and
an external RC oscillation converter interrupt occurs.
When the RC oscillation converter Timer A or Timer B
overflows, the RCOCON bit is automatically reset to
zero and stops counting.
An external RC oscillation converter is implemented in
certain devices and is a function which allows touch
switch functions to be implemented. When used in conjunction with the Analog Switch function up to eight
touch switches can be implemented.
External RC Oscillation Converter Operation
The RC oscillation converter is composed of two 16-bit
count-up programmable timers. One is Timer A and the
other is counter known as Timer B. The RC oscillation
converter is enabled when the RCO bit, which is bit 1 of
the RCOCR register, is set high. The RC oscillation converter will then be composed of four registers, TMRAL,
TMRAH, TMRBL and TMRBH. The Timer A clock
source comes from the fSYS or fSYS/4, the choice of which
is determined by bits in the RCOCCR register. The RC
oscillation converter Timer B clock source comes from
an external RC oscillator. As the oscillation frequency is
dependent upon external capacitance and resistance
values, it can therefore be used to detect the increased
capacitance of a touch switch pad.
The resistor and capacitor form an oscillation circuit and
input to TMRBH and TMRBL. The RCOM0, RCOM1
and RCOM2 bits of RCOCCR define the clock source of
Timer A.
When the RCOCON bit, which is bit 4 of the RCOCCR
register, is set high, Timer A and Timer B will start counting until Timer A or Timer B overflows. Now the timer
counter will generate an interrupt request flag which is
bit RCOCF, bit 5 of the INTCH register. Both Timer A and
Timer B will then stop counting and the RCOCON bit will
automatically be reset to ²0² at the same time. Note that
if the RCOCON bit is high, the TMRAH, TMRAL,
TMRBH and TMRBL registers cannot be read or written
to.
There are six registers related to the RC oscillation converter. These are, TMR2H, TMR2L, RCOCCR, TMR4H,
TMR4L and RCOCR. The internal timer clock is the input clock source for TMRAH and TMRAL, while the ex-
b 7
R C O M 2 R C O M 1 R C O M 0
b 0
R C O C O N
R C O C C R R e g is te r
U n d e fin e d , r e a d a s z e r o
C a n w r ite a n d r e a d , D e fa u lt a s " 1 "
R C O s c illa to r C o n v e r te r E n a b le
1 : E n a b le
0 : D is a b le
T im e r A C lo c k S o u r c e S e le c t
R C O M 2
R C O M 1
R C O M 0
0
0
0
0
0
1
0
1
0
:
:
:
1
1
1
fS Y S (fO S C /2 )
fS Y S /4 (fO S C /8 )
U n d e fin e d
:
U n d e fin e d
RCOCCR Register
b 7
O V B
b 0
R C O
R C O C R R e g is te r
In te r r u p t S o u r c e S e le c t
1 : T im e r B o v e r flo w
0 : T im e r A o v e r flo w
R C C o n v e rte r M o d e
1 : E n a b le
0 : D is a b le
U n d e fin e d , r e a d a s z e r o
RCOCR Register
Rev. 1.00
50
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
S y s te m
S y s te m
C lo c k
C lo c k /4
S 1
S 2
T im e r A
T O N
T im e r B
R C O S C
O V B = 0
E x te r n a l R C O s c illa tio n C o n v e r te r In te r r u p t
O V B = 1
R e s e t R C O C O N
O u tp u t
Programming Considerations
directly written to the high byte register. At the same
time the data in the low byte buffer will be transferred
into its associated low byte register. For this reason,
when preloading data into the 16-bit timer registers, the
low byte should be written first. It must also be noted that
to read the contents of the low byte register, a read to
the high byte register must first be executed to latch the
contents of the low byte buffer into its associated low
byte register. After this has been done, the low byte register can be read in the normal way. Note that reading
the low byte timer register will only result in reading the
previously latched contents of the low byte buffer and
not the actual contents of the low byte timer register.
As the 16-bit Timers have both low byte and high byte
timer registers, accessing these registers is carried out
in a specific way. It must be noted that when using instructions to preload data into the low byte registers,
namely TMRAL or TMRAL, the data will only be placed
into a low byte buffer and not directly into the low byte
register. The actual transfer of the data into the low byte
register is only carried out when a write to its associated
high byte register, namely TMRAH or TMRBH, is executed. However, using instructions to preload data into
the high byte timer register will result in the data being
Program Example
External RC oscillation converter mode example program - Timer A overflow:
clr RCOCCR
mov a, 00000010b
;
mov RCOCR,a
clr intch.5
;
mov a, low (65536-1000) ;
mov tmral, a
;
mov a, high (65536-1000)
mov tmrah, a
mov a, 00h
;
mov tmrbl, a
mov a, 00h
mov tmrbh, a
mov a, 00110000b
;
mov RCOCCR, a
p10:
clr wdt
Snz intch.5
;
jmp p10
clr intch.5
;
; Program continue
Rev. 1.00
Enable External RC oscillation mode and set Timer A overflow
Clear External RC Oscillation Converter interrupt request flag
Give timer A initial value
Timer A count 1000 time and then overflow
Give timer B initial value
Timer A clock source=fSYS/4 and timer on
Polling External RC Oscillation Converter interrupt request flag
Clear External RC Oscillation Converter interrupt request flag
51
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Analog Switch
There are 8 analog switch lines in the microcontroller for K0~K7 for HT37B90/70/50/30 and the Analog Switch control
register, which is mapped to the data memory. All of these Analog Switch lines can be used for touch key input keys.
b 7
b 0
A S O N 3 A S O N 2 A S O N 1 A S O N 0
A S C R R e g is te r
A n a lo g S w itc h S e le c t
A S O N 3 A S O N 2 A S O N 1
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
X
X
A S O N 0
0
1
0
1
0
1
0
1
X
K 0 o
K 1 o
K 2 o
K 3 o
K 4 o
K 5 o
K 6 o
K 7 o
A ll o
n ,
n ,
n ,
n ,
n ,
n ,
n ,
n ,
ff,
o th
o th
o th
o th
o th
o th
o th
o th
O S
e r
e r
e r
e r
e r
e r
e r
e r
s o
s o
s o
s o
s o
s o
s o
s o
C o ff
ff
ff
ff
ff
ff
ff
ff
ff
U n d e fin e d , r e a d a s z e r o
Analog Switch Control Register - ASCR
A S O N
K 0
T .G .1
K 2
T .G .3
K 1
T .G .2
K 3
T .G .4
K 4
T .G .5
K 5
T .G .6
K 6
T .G .7
K 7
T .G .8
R C O U T
R R
R C
C C
T im e r B
Analog Switch
Rev. 1.00
52
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Analog to Digital Converter
The need to interface to real world analog signals is a
common requirement for many electronic systems.
However, to properly process these signals by a
microcontroller, they must first be converted into digital
signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the
need for external components is reduced significantly
with the corresponding follow-on benefits of lower costs
and reduced component space requirements.
In the following tables, D0~D11 are the A/D conversion
data result bits.
A/D Overview
A/D Converter Control Register - ADCR
HT37B90/70/50/30 contains a 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control
signals and convert these signals directly into either a
12-bit digital value.
To control the function and operation of the A/D converter, a control register known as ADCR is provided.
This 8-bit register defines functions such as the selection of which analog channel is connected to the internal
A/D converter, which pins are used as analog inputs and
which are used as normal I/Os as well as controlling the
start function and monitoring the A/D converter end of
conversion status.
Device
HT37B90/70,
HT37B50/30
12
PB0~PB7
A/D Converter Data Registers - ADR, ADRL, ADRH
HT37B90/70/50/30 have a 12-bit A/D converter, two
registers are required, a high byte register, known as
ADRH, and a low byte register, known as ADRL. After
the conversion process takes place, these registers can
be directly read by the microcontroller to obtain the digitized conversion value. HT37B90/70/50/30 use two A/D
Converter Data Registers, note that only the high byte
register ADRH utilizes its full 8-bit contents. The low
byte register utilizes only 4 bit of its 8-bit contents as it
contains only the lower 4 bit of the 12-bit converted
value.
P B 0
P B 1
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
/A
/A
/A
/A
/A
/A
/A
/A
N 0
N 1
N 2
N 3
N 4
N 5
N 6
N 7
P C R 0 ~ P C R 2
P in C o n fig u r a tio n
B its
Bit
5
Bit
4
ADRL
D3
D2
D1
D0
¾
¾
¾
¾
ADRH
D11 D10 D9
D8
D7
D6
D5
D4
C h a n n e l S e le c t
B its
Bit
2
Bit
1
Bit
0
The ADCR control register also contains the
PCR2~PCR0 bits which determine which pins on Port A
are used as analog inputs for the A/D converter and
which pins are to be used as normal I/O pins. Note that if
the PCR2~PCR0 bits are all set to zero, then all the Port
B pins will be setup as normal I/Os and the internal A/D
converter circuitry will be powered off to reduce the
power consumption.
¸ 4 ~
¸ 1 2
C lo c k D iv id e R a tio
A C S R
V
S T A R T
R e g is te r
C C A 3
A /D r e fe r e n c e v o lta g e
A D R L
A D C
A D C S 0 ~ A D C S 2
Bit
3
One section of this register contains the bits
ACS2~ACS0 which define the channel number. As
each of the devices contains only one actual analog to
digital converter circuit, each of the individual 8 analog
inputs must be routed to the converter. It is the function
of the ACS2~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the
internal A/D converter.
The following diagram shows the overall internal structure of the A/D converter, together with its associated
registers.
A D C S o u rc e
fO S C
Bit
6
A/D Data Register
Input
Conversion
Input Pins
Channels
Bits
8
Bit
7
Register
A D R H
E O C
A /D D a ta
R e g is te r s
A D C R
R e g is te r
S ta rt a n d E n d o f
C o n v e r s io n B its
A/D Converter Structure
Rev. 1.00
53
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
A/D Converter Clock Source Register - ACSR
The START bit in the ADCR register is used to start and
reset the A/D converter. When the microcontroller sets
this bit from low to high and then low again, an analog to
digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOCB bit in the ADCR register will be set high and
the analog to digital converter will be reset. It is the
START bit that is used to control the overall on/off operation of the internal analog to digital converter.
The clock source for the A/D converter, which originates
from the system clock fOSC, is first divided by a division
ratio, the value of which is determined by the ADCS1
and ADCS0 bits in the ACSR register.
Although the A/D clock source is determined by the system clock fOSC, and by bits ADCS1 and ADCS0, there
are some limitations on the maximum A/D clock source
speed that can be selected. Refer to the following table.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is complete. This bit will be automatically cleared to zero by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detecting the end of an A/D conversion cycle.
b 7
S T A R T E O C B
P C R 2
P C R 1
P C R 0
A C S 2
A C S 1
b 0
A C S 0
ACS3
ACS2
ACS1
ACS0
Analog Channel
0
0
0
0
AN0
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
ACS Table: A/D Channel Select Table
A D C R
R e g is te r
S e le c t A /D c h a n n e l
T h e d e ta il r e fe r e n c e A C S ta b le
P o r t B A /D c h a n n e l c o n fig u r a tio n s
T h e d e ta il r e fe r e n c e P C R ta b le
E n d o f A /D c o n v e r s io n fla g
1 : n o t e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n w a itin g o r in p r o g r e s s
0 : e n d o f A /D c o n v e r s io n - A /D c o n v e r s io n e n d e d
S ta r t th e A /D c o n v e r s io n
0 ® 1 ® 0 : S ta rt
0 ® 1 : R e s e t A /D c o n v e rte r a n d s e t E O C B to "1 "
ADCR Register
b 7
T E S T
b 0
A D C S 1 A D C S 0
A C S R R e g is te r
S e le c t A /D c o n v e r te r
A D C S 1
A D C S 0
0
0
:
:
0
1
1
0
:
1
1
:
c lo c k s o u r c e
fO
fO
fO
fO
S C
S C
S C
S C
/4
/6
/8
/1 2
N o t im p le m e n te d , r e a d a s " 0 "
F o r te s t m o d e u s e o n ly
ACSR Register
Rev. 1.00
54
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
AN0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
AN1
AN0
0
1
1
PB7
PB6
PB5
PB4
PB3
AN2
AN1
AN0
1
0
0
PB7
PB6
PB5
PB4
AN3
AN2
AN1
PB0
1
0
1
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
0
PB7
PB6
AN5
AN4
AN3
AN2
AN1
AN0
1
1
1
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
PCR Table: Port A/D Channel Configuration Table
A/D Clock Period (tAD)
fOSC
ADCS1, ADCS0=00
(fOSC/4)
ADCS1, ADCS0=01
(fOSC/6)
ADCS1, ADCS0=10
(fOSC/8)
ADCS1, ADCS0=11
(fOSC/12)
8MHz
¾
¾
1ms
1.5ms
11.059MHz
¾
¾
¾
1.08ms
12MHz
¾
¾
¾
1ms
A/D Clock Period Examples
A/D Input Pins
Initialising the A/D Converter
All of the A/D analog input pins are pin-shared with the
I/O pins on Port B. Bits PCR2~PCR0 in the ACSR registers, not configuration options, determine whether the
input pins are setup as normal Port B input/output pins
or whether they are setup as analog inputs. In this way,
pins can be changed under program control to change
their function from normal I/O operation to analog inputs
and vice versa. Pull-high resistors, which are setup
through configuration options, apply to the input pins
only when they are used as normal I/O pins, if setup as
A/D inputs the pull-high resistors will be automatically
disconnected. Note that it is not necessary to first setup
the A/D pin as an input in the PBC port control register to
enable the A/D input, when the PCR2~PCR0 bits enable an A/D input, the status of the port control register
will be overridden.
The internal A/D converter must be initialized in a special
way. Each time the Port B A/D channel selection bits are
modified by the program, the A/D converter must be
re-initialised. If the A/D converter is not initialized after the
channel selection bits are changed, the EOCB flag may
have an undefined value, which may produce a false end
of conversion signal. To initialize the A/D converter after
the channel selection bits have changed, then, within a
time frame of one to ten instruction cycles, the START bit
in the ADCR register must first be set high and then immediately cleared to zero. This will ensure that the EOCB
flag is correctly set to a high condition.
The VDD power supply pin is used as the A/D converter
reference voltage, and as such analog inputs must not
be allowed to exceed this value. Appropriate measures
should also be taken to ensure that the VDD pin remains
as stable and noise free as possible.
Rev. 1.00
55
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
· Step 4
Summary of A/D Conversion Steps
The analog to digital conversion process can now be
initialised by setting the START bit in the ADCR register from ²0² to ²1² and then to ²0² again. Note that this
bit should have been originally set to ²0².
The following summarizes the individual steps that
should be executed in order to implement an A/D conversion process.
· Step 1
· Step 5
Select the required A/D conversion clock by correctly
programming bits ADCS1 and ADCS0 in the ACSR
register.
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR register
can be polled. The conversion process is complete
when this bit goes low. When this occurs the A/D data
registers ADRL and ADRH can be read to obtain the
conversion value.
· Step 2
Select which channel is to be connected to the internal
A/D converter by correctly programming the
ACS2~ACS0 bits which are also contained in the
ADCR register.
The following timing diagram shows graphically the various stages involved in an analog to digital conversion
process and its associated timing.
· Step 3
Select which pins on Port B are to be used as A/D inputs and configure them as A/D input pins by correctly
programming the PCR2~PCR0 bits in the ADCR register. Note that this step can be combined with Step 2
into ADCR registers programming operation.
S T A R T b it s e t h ig h w ith in o n e to te n in s tr u c tio n c y c le s a fte r th e P C R 0 ~ P C R 2 b its c h a n g e s ta te
S T A R T
E O C B
A /D s a m p lin g tim e
3 2 tA D
P C R 2 ~
P C R 0
A C S 2 ~
A C S 0
0 0 0 B
A /D s a m p lin g t im e
3 2 tA D
A /D s a m p lin g t im e
3 2 tA D
0 1 1 B
0 0 0 B
P o w e r-o n
R e s e t
R e s e t A /D
c o n v e rte r
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
1 0 0 B
0 1 0 B
0 0 0 B
0 0 1 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
tA D C
A /D c o n v e r s io n tim e
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
A /D
tA D C
c o n v e r s io n tim e
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
D o n 't c a r e
E n d o f A /D
c o n v e r s io n
tA D C
A /D c o n v e r s io n tim e
A/D Conversion Timing
Rev. 1.00
56
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
SPI Serial Interface
There are two SPI interfaces, with each interface containing four basic signals and pins. These are SDI (serial data input), SDO (serial data output), SCK (serial clock) and SCS (slave select pin).
S C S
S C K
S D I
S D O
S B C R
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7
C K S
D E F A U L T
D 5
M 0
D 4
S B E N
D 3
D 2
M L S
C S E N
D 1
W C O L
D 0
T R F
S B C R
: S E R IA L B U S
0
1
1
0
0
0
0
0
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
S B D R
U
U
U
U
U
U
U
U
D A T A R E G IS T E R
D E F A U L T
S B D R
D 6
M 1
C O N T R O L R E G IS T E R
: S E R IA L B U S
N o te : "U " m e a n s u n c h a n g e d .
SPI Timing
Two corresponding registers, SBCR and SBDR are
unique to the serial interface and provide control, status,
and data storage.
¨
Bit3 (MLS) ® MSB or LSB (1/0) shift first control bit
¨
Bit2 (CSEN) ® serial bus selection signal enable/disable (SCS), when CSEN=0, SCSB is floating.
· SBCR: Serial bus control register
¨
Bit1 (WCOL) ® this bit is set to 1 if data is written to
the SBDR register (TXRX buffer) when data is
transferred, writing will be ignored if data is written
to SBDR (TXRX buffer) when data is transferred.
¨
Bit7 (CKS) clock source selection: fSIO=fOSC/2,
select as ²0². fSIO=fOSC, select as ²1².
¨
Bit6 (M1), Bit5 (M0) master/slave mode and baud
rate selection
M1, M0:
00 ® MASTER MODE, BAUD RATE= fSIO
01 ® MASTER MODE, BAUD RATE= fSIO/4
10 ® MASTER MODE, BAUD RATE= fSIO/16
11 ® SLAVE MODE
¨
Bit0 (TRF) ® data transferred or data received
used to generate an interrupt.
Note: data reception is still in operation when the MCU
enters the Power-down mode.
¨
· SBDR: Serial bus data register
Data written to SBDR ® write data to the TXRX buffer
only
Data read from SBDR ® read from SBDR only
Operating Mode description:
Master transmitter: clock transmission and data I/O
started by writing to SBDR
Master clock transmission initiated by writing to SBDR
Slave transmitter: data I/O started by clock reception
Slave receiver: data I/O started by clock reception
Bit4 (SBEN) ® serial bus enable/disable (1/0)
-
Enable: (SCS dependent on CSEN bit)
Disable ® enable: SCK, SDI, SDO, SCS= 0
(SCK= ²0²) and waiting for writing data to SBDR
(TXRX buffer)
Master mode: write data to SBDR (TXRX buffer)
start transmission/reception automatically
Master mode: when the data has been transferred, set TRF
Slave mode: when an SCK (and SCS dependent
on CSEN) is received, data in the TXRX buffer is
shifted-out and data on SDI is shifted-in.
-
Disable: SCK (SCK), SDI, SDO, SCS floating
Rev. 1.00
57
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Clock polarity= rising (SCK) or falling (SCK): 1 or 0 (mask option).
Modes
Operations
1.
2.
3.
4.
Master
5.
6.
7.
8.
9.
1.
2.
3.
4.
Slave
5.
6.
7.
8.
9.
Select CKS and select M1, M0 = 00,01,10
Select CSEN, MLS (the same as the slave)
Set SBEN
Writing data to SBDR ® data is stored in TXRX buffer ® output SCK (and SCS) signals ® go to
step 5 ® (SIO internal operation ® data stored in TXRX buffer, and SDI data is shifted into TXRX
buffer ® data transferred, data in TXRX buffer is latched into SBDR)
Check WCOL; WCOL= 1 ® clear WCOL and go to step 4; WCOL= 0 ® go to step 6
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
CKS don¢t care and select M1, M0= 11
Select CSEN, MLS (the same as the master)
Set SBEN
Writing data to SBDR ® data is stored in TXRX buffer ® waiting for master clock signal (and SCS):
SCK ® go to step 5 ® (SIO internal operations ® SCK (SCS) received ® output data in TXRX
buffer and SDI data is shifted into TXRX buffer ® data transferred, data in TXRX buffer is latched
into SBDR)
Check WCOL; WCOL= 1 ® clear WCOL, go to step 4; WCOL= 0 ® go to step 6
Check TRF or wait for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
Operation of Serial Interface
WCOL: master/slave mode, set while writing to SBDR
when data is transferring (transmitting or receiving) and
this writing will then be ignored. WCOL function can be
enabled/disabled by mask option. WCOL is set by SIO
and cleared by users.
has 2 options: CSEN mask option is used to enable/disable software CSEN function. If CSEN mask option is
disabled, the software CSEN is always disabled. If
CSEN mask option is enabled, software CSEN function
can be used.
Data transmission and reception are still working when
the MCU enters the HALT mode.
SBEN= 1 ® serial bus standby; SCS (CSEN= 1) = 1;
SCS= floating (CSEN= 0); SDI= floating; SDO= 1; master SCK= output 1/0 (dependent on CPOL mask option),
slave SCK= floating.
CPOL is used to select the clock polarity of SCK. It is a
mask option.
SBEN= 0 ® serial bus disabled; SCS=SDO=1,
SDI=SCK= floating in master mode, SDI=SDO=SCK=
floating, SCS=1 in slave mode.
MLS: MSB or LSB first selection.
CSEN: chip select function enable/disable, CSEN=1 ®
SCS signal function is active. Master should output SCS
signal before SCL signal is set and slave data transferring should be disabled (or enabled) before (after) SCS
signal is received. CSEN= 0, SCS signal is not needed,
SCS pin (master and slave) should be floating. CSEN
Rev. 1.00
TRF is set by SIO and cleared by users. When data
transfer (transmission and reception) is completed, TRF
is set to generate SBI (serial bus interrupt).
58
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
S B E N = 1 , C S E N = 1 a n d w r ite d a ta to S B D R
S C S
( if p u ll- h ig h e d )
C L K
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D I
D 7 /D 0 D 6 /D 1 D 5 /D 2 D 4 /D 3 D 3 /D 4 D 2 /D 5 D 1 /D 6 D 0 /D 7
S D O
C L K
S B C R
D e fa u lt
S B D R
D e fa u lt
D 7
C K S
0
D 7
u
D 6
M 1
1
D 6
u
D 5
M 0
1
D 5
u
N o te : "u " m e a n s u n c h a n g e d .
D 4
S B E N
0
D 4
u
D 3
M L S
0
D 3
u
D 2
C S E N
0
D 2
u
D 1
W C O L
0
D 1
u
D 0
T R F
0
D 0
u
D a ta B u s
S B D R ( R e c e iv e d D a ta R e g is te r )
D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0
M
X
M L S
In te r n a l B a u d R a te C lo c k
E N
S C K
C lo c k P o la r ity
a n d , s ta rt
a n d , s ta rt
M
S D O
S D I
U
U
X
M a s te r o r S la v e
S B E N
E N
Rev. 1.00
B u ffe r
S B E N
M
X
a n d , s ta rt
W C O L : s e t b
C S E N : e n a b
1 . m a s te r
2 . s la v e m
S B E N : e n a b
1 . W h e n S
2 . W h e n S
T R F 1 : d a ta
C P O L 1 /0 : c
S D O
U
T R F
C 0 C 1 C 2
In te r n a l B u s y F la g
S B E N
A N D
W C O L F la g
W r ite S B D R
W r ite S B D R E n a b le /D is a b le
W r ite S B D R
S C S
M a s te r o r S la v e
S B E N
C S E N
y S IO c le a r e d b y u s e r s
le /d is a b le c h ip s e le c tio n fu n c tio
m o d e 1 /0 : w ith /w ith o u t S C S o u
o d e 1 /0 : w ith /w ith o u t S C S in p u
le /d is a b le s e r ia l b u s ( 0 : in itia liz
B E N = 0 , a ll s ta tu s fla g s s h o u ld
B E N = 0 , a ll S IO r e la te d fu n c tio
tr a n s m itte d o r r e c e iv e d , 0 : d a ta
lo c k p o la r ity r is in g /fa llin g e d g e
59
n
tp
t
e
p in
u t fu n c tio n
c o n tr o l fu n c tio
a ll s ta tu s fla g
b e in itia liz e d
n p in s s h o u ld s
is tr a n s m ittin g
: m a s k o p tio n
n
s )
ta y a t flo a tin g s ta te
o r s till n o t r e c e iv e d
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
IIS Function
the right channel, and a ²L² state is used for the left
channel.
D/A Converter Interface
The device provides the IIS serial data format to support
the multiple D/A converters, one bit clock output and a
word clock signal for left/right stereo serial data transmission.
CK Description
CK bit clock is the clock source for the signal. which can
accept the IIS serial data format.
Clock Signal
DT:Stereo Serial Data Format Transmit
The bit clock output signals DCK are used to synchronize the IIS serial data. The word clock signal LOAD divides the serial data into left channel and right channel
data for two-way audio output.
The audio output data is in serial mode with 16 bit digital
signal and LSB first output. There is a high sampling
rate of 50kHz when the fOSC is 12.8MHz and with two
channel outputs for Right/Left channel. The device provides only one serial data format as IIS mode. The user
could directly connect a D/A converter which can accept
the IIS serial data format.
WAS Description
The word clock signal WAS is used for IIS serial data.
The stereo serial data consists of 16-channel sound
generator. On IIS format, a ²H² state on WAS is used for
W A S
R ig h t
L e ft
C K
D T
L S B
M S B
S a m p le O u t
D/A Converter Timing
UART Bus Serial Interface
The device contains an integrated full-duplex asynchronous serial communications. The UART function can transmit
and receive data serially by transferring a frame of data with eight per transmission. The UART function possesses its
own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. If the
UART Clock always generates 31.25kHz, the value of BRGR should correspond to fOSC.
Register Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RS232C
¾
¾
PH
EN
¾
¾
BE
BF
TXD
D7
D6
D5
D4
D3
D2
D1
D0
RXD
D7
D6
D5
D4
D3
D2
D1
D0
¾: No function, read only, read as 0.
BF: RX buffer full; 0: Buffer not full; 1: Buffer full (Default=0)
BE: TX buffer empty; 0: Buffer not empty; 1: Buffer empty (Default=1)
EN: Enable/disable RS232 function; 0: disable; 1: enable
PH: RS232 input Pull High control (Default=1)
0= disable; 1= enable
Note:
BRGR
Decimal
Integer
Prescaler
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
2
Rev. 1.00
60
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
BRGR
Decimal
Integer
Prescaler
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
1
0
0
1
0
1
1
1
1
0
0
0
0
3
1
1
0
0
1
0
0
0
61
1
1
1
0
1
0
0
0
41
1
1
0
1
1
0
0
0
55
1
1
1
1
1
0
0
0
4
1
1
0
0
0
1
0
0
62
1
1
1
0
0
1
0
0
33
1
1
0
1
0
1
0
0
50
1
1
1
1
0
1
0
0
42
1
1
0
0
1
1
0
0
56
1
1
1
0
1
1
0
0
20
1
1
0
1
1
1
0
0
36
1
1
1
1
1
1
0
0
5
1
1
0
0
0
0
1
0
63
1
1
1
0
0
0
1
0
53
1
1
0
1
0
0
1
0
31
1
1
1
1
0
0
1
0
34
1
1
0
0
1
0
1
0
51
1
1
1
0
1
0
1
0
13
1
1
0
1
1
0
1
0
15
1
1
1
1
1
0
1
0
43
1
1
0
0
0
1
1
0
57
1
1
1
0
0
1
1
0
17
1
1
0
1
0
1
1
0
28
1
1
1
1
0
1
1
0
21
1
1
0
0
1
1
1
0
37
1
1
1
0
1
1
1
0
24
1
1
0
1
1
1
1
0
45
1
1
1
1
1
1
1
0
6
1
1
0
0
0
0
0
1
0
1
1
1
0
0
0
0
1
59
1
1
0
1
0
0
0
1
40
1
1
1
1
0
0
0
1
54
1
1
0
0
1
0
0
1
32
1
1
1
0
1
0
0
1
49
1
1
0
1
1
0
0
1
19
1
1
1
1
1
0
0
1
35
1
1
0
0
0
1
0
1
52
1
1
1
0
0
1
0
1
30
1
1
0
1
0
1
0
1
12
1
1
1
1
0
1
0
1
14
1
1
0
0
1
1
0
1
16
1
1
1
0
1
1
0
1
27
Rev. 1.00
61
60
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
BRGR
Decimal
Integer
Prescaler
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1
1
0
1
1
1
0
1
23
1
1
1
1
1
1
0
1
44
1
1
0
0
0
0
1
1
58
1
1
1
0
0
0
1
1
39
1
1
0
1
0
0
1
1
48
1
1
1
1
0
0
1
1
18
1
1
0
0
1
0
1
1
29
1
1
1
0
1
0
1
1
11
1
1
0
1
1
0
1
1
26
1
1
1
1
1
0
1
1
22
1
1
0
0
0
1
1
1
38
1
1
1
0
0
1
1
1
47
1
1
0
1
0
1
1
1
10
1
1
1
1
0
1
1
1
25
1
1
0
0
1
1
1
1
46
1
1
1
0
1
1
1
1
9
1
1
0
1
1
1
1
1
8
1
1
1
1
1
1
1
1
7
0
0
1
1
1
1
1
1
7.75
0
1
1
1
1
1
1
1
7.25
1
0
1
1
1
1
1
1
7.5
BRGR Baud Rate Prescaler Table
Note: Baud Rate: 31.25kHz= fOSC/(prescaler´32)
For HT37P00
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
fOSC
Baud Rate
1
1
0
1
1
1
1
1
8MHz
31.25kHz
1
1
1
0
1
0
1
1
11.059MHz
31.25kHz
0
0
0
1
0
1
0
1
12.8MHz
31.25kHz
1
1
0
0
1
1
0
1
16MHz
31.25kHz
UART Control Description
UART interface 3 pins: Mout , Min , Mth.
· Mout: transmit data output pin
· Min: receiver data input pin
· Mth: go through output pin
Note: Mout is hi-state when UART function initialized or finished to transmit.
Rev. 1.00
62
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-MDS software development
tools. As these options are programmed into the device using the hardware programming tools, once they are selected
they cannot be changed later as the application software has no control over the configuration options. All options must
be defined for proper system function, the details of which are shown in the table.
No.
Function
1
Watchdog Timer: enable or disable
2
Watchdog Timer clock source: T1 (fOSC/8) or RC OSC
3
CLRWDT instructions: 1 or 2 instructions
4
PA0~PA7: wake-up enable or disable (bit option)
5
PA, PB, PC, PD and PE: pull-high enable or disable (port numbers are device dependent)
6
System oscillator: Xtal Mode or RC Mode
7
LVR function: enable or disable
8
LVR / LVD voltage selection
1. 3.0V/3.1V
2. 2.4V/2.5V
9
Share PIN - PA5/INT: enable (INT) or disable (PA5)
Share PIN - PA6/TMR0: enable (TMR0) or disable (PA6)
Share PIN - PA7/TMR1: enable (TMR1) or disable (PA7))
10
R to F Function : enable or normal I/O (PD0~PD3)
11
When R to F Enable, the Share PIN that using and depend on the Option.
K0/PC0
K1/PC1
K2/PC2
K3/PC3
K4/PC4
K5/PC5
K6/PC6
K7/PC7
12
IIS/PD4~6 pin option:
1. IIS pin
2. PD4~PD6 are IO port
13
UART/PE0~PE2 pin option:
1. UART pin
2. PE0~PE2 are IO port
14
SPI/PE3~PE6 pin option:
1. SPI pin
2. PE3~PE6 are IO port
Rev. 1.00
63
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Application Circuits
V
D D
1 0 W
4 7 m F
V D D
V D D _ D A C
O S C 1
O S C 2
V
D D
4 7 m F
0 .1 m F
A u d _ in
*R C H
5 0 k W
V b ia s
V D D _ A M P
V D D _ A D C
1 0 m F
0 .1 m F
V
0 .1 m F
S P +
S p e a k e r
(8 W )
S P D D
In te r n a l P o w e r
A M P C ir c u it
L C H
1 0 0 k W
R E S
0 .1 m F
C
C
0 .1 m F
5 0 k W
S
4 7 m F
2
8
O U T N
V D D
IN
3
P
1 0 m F
H T 3 7 B 9 0 /7 0 /5 0 /3 0
H T 8 2 V 7 3 3
V R E F
C E
Note:
D D
O U T P
V S
V S S _ D A
V S S _ A M
V S S _ A D
V
5
O U T N
1
S P K
7
O U T P
(8 W )
4
If user has used internal power AMP circuit, need to add two capacitances (47mF, 0.1mF) that be connected between VDD_AMP and VSS.
V
D D
1 0 W
4 7 m F
O S C 1
1 1 .0 5 9 M H z
V D D
0 .1 m F
V D D _ D A C
D D
S P K
(8 W )
O S C 2
1 k W
L C H
V
D D
7 5 0 W
V D D _ A M P
V D D _ A D C
V
D D
R E S
V S
V S S _ D A
V S S _ A M
V S S _ A D
V
C
C
S
D D
S P K
(8 W )
1 k W
R C H
1 0 0 k W
0 .1 m F
V
7 5 0 W
P
H T 3 7 B 9 0 /7 0 /5 0 /3 0
Rev. 1.00
64
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Cen tral to the s uc ces sf ul oper atio n of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 11.059MHz system oscillator, most instructions would be implemented
within 0.723ms and branch or call instructions would be
implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.00
65
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.00
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
66
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.00
67
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.00
68
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.00
69
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.00
70
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.00
71
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.00
72
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.00
73
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.00
74
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.00
75
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.00
76
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.00
77
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Package Information
80-pin LQFP (10mm´10mm) Outline Dimensions
C
D
G
4 1
6 0
H
I
6 1
4 0
F
A
B
E
2 1
8 0
K
Symbol
Dimensions in inch
Min.
Nom.
Max.
A
¾
0.472 BSC
¾
B
¾
0.394 BSC
¾
C
¾
0.472 BSC
¾
D
¾
0.394 BSC
¾
E
¾
0.016 BSC
¾
0.0111
F
0.007
0.009
G
0.053
0.055
0.057
H
¾
¾
0.063
I
0.002
¾
0.006
J
0.018
0.024
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 1.00
J
2 0
1
a
Dimensions in mm
Min.
Nom.
Max.
A
¾
12 BSC
¾
B
¾
10 BSC
¾
C
¾
12 BSC
¾
D
¾
10 BSC
¾
E
¾
0.4 BSC
¾
0.23
F
0.13
0.18
G
1.35
1.40
1.45
H
¾
¾
1.60
¾
0.15
I
0.05
J
0.45
K
0.09
¾
0.20
a
0°
¾
7°
0.75
78
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
100-pin LQFP (14mm´14mm) Outline Dimensions
C
7 5
D
G
5 1
I
5 0
7 6
H
F
A
B
E
1 0 0
2 6
2 5
1
Symbol
a
J
Dimensions in inch
Min.
Nom.
Max.
A
¾
0.630 BSC
¾
B
¾
0.551 BSC
¾
C
¾
0.630 BSC
¾
D
¾
0.551 BSC
¾
E
¾
0.020 BSC
¾
F
0.007
0.009
0.011
G
0.053
0.055
0.057
H
¾
¾
0.063
I
0.002
¾
0.006
J
0.018
0.024
0.030
K
0.004
¾
0.008
a
0°
¾
7°
Symbol
Rev. 1.00
K
Dimensions in mm
Min.
Nom.
Max.
A
¾
16 BSC
¾
B
¾
14 BSC
¾
C
¾
16 BSC
¾
D
¾
14 BSC
¾
E
¾
0.50 BSC
¾
F
0.17
0.22
0.27
G
1.35
1.4
1.45
H
¾
¾
1.60
I
0.05
¾
0.15
J
0.45
0.06
0.75
K
0.09
¾
0.20
a
0°
¾
7°
79
June 22, 2017
HT37B90/HT37B70/HT37B50/HT37B30
Copyright Ó 2017 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and
Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a
risk to human life due to malfunction or otherwise. Holtek¢s products are not authorized for use
as critical components in life support devices or systems. Holtek reserves the right to alter its
products without prior notification. For the most up-to-date information, please visit our web
site at http://www.holtek.com.tw.
Rev. 1.00
80
June 22, 2017