ICST ICS85210AY-21T Low skew, dual, 1-to-5 differential-to-hstl fanout buffer Datasheet

ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS85210-21 is a low skew, high perforICS
mance dual 1-to-5 Differential-to-HSTL Fanout
HiPerClockS™
Buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The CLKx, nCLKx pairs can accept
most standard differential input levels. The ICS85210-21 is
characterized to operate from a 3.3V power supply.
Guaranteed output and par t-to-par t skew characteristics make the ICS85210-21 ideal for those clock distribution applications demanding well defined performance and repeatability.
• Dual 1-to-5 HSTL bank outputs
• 2 selectable differential clock input pairs
• CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
• Maximum output frequency: 650MHz
• Translates any single ended input signal to 3.3V
HSTL levels with resistor bias on nCLKx inputs
• Output skew: 50ps (maximum)
• Part-to-part skew: 350ps (maximum)
• Propagation delay: 2ns (maximum)
• 3.3V core, 1.8V output operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
QA0
nQA0
VDDO
nQA2
QA2
QB0
nQB0
QB1
nQB1
VDD
1
24
QA3
nc
2
23
nQA3
CLK0
3
22
QA4
nCLK0
4
21
nQA4
nc
5
20
QB0
CLK1
6
19
nQB0
nCLK1
7
18
QB1
GND
8
17
nQB1
ICS85210-21
9 10 11 12 13 14 15 16
VDDO
QB2
nQB2
QB3
nQB3
QB4
QB3
nQB3
nQB4
VDDO
QB2
nQB2
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
QB4
nQB4
85210AY-21
nQA1
QA4
nQA4
QA1
32 31 30 29 28 27 26 25
QA0
QA2
nQA2
QA3
nQA3
CLK1
nCLK1
nQA0
QA1
nQA1
VDDO
CLK0
nCLK0
PIN ASSIGNMENT
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1
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1
VDD
Power
Type
2, 5
nc
Unused
3
CLK0
Input
4
nCLK0
Input
6
CLK1
Input
7
nCLK1
Input
8
GND
Power
Description
Core supply pin.
No connect.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Pulldown Non-inver ting differential clock input.
Pullup
Inver ting differential clock input.
Power supply ground.
9, 16, 25, 32
VDDO
Power
Output supply pins.
10, 11
nQB4, QB4
Output
Differential output pair. HSTL interface levels.
12, 13
nQB3, QB3
Output
Differential output pair. HSTL interface levels.
14, 15
nQB2, QB2
Output
Differential output pair. HSTL interface levels.
17, 18
nQB1, QB1
Output
Differential output pair. HSTL interface levels.
19, 20
nQB0, QB0
Output
Differential output pair. HSTL interface levels.
21, 22
nQA4, QA4
Output
Differential output pair. HSTL interface levels.
23, 24
nQA3, QA3
Output
Differential output pair. HSTL interface levels.
26, 27
nQA2, QA2
Output
Differential output pair. HSTL interface levels.
28, 29
nQA1, QA1
Output
Differential output pair. HSTL interface levels.
30, 31
nQA0, QA0
Output
Differential output pair. HSTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
KΩ
RPULLDOWN
Input Pulldown Resistor
51
KΩ
85210AY-21
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2
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA
47.9°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
VDD
Input Power Supply Voltage
VDDO
Output Power Supply Voltage
IDD
Power Supply Current
IDDO
Output Supply Current
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
1.6
1.8
2.0
V
120
mA
No Load
0
mA
TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
IIH
Input High Current
IIL
Input Low Current
Test Conditions
Minimum
Typical
Maximum
Units
nCLK0, nCLK1
VDD = VIN = 3.465V
5
µA
CLK0, CLK1
VDD = VIN = 3.465V
150
µA
nCLK0, nCLK1
VDD = 3.465V, VIN = 0V
-150
CLK0, CLK1
VDD = 3.465V, VIN = 0V
-5
µA
µA
VPP
Peak-to-Peak Input Voltage
0.15
Common Mode Input Voltage;
0.5
VCMR
NOTE 1, 2
NOTE 1: For single ended applications the maximum input voltage for CLKx and nCLKx is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
1.3
V
VDD - 0.85
V
TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol Parameter
Output High Voltage;
VOH
NOTE 1
Output Low Voltage;
VOL
NOTE 1
VOX
Test Conditions
Output Crossover Voltage
Minimum
Maximum
Units
1
1.4
V
0
0.4
V
40% x (VOH - VOL) + VOL
60% x (VOH - VOL) + VOL
V
0.6
1.1
V
Peak-to-Peak
Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to ground.
VSWING
85210AY-21
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Typical
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 1.8V±0.2V, TA = 0°C TO 70°C
Symbol
Parameter
fMAX
Output Frequency
tPD
Propagation Delay; NOTE 1
t sk(o)
Output Skew; NOTE 2, 4
t sk(pp)
Par t-to-Par t Skew; NOTE 3, 4
t R/ t F
Output Rise/Fall Time
Test Conditions
Minimum
IJ 650MHz
30% to 70% @ 50MHz
Typical
1.5
300
odc
Output Duty Cycle
47
All parameters measured at 400MHz unless noted otherwise.
The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
85210AY-21
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4
Maximum
Units
650
MHz
2
ns
50
ps
350
ps
700
ps
53
%
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
3.3V±5%
V DD
Qx
V DD
SCOPE
nCLK0,
nCLK1
HSTL
V
Cross Points
PP
V
CMR
CLK0,
CLK1
nQx
GND
GND
0V
3.3V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
nQx
Qx
PART 1
nQx
Qx
Qy
PART 2
nQy
nQy
Qy
t sk(pp)
t sk(o)
OUTPUT SKEW
PART-TO-PART SKEW
nCLK0,
nCLK1
70%
70%
CLK0,
CLK1
VSW I N G
Clock
Outputs
nQAx,
nQBx
QAx,
QBx
30%
30%
tF
tR
OUTPUT RISE/FALL TIME
tPD
PROPAGATION DELAY
nQAx,
nQBx
QAx,
QBx
Pulse Width
t
odc =
PERIOD
t PW
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
85210AY-21
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5
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLKx
V_REF
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
85210AY-21
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6
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 3A, the input termination applies for ICS
HiPerClockS HSTL drivers. If you are using an HSTL driver from
another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
R1
50
R1
50
HiPerClockS
Input
R2
50
R2
50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
ICS HIPERCLOCKS HSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
BY
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
BY
R4
125
Zo = 50 Ohm
LVDS_Driv er
Zo = 50 Ohm
CLK
CLK
R1
100
Zo = 50 Ohm
nCLK
LVPECL
R1
84
HiPerClockS
Input
nCLK
Receiv er
Zo = 50 Ohm
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVDS DRIVER
BY
BY
3.3V
3.3V
3.3V
LVPECL
Zo = 50 Ohm
C1
Zo = 50 Ohm
C2
R3
125
R4
125
CLK
nCLK
R5
100 - 200
R6
100 - 200
R1
84
HiPerClockS
Input
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN
3.3V LVPECL DRIVER WITH AC COUPLE
85210AY-21
BY
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7
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS85210-21.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS85210-21 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 120mA = 416mW
Power (outputs)MAX = 32.8mW/Loaded Output pair
If all outputs are loaded, the total power is 10 * 32.8mW = 328mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 328mW = 744mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used . Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.744W * 42.1°C/W = 101°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 5. THERMAL RESISTANCE θJA
FOR
32-PIN LQFP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
200
500
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
85210AY-21
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REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
HSTL output driver circuit and termination are shown in Figure 3.
VDDO
Q1
VOUT
RL
50Ω
FIGURE 3. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R ) * (V
L
-V
DDO_MAX
/R ) * (V
Pd_L = (V
OL_MAX
L
)
OH_MIN
-V
DDO_MAX
)
OL_MAX
Pd_H = (1V/50Ω) * (2V - 1V) = 20mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
85210AY-21
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REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
200
500
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS85210-21 is: 1216
85210AY-21
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10
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
FOR
32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
32
N
A
--
--
1.60
A1
0.05
--
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
c
0.09
--
0.20
D
9.00 BASIC
D1
7.00 BASIC
D2
5.60 Ref.
E
9.00 BASIC
E1
7.00 BASIC
E2
5.60 Ref.
e
0.80 BASIC
L
0.45
0.60
0.75
θ
0°
--
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
85210AY-21
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REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Count
Temperature
ICS85210AY-21
ICS85210AY-21
32 lead LQFP
250 per tray
0°C to 70°C
ICS85210AY-21T
ICS85210AY-21
32 lead LQFP on Tape and Reel
1000
0°C to70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications.
Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by
ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
85210AY-21
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12
REV. A OCTOBER 6, 2003
ICS85210-21
Integrated
Circuit
Systems, Inc.
LOW SKEW, DUAL, 1-TO-5
DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET
Rev
A
85210AY-21
Table
Page
1
2
2
6
7
2
Description of Change
Throughout data sheet changed LVHSTL to HSTL.
Pin Description Table changed VDD description from Positive to Core.
Pin Characteristics Table - changed CIN 4pF max. to 4pF typical.
Revised Single Ended Signal Driving Differential Input diagram.
Added Differential Clock Input Interface section.
Updated data sheet format.
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13
Date
10/6/03
REV. A OCTOBER 6, 2003
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