TI CD74HC86M High-speed cmos logic quad 2-input exclusive-or gate Datasheet

[ /Title
(CD74
HC86,
CD74
HCT86
)
/Subject
(High
Speed
CMOS
Logic
Quad
2-Input
EXCL
USIVE
OR
CD54HC86, CD74HC86,
CD54HCT86, CD74HCT86
Data sheet acquired from Harris Semiconductor
SCHS137D
High-Speed CMOS Logic
Quad 2-Input EXCLUSIVE-OR Gate
August 1997 - Revised September 2003
Features
Description
• Typical Propagation Delay: 9ns at VCC = 5V,
CL = 15pF, TA = 25oC
• Balanced Propagation Delay and Transition Times
The ’HC86 and ’HCT86 contain four independent
EXCLUSIVE OR gates in one package. They provide the
system designer with a means for implementation of the
EXCLUSIVE OR function. Logic gates utilize silicon gate
CMOS technology to achieve operating speeds similar to
LSTTL gates with the low power consumption of standard
CMOS integrated circuits. All devices have the ability to drive
10 LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.
• Significant Power Reduction Compared to LSTTL
Logic ICs
Ordering Information
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
PART NUMBER
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
Applications
• Logical Comparators
• Parity Generators and Checkers
• Adders and Subtractors
TEMP. RANGE
(oC)
PACKAGE
CD54HC86F3A
-55 to 125
14 Ld CERDIP
CD54HCT86F3A
-55 to 125
14 Ld CERDIP
CD74HC86E
-55 to 125
14 Ld PDIP
CD74HC86M
-55 to 125
14 Ld SOIC
CD74HC86MT
-55 to 125
14 Ld SOIC
CD74HC86M96
-55 to 125
14 Ld SOIC
CD74HCT86E
-55 to 125
14 Ld PDIP
CD74HCT86M
-55 to 125
14 Ld SOIC
CD74HCT86MT
-55 to 125
14 Ld SOIC
CD74HCT86M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
Pinout
CD54HC86, CD54HCT86
(CERDIP)
CD74HC86, CD74HCT86
(PDIP, SOIC)
TOP VIEW
1A 1
14 VCC
1B 2
13 4B
1Y 3
12 4A
2A 4
11 4Y
2B 5
10 3B
2Y 6
9 3A
GND 7
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
1
CD54HC86, CD74HC86, CD54HCT86, CD74HCT86
Functional Diagram
1
14
2
13
1A
4B
1B
1Y
2A
2B
2Y
GND
VCC
3
12
4
11
5
10
6
9
7
8
4A
4Y
3B
3A
3Y
TRUTH TABLE
INPUTS
OUTPUT
nA
nB
nY
L
L
L
L
H
H
H
L
H
H
H
L
H = High Voltage Level, L = Low Voltage Level
Logic Symbol
nA
nY
nB
2
CD54HC86, CD74HC86, CD54HCT86, CD74HCT86
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
80
M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . .
86
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
Low Level Input
Voltage
VIL
25oC
IO (mA) VCC (V)
-40oC TO +85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
1.5
-
-
1.5
-
1.5
-
V
4.5
3.15
-
-
3.15
-
3.15
-
V
6
4.2
-
-
4.2
-
4.2
-
V
2
-
-
0.5
-
0.5
-
0.5
V
4.5
-
-
1.35
-
1.35
-
1.35
V
6
-
-
1.8
-
1.8
-
1.8
V
-0.02
2
1.9
-
-
1.9
-
1.9
-
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-0.02
6
5.9
-
-
5.9
-
5.9
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
-5.2
6
5.48
-
-
5.34
-
5.2
-
V
HC TYPES
High Level Output
Voltage
CMOS Loads
VOH
-
VIH or
VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
-
-
0.02
2
-
-
0.1
-
0.1
-
0.1
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
0.02
6
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
5.2
6
-
-
0.26
-
0.33
-
0.4
V
II
VCC or
GND
-
6
-
-
±0.1
-
±1
-
±1
µA
ICC
VCC or
GND
0
6
-
-
2
-
20
-
40
µA
3
CD54HC86, CD74HC86, CD54HCT86, CD74HCT86
DC Electrical Specifications
(Continued)
TEST
CONDITIONS
SYMBOL
VI (V)
High Level Input
Voltage
VIH
-
-
Low Level Input
Voltage
VIL
-
High Level Output
Voltage
CMOS Loads
VOH
VIH or
VIL
PARAMETER
25oC
IO (mA) VCC (V)
-40oC TO +85oC
-55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
2
-
-
2
-
2
-
V
-
4.5 to
5.5
-
-
0.8
-
0.8
-
0.8
V
-0.02
4.5
4.4
-
-
4.4
-
4.4
-
V
-4
4.5
3.98
-
-
3.84
-
3.7
-
V
0.02
4.5
-
-
0.1
-
0.1
-
0.1
V
4
4.5
-
-
0.26
-
0.33
-
0.4
V
±0.1
-
±1
-
±1
µA
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or
VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
II
VCC
and
GND
-
5.5
-
ICC
VCC or
GND
0
5.5
-
-
2
-
20
-
40
µA
∆ICC
(Note 2)
VCC
- 2.1
-
4.5 to
5.5
-
100
360
-
450
-
490
µA
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
All
1
NOTE: Unit Load is ∆ICC limit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
Switching Specifications
PARAMETER
Input tr, tf = 6ns
SYMBOL
TEST
CONDITIONS
tPLH, tPHL
CL = 50pF
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
-
-
120
-
150
-
180
ns
4.5
-
-
24
-
30
-
36
ns
6
-
-
20
-
26
-
31
ns
HC TYPES
Propagation Delay,Input to
Output (Figure 1)
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
5
-
9
-
-
-
-
-
ns
Transition Times (Figure 1)
tTLH, tTHL
CL = 50pF
2
-
-
75
-
95
-
110
ns
4.5
-
-
15
-
19
-
22
ns
6
-
-
13
-
16
-
19
ns
-
-
-
10
-
10
-
10
pF
Input Capacitance
CI
-
4
CD54HC86, CD74HC86, CD54HCT86, CD74HCT86
Switching Specifications
Input tr, tf = 6ns (Continued)
PARAMETER
SYMBOL
TEST
CONDITIONS
Power Dissipation Capacitance
(Notes 3, 4)
CPD
-
25oC
-40oC TO 85oC -55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
5
-
22
-
-
-
-
-
pF
HCT TYPES
Propagation Delay, Input to
Output (Figure 2)
tPLH, tPHL
CL = 50pF
4.5
-
-
32
-
40
-
48
ns
Propagation Delay, Data Input to
Output Y
tPLH, tPHL
CL = 15pF
5
-
13
-
-
-
-
-
ns
Transition Times (Figure 2)
tTLH, tTHL
CL = 50pF
4.5
-
-
15
-
19
-
22
ns
Input Capacitance
Power Dissipation Capacitance
(Notes 3, 4)
CI
-
-
-
-
10
-
10
-
10
pF
CPD
-
5
-
27
-
-
-
-
-
pF
NOTES:
3. CPD is used to determine the dynamic power consumption, per gate.
4. PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Test Circuits and Waveforms
tr = 6ns
tf = 6ns
90%
50%
10%
INPUT
GND
tTLH
GND
tTHL
90%
50%
10%
INVERTING
OUTPUT
3V
2.7V
1.3V
0.3V
INPUT
tTHL
tPHL
tf = 6ns
tr = 6ns
VCC
tTLH
90%
1.3V
10%
INVERTING
OUTPUT
tPHL
tPLH
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tPLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
5
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