Anpec APW8812 System power pwm controller for notebook computers with charge pump Datasheet

APW8812
System Power PWM Controller for Notebook Computers with Charge Pump
Features
Simplified Application Circuit
•
•
VIN
6V~28V
Wide Input voltage Range from 6V to 25V
Provide 5 Independent Outputs with ±1.5% Accu-
VLDO5
racy Over-Temperature
- PWM1 Controller with Adjustable (2V to 5.5V) Out-
VOUT1
put
- PWM2 Controller with Adjustable (2V to 5.5V) Out-
D1
•
•
•
•
•
•
•
•
•
•
•
PWM2
Q4
D3 C3
C2
VCP
D4
C4
The APW8812 integrates dual step-down, constant-ontime, synchronous PWM controllers (that drives dual N-
Temperature Range
±1%, (±1.5%, 50µA) 2.0V Reference Voltage Output
•
D2
VOUT2
General Description
VOUT1 as Its Power Supply)
Excellent Line/Load Regulations about ±1.5% Over-
(with Selectable Ultrasonic Operation)
Constant-On-Time Control Scheme with Frequency
L2
C1
- 270kHz Clock Signal for 15V Charge Pump (Used
VLDO3
Q3
Charge Pump
- 100mA Low Dropout Regulator (LDO3) with Fixed
3.3V Output
Built-In POR Control Scheme Implemented
Selectable Forced-PWM or Automatic PFM/PWM
LDO3
L1
PWM1
- 100mA Low Dropout Regulator (LDO5) with Fixed
5V Output
•
•
•
LDO5
Q1
Q2
put
•
ENILIM1 EN LDO ENILIM2
channel MOSFETs for each channel) and two low dropout regulators as well as various protections into a chip.
The PWM controllers step down high voltage of a battery
to generate low-voltage for NB applications. The output
of PWM1 and PWM2 can be adjusted from 2V to 5.5V by
setting a resistive voltage-divider from VOUTx to GND.
Compensation for PWM Mode
Selectable Switching Frequency in PWM Mode
The linear regulators provide 5V and 3.3V output for
standby power supply. The linear regulators provide up
Built-in Digital Soft-Start for PWM Outputs and SoftStop for PWM Outputs and LDO Outputs
to 100mA output current. When the PWMx output voltage
is higher than LDOx bypass threshold, the related LDOx
Integrated Bootstrap Forward P-CH MOSFET
High Efficiency over Light to Full Load Range
regulator is shut off and its output is connected to VOUTx
by internal switchover MOSFET. It can save power
(PWMs)
Built-in Power Good Indicators (PWMs)
dissipation. The charge pump circuit with 270kHz clock
driver uses VOUT1 as its power supply to generate ap-
Independent Enable Inputs (PWMs, LDO)
70% Under-Voltage and 125% Over-Voltage Protec-
proximately 15V DC voltage.
The APW8812 provides excellent transient response and
tions (PWM)
Adjustable Current-Limit Protection (PWMs)
accurate DC output voltage in either PFM or PWM Mode.
In Pulse-Frequency Mode (PFM), the APW8812 provides
- Using Sense Low-Side MOSFET’s RDS(ON)
Over-Temperature Protection
very high efficiency over light to heavy loads with loadingmodulated switching frequencies. The Forced-PWM
4mmx4mm Thin QFN-24 (TQFN4x4-24A) package
Lead Free and Green Device Available (RoHS
Mode works nearly at constant frequency for low-noise
requirements. The unique ultrasonic mode maintains the
Compliant)
switching frequency above 25KHz, which eliminates
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
1
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APW8812
General Description (Cont.)
POK
BOOT1
UGATE1
PHASE1
LGATE1
22
21
20
19
17
LDO5
REF
3
16
VIN
15
PGND
Bottom View
Thermal Pad
SKIP#
ENILIM2
6
13
EN LDO
12
14
LGATE2
5
11
FB2
PHASE2
4
10
TON
UGATE2
Notebook and Sub-Notebook Computers
Portable Devices
2
BOOT2
•
•
•
•
•
•
•
FB1
9
Applications
VCLK
8
The APW8812 is available in a TQFN4x4-24A package.
18
LDO3
ing both ENILIM1/2 pin and ENLDO pin low shuts down
the whole chip with low quiescent current close to zero.
1
7
tors by the discharge device. The APW8812 has individual
enable controls for each PWM channels and LDOs. Pull-
ENILIM1
VOUT2
(typ.) digital soft-start can reduce the start-up current. A
soft-stop function actively discharges the output capaci-
23
current-limit, output under-voltage output over-voltage
protections, being perfect for NB applications. A 1.7ms
VOUT1
noise in audio applications.
The APW8812 is equipped with accurate sourcing and
24
Pin Configuration
TQFN4x4-24A
Top View
DDR1, DDR2, and DDR3 Power Supplies
3-Cell and 4-Cell Li+ Battery-Powered Devices
Graphic Cards
= Thermal Pad (connected to GND plane for
better heat dissipation)
Game Consoles
Telecommunications
Ordering and Marking Information
Package Code
QB : TQFN4x4-24A
Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
TR : Tape & Reel
Assembly Material
G : Halogen and Lead Free Device
APW8812
Assembly Material
Handling Code
Temperature Range
Package Code
APW8812 QB:
XXXXX - Date Code
APW8812
XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
2
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APW8812
Absolute Maximum Ratings
Symbol
VIN
VBOOT
VBOOT-GND
(Note 1)
Parameter
Rating
Unit
Input Power Voltage (VIN to GND)
-0.3 ~ 28
V
BOOT Supply Voltage (BOOT to PHASE)
-0.3 ~ 7
V
BOOT Supply Voltage (BOOT to GND)
-0.3 ~ 35
V
<400ns pulse width
>400ns pulse width
-5 ~ VBOOT+0.3
-0.3 ~ VBOOT+0.3
V
<400ns pulse width
>400ns pulse width
-5 ~ VLDO5+0.3
-0.3 ~ VLDO5+0.3
V
-5 ~ 35
-0.3 ~ 28
V
-0.3 ~ 6
V
UGATE Voltage (UGATE to PHASE)
VUG-PHASE
LGATE Voltage (LGATE to GND)
VLG-GND
PHASE Voltage (PHASE to GND)
VPHASE
<400ns pulse width
>400ns pulse width
All Other Pins (LDOx, FBx, VOUTx, LDO5, LDO3, REF, VCLK, EN
LDO, ENILIMx to GND)
TJ
Maximum Junction Temperature
TSTG
Storage Temperature
TSDR
Maximum Lead Soldering Temperature, 10 Seconds
150
o
-65 ~ 150
o
260
o
C
C
C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics (Note 2)
Symbol
Parameter
Typical Value
θJA
Thermal Resistance - Junction to Ambient
52
θJC
Thermal Resistance - Junction to Case
7
Unit
o
C/W
Note 2: θJA and θJC are measured with the component mounted on a high effective thermal conductivity test board in free air. The
thermal pad of package is soldered directly on the PCB.
Recommended Operating Conditions
Symbol
Parameter
Range
Unit
VIN
PWM1/2 Converter Input Voltage
6 ~ 25
V
VOUT1
PWM1 Converter Output Voltage
2 ~ 5.5
V
VOUT2
PWM2 Converter Output Voltage
2 ~ 5.5
V
PWM1/2 Converter Input Capacitor (MLCC)
10 ~
µF
LDO Output Capacitor (MLCC)
2.2 ~
µF
CIN
CLDO
TA
Ambient Temperature
-40 ~ 85
o
TJ
Junction Temperature
-40 ~ 125
o
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
3
C
C
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APW8812
Electrical Characteristics
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8812
Test Conditions
Unit
Min.
Typ.
Max.
-
0.55
1.3
mA
-
5
7
mW
-
200
-
-
20
40
INPUT SUPPLY POWER
IVN
VIN Supply Current
Supply current1, VOUT1 = VOUT2 =
0V, SKIP# = GND, EN LDO = open,
ENILIMx = 5V, VFB1 = VFB2 = 2.05V
Supply current2, VOUT1 = 5V,
VOUT2 = 3.3V, SKIP# = GND,
EN LDO = open, ENILIMx = 5V,
VFB1 = VFB2 = 2.05V, PVIN+PLDO5
Standby current, EN LDO=open,
EN PWM=0V
Shutdown current, EN LDO= 0V,
ENILIMx = 0V
µA
UNDER-VOLTAGE LOCK OUT PROTECTION (UVLO)
LDO5 UVLO threshold
LDO3 UVLO threshold
Rising Edge
4.1
4.2
4.3
V
Hysteresis
-
0.1
-
V
Shutdown
-
2.5
-
V
2
-
5.5
V
1.98
2.0
2.02
V
-20
-
20
nA
SKIP# = LDO5, IOUT = 0A to 5A
-
-1.7
-
%
SKIP# = REF, IOUT = 0A to 5A
-
-1.5
-
%
SKIP# = GND, IOUT = 0A to 5A
-
-0.1
-
%
PWM CONTROLLERS
Output Voltage Adjust Ranve
VFB
IFB
FBx Reference Voltage
FBx input current
PWM 1/2 Load Regulation
VOUT1, VOUT2
o
o
IREF = 0A, TA = -40 C to 85 C
o
VFBX = 2.0V, TA = 25 C
PWM1/2 Line Regulation
VIN = 6V to 25V
-
0.005
-
%/V
Soft-Start Ramp Time
ENPWM High to VOUT Full Regulation
-
1.7
-
ms
TON11
PWM1 On Time seting1
TON = GND, SKIP# = GND,
VIN = 12V, PWM1 = 5V
-
2080
-
TON12
PWM1 On Time seting2
TON = REF, SKIP# = GND, VIN=12V,
PWM1=5V
-
1700
-
TON13
PWM1 On Time seting3
TON = LDO3, SKIP# = GND,
VIN = 12V, PWM1 = 5V
-
1390
-
TON14
PWM1 On Time seting4
TON = LDO5, SKIP# = GND,
VIN=12V, PWM1=5V
-
1140
-
TON21
PWM2 On Time seting1
TON = GND, SKIP# = GND, VIN=12V,
PWM2 = 3.3V
-
1100
-
TON22
PWM2 On Time seting2
TON = REF, SKIP# = GND, VIN=12V,
PWM2 = 3.3V
-
900
-
TON23
PWM2 On Time seting3
TON = LDO3, SKIP# = GND,
VIN = 12V, PWM2 = 3.3V
-
730
-
TON24
PWM2 On Time seting4
TON = LDO5, SKIP# = GND,
VIN = 12V, PWM2 = 3.3V
-
600
-
350
450
550
UGATEx Minimum Off-Time
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
4
ns
ns
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APW8812
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8812
Test Conditions
Unit
Min.
Typ.
Max.
UGATEx Minimum On-Time
80
110
140
ns
Minimum Ultrasonic SKIP Operating
Frequency
25
37
-
kHz
PWM CONTROLLERS (CONT.)
LOW DROUPUT LINEAR REGULATORS (LDO5/LDO3)
LDO5 Output Voltage
VOUT1 = GND, 6V < VIN < 25V, 0<
ILDO < 100mA
4.8
5.0
5.2
V
LDO3 Output Voltage
VOUT2 = GND, 6V < VIN < 25V, 0<
ILDO3 < 100mA
3.2
3.33
3.46
V
VTHBYP5
LDO5 Bypass Threshold for
VOUT1-to-LDO5 Switch On
VOUT1 Regulation Voltage Rising
4.55
4.7
4.85
Hysteresis
0.15
0.25
0.3
VTHBYP3
LDO3 Bypass Threshold for
VOUT2-to-LDO3 Switch On
VOUT2 Regulation Voltage Rising
3.05
3.15
3.25
Hysteresis
0.1
0.2
0.25
VOUTx-to-LDOx Switch On Resistance
VOUTx to LDOx, 10mA
LDOx Current-Limit
VOUTx = GND, LDOx = GND
LDOx Discharge On Resistance
V
V
-
1.5
3
Ω
150
-
-
mA
-
40
65
Ω
1.98
2.00
2.02
V
-
10
-
mV
10
-
-
µA
4.84
4.92
-
-
0.06
0.12
REFFERENCE
REF Output Voltage
IREF = 0A
REF Load Regulation
ILOAD = 0 to 50µA
REF Sink Current
REF in Regulation
CHARGE PUMP CLOCK
VCLKH
High Level Voltage
IVCLK = -10mA, LDO5 = 5V, TA = 25oC
o
V
VCLKL
Low Level Voltage
IVCLK = 10mA, LDO5 = 5V, TA = 25 C
FCLK
Clock Frequency
TA = 25oC
175
270
325
kHz
Over-Voltage Protection Threshold
VOUTX RIsing
120
125
130
%
Over-Voltage Fault Propagation Delay
Delta voltage = 10mV
PWM 1/2 PROTECTIONS
Current-Limit Current Source
VILIM = 920mV, TA = 25oC
On the basis of 25 oC
-
1.5
-
µs
9.4
10
10.6
µA
-
4500
-
ppm/ oC
ILIMx Adjustment Range
VENILIMx-GND
0.7
-
2
V
Maximum setting voltage
VENILIMx = 5V, Setting Current-Limit
Threshold
205
250
-
mV
Current-limit comparator offset
(VENILIMx -GND-VPGND-PHASEx),
VENILIMx = 920mV
-8
0
8
mV
Zero-Crossing Threshold
SKIP# = REF or LDOx, VPGND-PHASE
-5
0
5
mV
Under-Voltage Protection Threshold
65
70
75
%
Under-Voltage Protection Hysteresis
-
3
-
%
Under-Voltage Protection Debounce
Interval
22
32
42
µs
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
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APW8812
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8812
Test Conditions
Unit
Min.
Typ.
Max.
From EN signal go high to UVP
workable
-
2
2.6
TJ Rising
-
160
-
Hysteresis
-
25
-
POK in from Lower (POK goes high)
87
90
93
POK Threshold
POK in from higher (POK goes low)
120
125
130
POK Propagation Delay
VFBX falling and rising
POK Enable Delay
ENILMx goes high to POK goes High
POK Sink Current
VPOK = 500mV
POK Leakage Current
VPOK = 5V
PWM 1/2 PROTECTIONS (CONT.)
Under-Voltage Protection Enable
Blanking Time
Over-Temperature Protection THreshold
ms
o
C
POWER GOOD
POK hysteresis
%
-
3
-
43
63
85
µs
-
2
-
ms
2.5
7.5
-
mA
-
0.1
1
µA
LOGIC LEVELS
Forced PWM Mode
SKIP# Input Voltage
TON Input Voltage
ENILIMx Input Voltage
-
-
1.5
V
Automatic PFG/PWM Mode
1.9
-
2.1
V
Auto Skip with Ultrasonic
2.7
-
-
V
200kHz/250kHz
-
-
1.5
V
245kHz/305kHz
1.9
-
2.1
V
300kHz/375kHz
2.7
-
3.6
V
V
365kHz/460kHz
4.7
-
-
Enable
450
-
-
Disable
-
-
400
Shutdown
EN LDO Input Voltage
Input Leakage Current
-
-
0.4
Enable, VCLK = off
0.8
-
1.6
Enable, VCLK = on
2.4
-
-
mV
V
VSKIP# = VTON = 0V or 5V
-1
-
1
µA
IEN LDO
0.5
1
3
µA
GATE DRIVERS
UG Pull-Up Resistance
VBOOTx – VUGATEx = 100mV
-
4
8
Ω
UG Sink Resistance
VUGATEx – VPHASEx = 100mV
-
1.5
4
Ω
LG Pull-Up Resistance
VLDO5 – VLGATEx = 100mV
-
4
8
Ω
LG Sink Resistance
Dead-Time
VLGATEx – VPGND = 100mV
-
1.5
4
Ω
UG falling to LG rising
-
40
-
ns
LG falling to UG rising
-
40
-
ns
-
40
80
Ω
VOUT1/2 Discharge On Resistance
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
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APW8812
Electrical Characteristics (Cont.)
Refer to the typical application circuits. These specifications apply over VIN=12V and TA= -40 ~ 85 °C, unless otherwise
specified. Typical values are at TA=25°C.
Symbol
Parameter
APW8812
Test Conditions
Unit
Min.
Typ.
Max.
BOOTSTRAP SWITCH
VF
Forward Voltage
VLDO5x – VBOOTx-GND, IF = 10mA
-
0.5
0.8
V
IR
Reverse Leakage
VBOOTx-GND = 30V, VPHASEx = 25V, VLDO5
= 5V
-
-
0.5
µA
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
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APW8812
Pin Description
PIN
NO.
FUNCTION
NAME
1
ENILIM1
PWM1 Enable and Current-Limit Adjustment. There is an internal 10µA current source from LDO5 to
ENILIM1 and connected a resistor from ENILIM1 to GND to set the current-limit threshold. The
PGND-PHASE1 current-limit threshold is 1/10th the voltage set at ENILIM1 over a 0.7 to 2V range. The logic
current-limit threshold is default to 250mV value if ENILIM1 is 5V PWM1 is enabled when ENILIM1=1. When
ENILIM1=0, PWM1 is in shutdown.
2
FB1
Output voltage feedback pin (PWM1). It can use a resistive divider from VOUT1 to GND to adjust the output
from 2V to 5.5V.
3
REF
2V Reference Output. Bypass to GND with a 0.1µF (minimum) capacitor. REF can supply external loads for
50µA (maximum). REF load-regulation error will degrade feedback and output accuracy.
4
TON
Frequency Selection Input. Connect to LDO5 for 365kHz(PWM1)/460kHz(PWM2) operation and to LDO3
for 300kHz/375kHz operation. Connect to REF for 245kHz/305kHz operation and to GND for
200kHz/250kHz operation.
5
FB2
Output voltage feedback pin (PWM2). It can use a resistive divider from VOUT2 to GND to adjust the output
from 2V to 5.5V.
6
ENILIM2
7
VOUT2
PWM2 Enable and Current-Limit Adjustment. There is an internal 10µA current source from LDO5 to
ENILIM2 and connected a resistor from ENILIM2 to GND to set the current-limit threshold. The
PGND-PHASE2 current-limit threshold is 1/10th the voltage set at ENILIM2 over a 0.7 to 2V range. The logic
current-limit threshold is default to 250mV value if ENILIM2 is 5V PWM2 is enabled when ENILIM2=1. When
ENILIM2=0, PWM2 is in shutdown.
PWM2 Output Voltage-Sense Input. The VOUT2 pin makes a direct measurement of the PWM2 output
voltage. VOUT2 is an input to the constant-on-time PWM one-time one-shot circuit.
8
LDO3
3.3V Linear Regulator Output. LDO3 can provide a total of 100mA, 3.3V external loads. When LDO3 is at
3.3V and PWM2 output voltage is over 3.15V bypass threshold, the internal LDO will shut down, and LDO3
output pin connects to VOUT2 through a 1.5Ω switch. Bypass to GND with a minimum of 2.2µF ceramic
capacitor for stability.
9
BOOT2
Supply Input for The UGATE2 Gate Driver and an internal level-shift circuit. Connect to an external capacitor
to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
10
UGATE2 Output of The High-Side MOSFET Driver for PWM2. Connect this pin to Gate of the high-side MOSFET.
11
Junction Point of The High-Side MOSFET Source, Output Filter Inductor and The Low-Side MOSFET Drain
PHASE2 for PWM2. Connect this pin to the Source of the high-side MOSFET. PHASE2 serves as the lower supply rail
for the UGATE2 high-side gate driver. PHASE2 is the current-sense input for the PWM2.
12
LGATE2
Output of The Low-Side MOSFET Driver for PWM2. Connect this pin to Gate of the low-side MOSFET.
Swings from PGND to LDO5.
13
EN LDO
Master Enable Input. The LDOx is enabled when EN LDO=1. When ENLDO=0, the LDO is shutdown. See
the table 2 “Power-Up Control Logics.”
14
SKIP#
PWM1 and 2 Controller Operation Mode Control. Connect SKIP# to GND for forced-PWM mode, to REF for
auto PWM/PFM mode and to LDO3 or LDO5 for ultra-sonic mode,
15
PGND
Power Ground of The LGATE Low-Side MOSFET Drivers. Connect the pin to the source of the low-side
MOSFETs.
16
VIN
Battery voltage input pin. VIN powers linear regulators and is also used for the constant-on-time PWM
on-time one-shot circuits. Connect VIN to the battery input and bypass with a 1µF capacitor for noise
interference.
17
LDO5
5V Linear Regulator Output. LDO5 can provide a total of 100mA, 5V external loads. When LDO5 is at 5V
and PWM1 output voltage is over 4.7V bypass threshold, the internal LDO will shut down, and LDO5 output
pin connects to VOUT1 through a 1.5Ω switch. Bypass to GND with a minimum of 2.2µF ceramic capacitor
for stability.
18
VCLK
270kHz Clock Output for 15V Charge Pump.
19
LGATE1
20
Junction Point of The High-Side MOSFET Source, Output Filter Inductor and The Low-Side MOSFET Drain
PHASE1 for PWM1. Connect this pin to the Source of the high-side MOSFET. PHASE1 serves as the lower supply rail
for the UGATE1 high-side gate driver. PHASE1 is the current-sense input for the PWM1.
Output of The Low-Side MOSFET Driver for PWM1. Connect this pin to Gate of the low-side MOSFET.
Swings from PGND to LDO5.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
8
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APW8812
Pin Description (Cont.)
PIN
NO.
FUNCTION
NAME
21
UGATE1 Output of The High-Side MOSFET Driver for PWM1. Connect this pin to Gate of the high-side MOSFET.
22
BOOT1
Supply Input for The UGATE1 Gate Driver and an internal level-shift circuit. Connect to an external capacitor
to create a boosted voltage suitable to drive a logic-level N-channel MOSFET.
23
POK
Power-Good Output Pin of Both PWMs.(Logic AND) POK is an open-drain output used to indicate the status
of the PWMx output voltage. Connect the POK in to +5V through a pull-high resistor.
24
VOUT1
PWM1 Output Voltage-Sense Input. The VOUT1 pin makes a direct measurement of the PWM1 output
voltage. VOUT1 is an input to the constant-on-time PWM one-time one-shot circuit.
Thermal
Pad
GND
Signal Ground for The IC.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
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APW8812
Block Diagram
TON
BOOT2
ADAPTIVE
DEAD-TIME
DIODE
EMULATION
PWM/PFM
TRANSITION
UGATE2
PHASE2
PWM FREQUENCY
CONTROL
SKIP#
LDO5
LGATE2
TON
Generator
VOUT2
VOUT1
SMPS1
PWM2
CONTROLLER
SMPS2
PWM2
CONTROLLER
BOOT1
ADAPTIVE
DEAD-TIME
DIODE
EMULATION
PWM/PFM
TRANSITION
UGATE1
PHASE1
SKIP#
LDO5
LGATE1
PGND
SKIP#
VIN
LDO UVLO
LDO3
LDO5
THERMAL
SHUTDOWN
LDO3
LDO5
EN ENABLE
POWER ON SEQUENCE
CLEAR FAULT LATCH
VOUT2
VTHBYP3
PHASE1
ENILIM2
ENILIM1
VTHBYP5
PHASE2
REF
ENABLE
CURRENT-LIMIT
CONTROLLER
REF
VOUT1
REF
EN LDO
CHARGE PUMP
OSCILLATOR
SOFT-START
POK
POK2
90% VFB2
VCLK
POK1
125% VFB2
90% VFB1
OV2
FB2
FAULT
LATCH
LOGIC
UV2
OV1
FB1
UV1
70% VFB1
70% VFB2
VOUT2
SOFTSTOP
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
125% VFB1
VOUT1
EN LDO or
ENILIM2
EN LDO or
ENILIM1
10
SOFTSTOP
GND
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APW8812
Typical Application Circuit
VIN : 6V to 25V
LDO5
CLDO5
4.7µF
CIN1
10µF
VOUT1
5V/7A
COUT1
330µF/6.3V
9mΩ
Q1
APM4810
LOUT1
4.7µH
POK
RPOK
200k
CBOOT1
0.1µF
LDO3
VIN
RBOOT1
0
Q2
APM4810
BOOT1
BOOT2
UGATE1
UGATE2
PHASE1
PHASE2
LGATE1
VOUT1
RGND1
20k
OFF
CBOOT2
0.22µF
CIN2
10µF
Q3
APM4810
LOUT2
2.2µH
Q4
APM4810
VOUT2
3.3V/11A
COUT2
330µF/6.3Vx2
4mΩ
RTOP2
13k
VOUT2
FB1
RILIM1
200k
ON
RBOOT2
0
LGATE2
PGND
PGND
RTOP1
30k
CLDO3
4.7µF
TON
FB2
ENILIM1 ENILIM2
SKIP#
EN LDO
REF
GND
GND
RILIM2
200k
RGND2
20k
CREF
0.1µF
VCLK
CCP1
100nF
CCP2
100nF
D1
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
CCP3
100nF
D2
11
D3
D4
VCP
15V
CCP4
1µF
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APW8812
Function Description
Where FSW is the nominal switching frequency of the converter in PWM mode. Similarly, the on-time of ultrasonic
Constant-On-Time PWM Controller with Input Feed-Forward
The constant-on-time control architecture is a pseudo-
mode is the same with PFM mode. The description of
ultrasonic mode will be illustrated later.
fixed frequency with input voltage feed-forward. This architecture relies on the output filter capacitor’s effective
The load current at handoff from PFM to PWM mode is
given by:
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
ILOAD(PFM to PWM) =
In PFM operation, the high-side switch on-time controlled
by the on-time generator is determined solely by a one-
=
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage. In PWM
operation, the high-side switch on-time is determined by
a switching frequency control circuit in the on-time gen-
1 VIN − VOUT
×
× TON −PFM
2
L
VIN − VOUT
V
1
×
× OUT
2L
F SW
VIN
Forced-PWM Mode
Connect SKIP# to GND for normal Forced-PWM operation.
erator block. The switching frequency control circuit
senses the switching frequency of the high-side switch
The Forced-PWM mode disables the zero-crossing
comparator, which truncates the low-side switch on-time
and keeps regulating it at a constant frequency in PWM
mode. The design improves the frequency variation and
at the inductor current zero crossing. This causes the
low-side gate-drive waveform to become the complement
is more outstanding than a conventional constant-ontime controller, which has large switching frequency varia-
of the high-side gate-drive waveform. This in turn causes
the inductor current to reverse at light loads while UGATE
tion over input voltage, output current and temperature.
Both in PFM and PWM, the on-time generator, which
maintains a duty factor of VOUT/VIN. The benefit of ForcedPWM mode is to keep the switching frequency fairly
senses input voltage on VIN pin, provides very fast ontime response to input line transients.
constant. The Forced-PWM mode is the most useful for
reducing audio frequency noise, improving load-transient
Another one-shot sets a minimum off-time (typ.: 300ns).
The on-time one-shot is triggered if the error comparator
response, and providing sink-current capability for dynamic output voltage adjustment.
is high, the low-side switch current is below the currentlimit threshold, and the minimum off-time one-shot has
Ultrasonic Mode
timed out.
Connecting SKIP# to LDO3 or LDO5 for ultrasonic mode.
Pulse-Frequency Modulation (PFM) Mode
The ultrasonic mode activates a unique PFM mode with
a minimum switching frequency of 37kHz. The minimum
Connect SKIP# to REF for normal PFM operation. In PFM
frequency 37KHz of ultrasonic mode eliminates audiofrequency interference in light load condition. It will transit
mode, an automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. This switchover is
to unique PFM mode when output loading makes the
frequency bigger than ultrasonic frequency. In ultrasonic
affected by a comparator that truncates the low-side
switch on-time at the inductor current zero crossing. This
mode, the controller automatically transits to fixed-frequency PWM operation when the load reaches the same
mechanism causes the threshold between PFM and
PWM operation to coincide with the boundary between
critical conduction point (ILOAD(PFM to PWM)).
When the controller detects that no switching has oc-
continuous and discontinuous inductor-current operation
(also known as the critical conduction point). The on-
curred within about 27µs (typ.), an ultrasonic pulse will
occurre. The ultrasonic controller turns on the low-side
time of PFM is given by:
TON - PFM =
V
1
× OUT
FSW
VIN
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
MOSFET first to reduce the output voltage. After feedback
voltage drops below the internal reference voltage, the
12
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APW8812
Function Description (Cont.)
Ultrasonic Mode (Cont.)
Digital Soft-Start
controller turns off the low-side MOSFET and triggers a
The APW8812 integrates digital soft-start circuit to ramp
constant-on-time. When the constant-on-time has
expired, the controller turns on the low-side MOSFET
up the PWMx output voltage of the converter to the programmed regulation set point at a predictable slew rate.
again until the inductor current is below the zero-crossing threshold. The behavior is the same with PFM mode.
The slew rate of PWMx output voltage is internally controlled to limit the inrush current through the output capacitors during soft-start process. When the ENILIMx pin
is pulled above the rising threshold voltage, the related
Reference Voltages and Linear Regulator
(REF and LDO3/5)
PWM initiates a soft-start process to ramp up the output
voltage. The soft-start interval is 1.7ms(typ.) and inde-
The 2V reference, REF, is accurate to ±1% overtemperature. Bypass to GND with a 0.1µF (minimum)
capacitor. REF can source up to 50µA for external loads.
pendent of the UGATE switching frequency.
However, avoid loading REF if extremely accurate specifications for both the main output voltages and REF are
Enable Controls
The APW8812 has two independent enable controls for
PWM and LDO. When the ENLDO pin is higher than 0.8V,
essential. In addition, REF voltage must be bigger than
its rising enable threshold, and then the LDO output starts
the REF, LDO3 and LDO5 are enabled to standby mode.
It means that the PWM1 and PWM2 are ready to enable at
to rise up.
The LDO3 and LDO5 regulators can supply up to 100mA
this mode. When the ENPWM pin is high (ENILIMx=1) at
standby mode, the PWMx initiates a soft-start process to
for external loads. Bypass to GND with a minimum of
2.2µF ceramic capacitor for stability. When ENLDO is
ramp up the output voltage. The PWM1 and PWM2 are
enabled, the VLDO3 is fixed 3.33V and the VLDO5 is fixed 5V in
standby mode. When PWMx output voltage is over whose
controlled individually by ENILIM1 and ENILIM2. When
ENLDO, ENILIM1 and ENILIM2 are low, the chip is in its
bypass threshold(PWM1 is 4.7V and PWM2 is 3.15V), the
switchover between the internal LDOx and VOUTx is
low-power shutdown state. The APW8812 only consumes
20µA of quiescent current while in shutdown. When the
workable. These actions change the current path to power
the loads from the PWMx regulateon voltage, rather than
ENLDO is higher than 2.4V and ENILIM1 is high
(ENILIM1=1), the clock signal becomes available from
from the internal linear regulator.
VCLK pin. Both PWM outputs are discharged to 0V
through a 25Ω switch and both LDO outputs are dis-
Power-On-Reset
charged to 0V through a 40W switch in shutdown mode.
Driving ENILIM1 and ENILIM2 (logic AND) or ENLDO be-
A Power-On-Reset (POR) function is designed to prevent
wrong logic controls. The POR function continually moni-
low 0.4V clears the over-voltage, under-voltage and overtemperature fault latches.
tors the supply voltage on the LDO5 pins. LDO5 POR
circuitry inhibits wrong switching. When the rising VLDO5
voltage reaches the rising POR threshold (4.2V typ.), the
output voltages begin to ramp up. When the LDO5 volt-
Charge Pump
The condition for the 270kHz clock signal to be used is
that the ENLDO is higher than 2.4V and ENILIM1 is high
age is lower than 4.1V(typ.) or LDO3 voltage is lower than
2.5V(typ.), both switch power supplies are shut off. This
(ENILIM1=1). When VOUT1 regulates at 5V and the clock
signal uses VOUT1 as its power supply, the charge pump
is non-latch protection. LDO5 POR threshold could reset
the under-voltage, over-voltage.
circuit can generate approximately 15V DC voltage. The
example of charge pump circuit is shown in typical application circuit.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
13
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APW8812
Function Description (Cont.)
Soft-Stop (PWMs)
ger than the value of current-limit threshold, the output
In the event of PWM under-voltage or shutdown, the chip
enables the soft-stop function. The soft-stop function dis-
voltage will fall out of the required regulation range. The
under-voltage continually monitors the setting output volt-
charges the PWM output voltages to GND through an
internal 25Ω switch. The reference remains active to pro-
age after soft-start is completed. If a load step is strong
enough to pull the output voltage lower than the under-
vide an accurate threshold and to provide over-voltage
protection.
voltage threshold for at least 2µs, the PWM controller starts
a soft-stop process to shut down the output gradually. As
Power Sequencing
long as either of PWM channels triggers under-voltage,
both of PWM channels active under-voltage protection
and latched off when the soft-stop process is completed.
The under-voltage threshold is 70% of the nominal out-
ENILIM1, ENILIM2 and ENLDO are enable signals for
PWM1, PWM2 and LDOs. In the single channel mode,
when ENILIM1 or ENILIM2 higher than 630mV, the PWM
put voltage. Under-voltage protection is ignored for at least
2ms (typ.) after a rising edge on EN. Toggling ENLDO or
controller enables the respective outputs, and when
ENILIM1 or ENILIM2 is lower than 600mV, it disables the
ENPWM signal will clear the latch and bring the chip back
to operation.
respective outputs. Also, ENILIM1 and ENILIM2 signal
timing will control PWM1 and PWM2 power-up sequence.
Over-Voltage Protection (OVP)
If ENILIMx pin is high (ENILIMx=1) while other channel is
starting up, its soft-start will be postponed until the other
Should the output voltage of VOUT1 and VOUT2 increase over
25% of the setting voltage due to the high-side MOSFET
channel reaches regulation. On the other hand, if both
ENILIM1 and ENILIM2 become high state at the same
failure or for other reasons, the over-voltage protection
will active. As long as either of PWM channels triggers
time (within 60µs), both channels ramp up at the same
time. About power off sequencing, both supplies begin
over-voltage, both of PWM channels active over-voltage
their power-down sequence immediately when the first
supply turns off.
protection. Over-voltage protection will force the low-side
MOSFET gate driver fully turn on. This action actively pulls
Power Good Indicator (PWMs)
down the output voltage. When the OVP occurs, the POK
pin will pull down and latch-off the converter. This OVP
POK is actively held low in shutdown, standby, and softstart. In the soft-start process, the POK is an open-drain
scheme only clamps the voltage overshoot, and does not
invert the output voltage when otherwise activated with a
output, and it is released with enable delay after the latest
ENILIMx goes high (about 2ms typ.). In normal operation,
continuously high output from low-side MOSFET driver.
It’s a common problem for OVP schemes with a latch.
the POK window is from 90% to its OVP threshold of the
converter reference voltage. Both of VOUT1 and VOUT2
Once an over-voltage fault condition is set, it can be reset
by toggling ENLDO or ENILIM1 and ENILIM2 (logic AND)
have to stay within this window for POK to be high (AND
gated). In order to prevent false POK drop, capacitors need
signal.
Over-Temperature Protection
to parallel at the output to confine the voltage deviation
with severe load step transient.
When the junction temperature increases above the ris-
Under-Voltage Protection (PWMs)
ing threshold temperature 160°C, the IC will enter the
over-temperature protection (OTP). When the OTP occurs,
REF, LDO and PWM controllers circuitry shuts down. It is
non-latch protection.
In the process of operation, if a short-circuit occurs, the
output voltage will drop quickly. When load current is big-
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
14
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APW8812
Function Description (Cont.)
Where VENILIMX is the voltage at the ENILIMx pin. RDS(ON) is
the low side MOSFETs conducive resistance. ILIMIT is the
Current-Limit (PWMs)
The current-limit circuit employs a “valley” current-sensing algorithm (See Figure 1). The APW8812 uses the
setting current-limit threshold. ILIMIT can be expressed as
IOUT minus half of peak-to-peak inductor current.
low-side MOSFET’s RDS(ON) of the synchronous rectifier
as a current-sensing element. If the magnitude of the
The PCB layout guidelines should ensure that noise and
DC errors do not corrupt the current-sense signals at
current-sense signal at PHASE pin is above the currentlimit threshold, the PWM is not allowed to initiate a new
PHASE. Place the hottest power MOSEFTs as close to
the IC as possible for best thermal coupling. When com-
cycle. The actual peak current is greater than the currentlimit threshold by an amount equal to the inductor ripple
bined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance.
current. Therefore, the exact current-limit characteristic
and maximum load capability are a function of the sense
ENILIM
resistance, inductor value, and input voltage.
INDUCTOR CURRENT
IPEAK
IOUT
VENILIM RILIM
VCC
ILIMIT
0
10µA
9R
∆I
TO CURRENT
LIMIT LOGIC
R
Time
Figure 2. Current-Limit Setting Block Diagram
Figure 1. Current-Limit Algorithm
Both PWM controllers use the low-side MOSFETs onresistance RDS(ON) to monitor the current for protection
against shorted outputs. The MOSFET’s R
is varied
DS(ON)
by temperature and gate to source voltage, the user
should determine the maximum R
in manufacture’s
DS(ON)
datasheet.
The current-limit threshold of APW8812 is adjusted with
an external resistor. The ENILIMx pin adjustment range
is from 700mV to 2V. In the adjustable mode, the currentlimit threshold voltage is 1/10th the voltage at ENILIMx pin.
As shown in Figure 2, The ENILIMx pin can source 10µA.
The voltage at ENILIMx pin is equal to 10µA x RILIM. Connect ILIM to REF for a fixed 200mV threshold. The logic
current-limit threshold is default to 250mV value if ENILIMx
is 5V. The relationship between the sampled voltage VILIM
and the current-limit threshold ILIMIT is given by:
1
× VENILIMX = ILIMIT × R DS ( ON )
10
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
15
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APW8812
Function Description (Cont.)
Table 1. Operating Mode Truth Table
MODE
Run
CONDITION
COMMENT
ENLDO = 1, ENILIMx =1
PWM is in normal operation.
Standby &
Soft-Stop
ENPWM=0, ENLDO=1
If PWMx is in shutdown, discharge switch (25 Ω) connects their
VOUTx to GND. LDOx and REF active.
Shutdown
EN PWM=0 and EN LDO=0
PWMx output discharge switch (25 Ω) connects VOUTx to GND.
LDOx discharge switch (40 Ω) connects LDOx to GND. In this
mode, all circuitry is off.
UVP
OVP
OTP
The internal 25Ω switch turns on to pull low output voltage.
Either VOUT1, or VOUT2 < 70% of nominal output
LDOx and REF are active. Reset by toggling ENILIM1 and
voltage
ENILIM2 (logic AND) or EN LDO single.
LGATE of two PWM channel are forced high. LDOx and REF
Either VOUT1 and VOUT2 > 125% of normal output
active. Reset by toggling ENILIM1 and ENILIM2 (logic AND) or
voltage
ENLDO single.
All circuitry off. It is non-latch protection after the junction
o
TJ > +160 C
temperature cools by 25oC.
Table 2. Power-Up Control Logics
VENLDO
VENILIM1
VENILIM2
LDO5
LDO3
PWM1
PWM2
VCLK
Low
Don’t Care
Don’t Care
OFF
OFF
OFF
OFF
OFF
0.8V ~ 1.6V
Low
Low
ON
ON
OFF
OFF
OFF
0.8V ~ 1.6V
High
High
ON
ON
ON
ON
OFF
0.8V ~ 1.6V
High
Low
ON
ON
ON
OFF
OFF
0.8V ~ 1.6V
Low
ON
ON
OFF
ON
OFF
0.8V ~ 1.6V
High
High
High (after
ENILIM1 is
high without
60µs)
ON
ON
ON
ON (after
PWM1 is
POK)
OFF
High
ON
ON
ON (after
PWM2 is
POK)
ON
OFF
Low
ON
ON
OFF
OFF
OFF
High
ON
ON
ON
ON
ON
> 2.4V
High (after
ENILIM2 is
high without
60µs)
Low
> 2.4V
High
> 2.4V
High
Low
ON
ON
ON
OFF
ON
> 2.4V
Low
ON
ON
OFF
ON
OFF
> 2.4V
High
High
High(after
ENILIM1 is
high without
60µs)
ON
ON
ON
ON (after
PWM1 is
POK)
ON
> 2.4V
High(after
ENILIM2 is
high without
60µs)
High
ON
ON
ON (after
PWM2 is
POK)
ON
ON
0.8V ~ 1.6V
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
16
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APW8812
Application Information
Output Voltage Selection
ripple current occurs at the maximum input voltage. A
The output voltage of PWM1 can be adjusted from 2V to
5.5V with a resistor-driver at FB1 between VOUT1 and
good starting point is to choose the ripple current to be
approximately 30% of the maximum output current.
GND. Using 1% or better resistors for the resistive divider is recommended. The FB1 pin is the inverter input
Once the inductance value has been chosen, selecting
an inductor is capable of carrying the required peak cur-
of the error amplifier, and the reference voltage is 2V.
Take the example, the output voltage of PWM1 is deter-
rent without going into saturation. In some types of
inductors, especially core that is made of ferrite, the ripple
mined by:
current will increase abruptly when it saturates. This will
be result in a larger output ripple voltage.
VOUTI

R
= 2 ×  1 + TOP1
R GND1

Output Capacitor Selection




Output voltage ripple and the transient voltage deviation are factors that have to be taken into consideration when selecting an output capacitor. Higher
Where RTOP1 is the resistor connected from VOUTI to VFB1
and RGND1 is the resistor connected from FB1 to GND.
capacitor value and lower ESR reduce the output ripple
and the load transient drop. Therefore, selecting high
Similarly, the output voltage of PWM2 can be alsoadjusted
from 2V to 5.5V.
performance low ESR capacitors is intended for switching regulator applications. In addition to high frequency
Output Inductor Selection
noise related MOSFET turn-on and turn-off, the output
voltage ripple includes the capacitance voltage drop and
The duty cycle of a buck converter is the function of the
input voltage and output voltage. Once an output voltage
ESR voltage drop caused by the AC peak-to-peak current.
These two voltages can be represented by:
is fixed, it can be written as:
D=
VOUT
VIN
∆VESR
The inductor value determines the inductor ripple current
and affects the load transient reponse. Higher inductor
These two components constitute a large portion of the
total output voltage ripple. In some applications, multiple
value reduces the inductor’s ripple current and induces
lower output ripple voltage. The ripple current can be
capacitors have to be paralleled to achieve the desired
ESR value. If the output of the converter has to support
approxminated by:
IRIPPLE =
IRIPPLE
8COUTFSW
= IRIPPLE × RESR
∆VCOUT =
VIN - VOUT VOUT
×
VIN
FSW × L
another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR
Where FSW is the switching frequency of the regulator.
Increasing the inductor value and frequency will re-
and suppress the voltage ripple to a tolerable level. A
small decoupling capacitor in parallel for bypassing
duce the ripple current and voltage. However, there is a
tradeoff between the inductor’s ripple current and the
the noise is also recommended, and the voltage rating
of the output capacitors must also be considered.
regulator load transient response time.
To support a load transient that is faster than the
A smaller inductor will give the regulator a faster load
transient response at the expense of higher ripple
switching frequency, more capacitors have to be used
to reduce the voltage excursion during load step change.
current. Increasing the switching frequency (FSW ) also
reduces the ripple current and voltage, but it will
Another aspect of the capacitor selection is that the
total AC current going through the capacitors has to be
increase the switching loss of the MOSFETs and the
power dissipation of the converter. The maximum
less than the rated RMS current specified on the capacitors to prevent the capacitor from over-heating.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
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APW8812
Application Information (Cont.)
(CRSS) and maximum output current requirement. The
Input Capacitor Selection
losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and low-
The input capacitor is chosen based on the voltage rating
and the RMS current rating. For reliable operation, select
side MOSFETs, the losses are approximately given by
the following equations:
the capacitor voltage rating to be at least 1.3 times higher
than the maximum input voltage. The maximum RMS
2
Phigh-side = IOUT (1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW
current rating requirement is approximately IOUT/2, where
IOUT is the load current. During power up, the input capaci-
2
Plow-side = IOUT (1+ TC)(RDS(ON))(1-D)
tors have to handle large amount of surge current. In lowduty notebook appliactions, ceramic capacitors are
Where
I
is the load current
OUT
remmended. The capacitors must be connected between
the drain of high-side MOSFET and the source of low-
TC is the temperature dependency of RDS(ON)
FSW is the switching frequency
side MOSFET with very low-impeadance PCB layout.
tSW is the switching interval
D is the duty cycle
MOSFET Selection
The application for a notebook battery with a maximum voltage of 24V, at least a minimum 30V MOSFETs should
Note that both MOSFETs have conduction losses while
the high-side MOSFET includes an additional transi-
be used. The design has to trade off the gate charge with
the RDS(ON) of the MOSFET:
tion loss. The switching internal, t SW , is the function
of the reverse transfer capacitance CRSS. The (1+TC) term
•
is to factor in the temperature dependency of the RDS(ON)
and can be extracted from the “RDS(ON) vs Temperature”
For the low-side MOSFET, before it is turned on, the
body diode has been conducted. The low-side MOSFET
driver will not charge the miller capacitor of this
•
curve of the power MOSFET.
MOSFET.
Layout Consideration
In the turning off process of the low-side MOSFET,
In any high switching frequency converter, a correct layout
is important to ensure proper operation of the regulator.
the load current will shift to the body diode first. The
high dv/dt of the phase node voltage will charge the
With power devices switching at higher frequency, the
resulting current transient will cause voltage spike across
miller capacitor through the low-side MOSFET driver
sinking current path. This results in much less
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
switching loss of the low-side MOSFETs. The duty
cycle is often very small in high battery voltage
of the PWM MOSFET. Before turn-off condition, the
MOSFET is carrying the full load current. During turn-off,
applications, and the low-side MOSFET will conduct most of the switching cycle; therefore, the less
current stops flowing in the MOSFET and is freewheeling
by the lower MOSFET and parasitic diode. Any parasitic
the RDS(ON) of the low-side MOSFET, the less the power
loss. The gate charge for this MOSFET is usually a
inductance of the circuit generates a large voltage spike
during the switching interval. In general, using short and
secondary consideration. The high-side MOSFET
does not have this zero voltage switching
wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And
condition, and because it conducts for less time
compared to the low-side MOSFET, the switching
signal and power grounds are to be kept separating and
finally combined to use the ground plane construction or
loss tends to be dominant. Priority should be given
to the MOSFETs with less gate charge, so that both
single point grounding. The best tie-point between the
signal ground and the power ground is at the negative
the gate driver loss and switching loss will be
minimized.
The selection of the N-channel power MOSFETs are de-
side of the output capacitor on each channel, where there
is less noise. Noisy traces beneath the IC are not
termined by the RDS(ON), reversing transfer capacitance
recommended. Below is a checklist for your layout:
Copyright  ANPEC Electronics Corp.
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18
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APW8812
Application Information (Cont.)
TQFN4x4-24A
Layout Consideration (Cont.)
•
4mm
Keep the switching nodes (UGATEx, LGATEx, BOOTx,
ThermalVia
diameter
0.3mm X 4
and PHASEx) away from sensitive small signal nodes
(REF, ILIMx, and FBx) since these nodes are fast mov-
•
signal traces in parallel with theses traces on any layer.
The signals going through theses traces have both
high dv/dt and high di/dt, with high peak charging and
discharging current. The traces from the gate drivers
•
0.5mm *
0.25mm
2.25 mm
ing signals. Therefore, keep traces to these nodes as
short as possible and there should be no other weak
4mm
0.5mm
to the MOSFETs (UGATEx and LGATEx) should be short
and wide.
2.25 mm
0.46mm
Place the source of the high-side MOSFET and the
drain of the low-side MOSFET as close as possible.
0.4mm
Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of
•
* Just Recommend
the node.
Decoupling capacitor, the resistor dividers, boot
capacitors, and current-limit stetting resistor should
be close to their pins. (For example, place the
decoupling ceramic capacitor near the drain of the
high-side MOSFET as close as possible. The bulk
•
capacitors are also placednear the drain).
The input capacitor should be near the drain of the
upper MOSFET; the high quality ceramic decoupling
capacitor can be put close to the VCC and GND pins;
the output capacitor should be near the loads. The
input capacitor GND should be close to the output ca-
•
pacitor GND and the lower MOSFET GND.
The drain of the MOSFETs (VIN and PHASEx nodes)
should be a large plane for heat sinking. And PHASEx
pin traces are also the return path for UGATEx. Con-
•
nect these pins to the respective converter’s upper
MOSFET source.
The controller used ripple mode control. Build the resistor divider close to the FB1 pin so that the high
impedance trace is shorter when the output voltage is
in ad justable mode. And the FB1 pin traces can’t be
•
close to the switching signal traces (UGATEx, LGATEx,
BOOTx, and PHASEx).
The PGND trace should be a separate trace, and independently go to the source of the low-side MOSFETs
for current-limit accuracy.
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
19
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APW8812
Package Information
TQFN4x4-24A
A
E
b
D
Pin 1
A1
A3
NX
D2
aaa c
L K
E2
Pin 1 Corner
e
S
Y
M
B
O
L
TQFN4x4-24A
MILLIMETERS
INCHES
MIN.
MAX.
MIN.
MAX.
A
0.70
0.80
0.028
0.032
A1
0.00
0.05
0.000
A3
0.20 REF
0.002
0.008 REF
b
0.18
0.30
0.007
0.012
D
3.90
4.10
0.154
0.161
D2
2.00
2.50
0.079
0.098
0.161
0.098
E
3.90
4.10
0.154
E2
2.00
2.50
0.079
0.45
0.014
e
L
K
0.50 BSC
0.35
0.020 BSC
0.20
aaa
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
0.018
0.008
0.08
0.003
20
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APW8812
Carrier Tape & Reel Dimensions
P0
P2
P1
A
B0
W
F
E1
OD0
K0
A0
A
OD1 B
B
T
SECTION A-A
SECTION B-B
H
A
d
T1
Application
TQFN4x4-24A
A
H
T1
C
d
D
W
E1
F
330.0±2.00
50 MIN.
12.4+2.00
-0.00
13.0+0.50
-0.20
1.5 MIN.
20.2 MIN.
12.0±0.30
1.75±0.10
5.5±0.05
P0
P1
P2
D0
D1
T
A0
B0
K0
2.0±0.05
1.5+0.10
-0.00
1.5 MIN.
0.6+0.00
-0.40
4.30±0.20
4.30±0.20
1.25±0.20
4.0±0.10
8.0±0.10
(mm)
Devices Per Unit
Package Type
Unit
Quantity
TQFN4x4-24A
Tape & Reel
3000
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Rev. A.2 - Sep., 2012
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APW8812
Taping Direction Information
TQFN4x4-24A
USER DIRECTION OF FEED
Classification Profile
Supplier Tp≧Tc
User Tp≦Tc
TC
TC -5oC
User tp
Supplier tp
Tp
tp
Temperature
Max. Ramp Up Rate = 3oC/s
Max. Ramp Down Rate = 6oC/s
TL
Tsmax
TC -5oC
t
Preheat Area
Tsmin
tS
25
Time 25oC to Peak
Time
Copyright  ANPEC Electronics Corp.
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APW8812
Classification Reflow Profiles
Profile Feature
Sn-Pb Eutectic Assembly
Pb-Free Assembly
100 °C
150 °C
60-120 seconds
150 °C
200 °C
60-120 seconds
3 °C/second max.
3 °C/second max.
183 °C
60-150 seconds
217 °C
60-150 seconds
See Classification Temp in table 1
See Classification Temp in table 2
Time (tP)** within 5°C of the specified
classification temperature (Tc)
20** seconds
30** seconds
Average ramp-down rate (Tp to Tsmax)
6 °C/second max.
6 °C/second max.
6 minutes max.
8 minutes max.
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate
(Tsmax to TP)
Liquidous temperature (TL)
Time at liquidous (tL)
Peak package body Temperature
(Tp)*
Time 25°C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Package
Thickness
<2.5 mm
≥2.5 mm
Volume mm
<350
235 °C
220 °C
3
Volume mm
≥350
220 °C
220 °C
3
Table 2. Pb-free Process – Classification Temperatures (Tc)
Package
Thickness
<1.6 mm
1.6 mm – 2.5 mm
≥2.5 mm
Volume mm
<350
260 °C
260 °C
250 °C
3
Volume mm
350-2000
260 °C
250 °C
245 °C
3
Volume mm
>2000
260 °C
245 °C
245 °C
3
Reliability Test Program
Test item
SOLDERABILITY
HOLT
PCT
TCT
HBM
MM
Latch-Up
Method
JESD-22, B102
JESD-22, A108
JESD-22, A102
JESD-22, A104
MIL-STD-883-3015.7
JESD-22, A115
JESD 78
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
23
Description
5 Sec, 245°C
1000 Hrs, Bias @ Tj=125°C
168 Hrs, 100%RH, 2atm, 121°C
500 Cycles, -65°C~150°C
VHBM≧2KV
VMM≧200V
10ms, 1tr≧100mA
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APW8812
Customer Service
Anpec Electronics Corp.
Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
Copyright  ANPEC Electronics Corp.
Rev. A.2 - Sep., 2012
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