STMicroelectronics AN3994 One of the bigger challenge Datasheet

AN3994
Application note
Managing the best in class MDmesh™ V and MDmesh™ II
super junction technologies: driving and layout key notes
Introduction
One of the bigger challenges of the 21st century is to deal with the growing need for power
and, at the same time, the necessity of product compactness.
The new MDmesh™ V series from STMicroelectronics, based on the super junction
concept, meets these targets by offering an extremely low RDS(on) value in a given package,
unobtainable in standard HV MOSFETs.
In addition to the dramatic reduction of RDS(on), super junction MOSFETs are extremely fast
in transients and this may lead to some issues when a better performing technology
replaces an older version on the same board with the same driving network.
The two main components in the ST super junction MOSFET family (MDmesh™ II and
MDmesh™ V) are analyzed and compared in terms of energy losses, voltage, and current
rates. It is shown how the external driving network impacts on their performances.
Furthermore, a separate section is dedicated to the layout parasitic effects and their impact
on MOSFET behavior.
It is clear in the end that layout can be crucial, especially when managing very fast
transients, and it must be carefully planned in order to help the MOSFET exploit its best
potential.
December 2011
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www.st.com
Contents
AN3994
Contents
1
ST multidrain technology evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Parasitic capacitances overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3
MOSFET standard turn-on and turn-off analysis . . . . . . . . . . . . . . . . . 11
4
Gate charge curve impact on dynamic responses . . . . . . . . . . . . . . . 15
5
Latest ST MD II and MD V technology at a glance . . . . . . . . . . . . . . . . 20
6
MD II and MD V: which is the lowest loss one? . . . . . . . . . . . . . . . . . . 21
7
6.1
STB42N65M5 vs. STW48NM60N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2
STP35N65M5 vs. STB36NM60N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.3
STP21N65M5 vs. STP24NM60N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4
STP16N65M5 vs. STP18NM60N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.5
Comments about energy ON comparison . . . . . . . . . . . . . . . . . . . . . . . . 33
6.6
Comments about energy OFF comparison . . . . . . . . . . . . . . . . . . . . . . . 33
MOSFET critical parameters in high switching environments . . . . . . 36
7.1
Parasitic inductance influence on switching losses . . . . . . . . . . . . . . . . . 36
7.2
Common source inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
7.3
Minimizing common source inductance: layout optimization and Kelvin
source connection on STW77N65M5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
7.4
Minimizing common source inductance impact at turn-off: negative
VGMoff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.5
8
2/53
Switching loop inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
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AN3994
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Standard HV MOSFET device cross section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MD device cross section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Silicon ideal limit, SJ limit and ST MD V position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ST’s HV technology evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
N-channel Power MOSFET structure and intrinsic capacitances . . . . . . . . . . . . . . . . . . . . . 8
Equivalent model of Power MOSFET intrinsic capacitances . . . . . . . . . . . . . . . . . . . . . . . . 8
Clamped inductive load test circuit used to carry out the dynamic tests on the MOSFETs 10
Turn-on of a MOSFET in a clamped inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Equivalent capacitive model of a MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Turn-off of a MOSFET in a clamped inductive load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Vg(t) curve measured on STB42NM60N @16 A, 400 V, IG=1.5 mA . . . . . . . . . . . . . . . . . 17
Vg(t) curve measured on STW48NM60N @16 A, 400 V, IG=1.5 mA . . . . . . . . . . . . . . . . 17
Turn-on of STB42N65M5 @16 A, 400 V, 47 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-on of STW48NM60N @16 A, 400 V, 47 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-off of STB42N65M5 @16 A, 400 V, 47 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Turn-off of STW48NM60N @16 A, 400 V, 47 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Minimum RDS(on) per package achievable by MD II and MD V . . . . . . . . . . . . . . . . . . . . 20
STB42N65M5 vs. STW48NM60N Eon @ 8 A/16 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . 21
STB42N65M5 vs. STW48NM60N di/dt at turn-on @ 8 A/16 A, 400 V . . . . . . . . . . . . . . . . 21
STB42N65M5 vs. STW48NM60N dv/dt at turn-on @ 8 A/16 A 400 V . . . . . . . . . . . . . . . . 22
STB42N65M5 vs. STW48NM60N zoom of dv/dt at turn-on @ 8 A/16 A 400 V . . . . . . . . . 22
STB42N65M5 vs. STW48NM60N Eoff @ 8 A/16 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . 23
STB42N65M5 vs. STW48NM60N di/dt at turn-off @ 8 A/16 A, 400 V . . . . . . . . . . . . . . . . 23
STB42N65M5 vs. STW48NM60N dv/dt at turn-off @ 8 A/ 16 A, 400 V . . . . . . . . . . . . . . . 24
STP35N65M5 vs. STB36NM60N Eon @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . 24
STP35N65M5 vs. STB36NM60N di/dt at turn-on @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . . 25
STP35N65M5 vs. STB36NM60N dv/dt at turn-on @ 7.5 A/15 A 400 V . . . . . . . . . . . . . . . 25
STP35N65M5 vs. STB36NM60N Eoff @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . 26
STP35N65M5 vs. STB36NM60N di/dt at turn-off @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . . 26
STP35N65M5 vs. STB36NM60N dv/dt at turn-off @ 7.5 A/15 A, 400 V . . . . . . . . . . . . . . 27
STP21N65M5 vs. STP24NM60N Eon @ 4 A/ 8 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . . 27
STP21N65M5 vs. STP24NM60N di/dt at turn-on @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . 28
STP21N65M5 vs. STP24NM60N dv/dt at turn-on @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . 28
STP21N65M5 vs. STP24NM60N Eoff @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . . . 29
STP21N65M5 vs. STP24NM60N di/dt at turn-off @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . 29
STP21N65M5 vs. STP24NM60N dv/dt at turn-off @ 4 A/8 A, 400 V . . . . . . . . . . . . . . . . . 30
STP16N65M5 vs. STP18NM60N Eon @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STP16N65M5 vs. STP18NM60N di/dt at turn-on @ 3 A/ 6 A, 400 V . . . . . . . . . . . . . . . . . 31
STP16N65M5 vs. STP18NM60N dv/dt at turn-on @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . 31
STP16N65M5 vs. STP18NM60N Eoff @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STP16N65M5 vs. STP18NM60N di/dt at turn-off @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . 32
STP16N65M5 vs. STP18NM60N dv/dt at turn-off @ 3 A/6 A, 400 V . . . . . . . . . . . . . . . . . 33
Equivalent capacitive model of a MOSFET with parasitic inductances at turn-on . . . . . . . 36
Turn-on of STW77N65M5@400 V, 13 A, 25 °C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Equivalent driving circuit of a MOSFET at turn-on with parasitic source inductance . . . . . 38
Simplified equivalent series resonant model of the driving circuit of a MOSFET . . . . . . . . 39
Gate driving and main switching loops for a MOSFET in a BOOST-like topology . . . . . . . 40
STW77 energy ON difference between the standard layout and the optimized layout . . . 41
STW77 energy OFF difference between the standard layout and the optimized layout. . . 41
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List of figures
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Figure 60.
Figure 61.
Figure 62.
Figure 63.
Figure 64.
Figure 65.
Figure 66.
Figure 67.
Figure 68.
Figure 69.
Figure 70.
Figure 71.
Figure 72.
Figure 73.
Figure 74.
Figure 75.
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AN3994
STW77N65M5 Eoff @ 20 A, 2.2 W with non-optimized common path. . . . . . . . . . . . . . . . 42
STW77N65M5 Eoff @ 20 A, 2.2 W with non-optimized common path. . . . . . . . . . . . . . . . 42
STW77N65M5 Eoff @ 20 A, 2.2 W with optimized common path . . . . . . . . . . . . . . . . . . . 42
STW77N65M5 Eoff @ 40 A, 2.2 W with non-optimized common path. . . . . . . . . . . . . . . . 43
STW77N65M5 Eoff @ 40 A, 2.2 W with non-optimized common path. . . . . . . . . . . . . . . . 43
STW77N65M5 Eoff @ 40 A, 2.2 W, 400 V with optimized common path . . . . . . . . . . . . . 43
STW77N65M5 Eon@20 A, 2.2 W with no n-optimized common path . . . . . . . . . . . . . . . . 44
STW77N65M5 Eon@20 A, 2.2 W with non-optimized common path. . . . . . . . . . . . . . . . . 44
STW77N65M5 Eon@20 A, 2.2 W with optimized common path . . . . . . . . . . . . . . . . . . . . 44
STW77N65M5 Eon@20 A, 2.2 W with optimized common path . . . . . . . . . . . . . . . . . . . . 44
STW77N65M5 Eon@40 A, 2.2 W with non-optimized common path. . . . . . . . . . . . . . . . . 45
STW77N65M5 Eon@40 A, 2.2 W with non-optimized common path. . . . . . . . . . . . . . . . . 45
STW77N65M5 Eon@40 A, 2.2 W with optimized common path . . . . . . . . . . . . . . . . . . . . 45
STW77N65M5 Eon@40 A, 2.2 W with optimized common path . . . . . . . . . . . . . . . . . . 45
Schematic of 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STW77N65M5 energy ON difference between the optimized layout (3-pin) and 4-pin
solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
STW77N65M5 energy ON difference between the optimized layout (3-pin) and 4-pin
solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STW77N65M5 energy OFF difference between the optimized layout (3-pin) and 4-pin
solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
STW77N65M5 Eoff@20 A, 2.2 W, 400 V 4-pin solution. . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STW77N65M5 Eon@20 A, 2.2 W 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STW77N65M5 Eon @20 A, 2.2 W 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
STW77N65M5 Eon@40 A, 2.2 W 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STW77N65M5 Eon@40 A, 2.2 W 4-pin solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Basic driving stage of a Power MOSFET at turn-off with negative VGM . . . . . . . . . . . . . . 49
STW77N65M5 Eoff@52 A, 4.7 W, 400 V, VGMoff=-5 V . . . . . . . . . . . . . . . . . . . . . . . . . . 50
STW77N65M5 Eoff@52 A, 4.7 W, 400 V, VGMoff=-5 V . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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AN3994
ST multidrain technology evolution
At the beginning of 2000, STMicroelectronics introduced the super junction MOSFET
technology to the market, the basic structure of which is clear from Figure 1:
Figure 1.
Standard HV MOSFET device cross section
-ETAL
3OURCE
"ODY
!
. REGION
$RAIN
"
3UBSTRATE
!-V
Figure 2.
MD device cross section
-$MESH˜
-ETAL
3OURCE
/SFHJPO
"ODY
1SFHJPO
1
ST multidrain technology evolution
!
$RAIN
"
3UBSTRATE
!-V
As concerns standard MOSFET technology, designers understand that RDS(on) * area and
breakdown voltage are associated with a theoretical limit which strictly depends on the
material and can not be overcome. Development efforts of the major suppliers have mainly
focused on making the RDS(on)* area as close as possible to this physical limit, by reducing
the most important contributions of a high voltage Power MOSFET to the total RDS(on).
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ST multidrain technology evolution
Figure 3.
AN3994
Silicon ideal limit, SJ limit and ST MD V position
0'
6L ,*%7
6L,*%7
2
$3ON
AREA M/HM CM 6L6-³/LPLW´
"REAKDOWN VOLTAGE 6
!-V
RJFET and RCHANNEL were significantly lowered by increasing the cell density and
optimizing their structure, and by also reducing, at the same time, the channel length.
Thanks to the continuos optimization of resistivity and the thickness of N-Drift, the REPY
contribution has been lowered, but the need to guarantee the same breakdown voltage and
avalanche capability establishes the well known “Silicon Ideal limit”, as shown in Figure 3.
The MD concept, based on SJ technology, has overcome this limit: through the p-doped
column insertion under the device strips, it has been possible to significantly lower the
resistivity of the epitaxial N region without compromising the breakdown capability and
enabling a dramatic reduction in RDS(on): the particular p-column geometry and the
alternating of p regions with n regions allows a constant electric field in the whole drain
volume despite the low resistivity in the conducting region: as a direct consequence, it was
possible to achieve an RDS(on) * area reduction, previously not possible, by keeping the
same voltage capability.
From this starting point, MD technology moved towards RDS(on) continuous optimization, as
seen in Figure 4.
6/53
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AN3994
ST multidrain technology evolution
Figure 4.
ST’s HV technology evolution
-$MESH
AREA M/HM CM
-$MESH ))
-$MESH 6
2
$3ON
-$MESH 6)
3TART PRODUCTION YEAR
!-V
The MD II generation has already optimized the RDS(on) * area of about 40% compared to
the first MD version, with an average value of about 30 mΩ*cm2.
The excellent achievement of the MD II enabled STMicroelectronics to establish a new
milestone in the power switch arena with the last MD V generation.
Thanks to a proprietary ST technology, an extremely low value of p-column distance has
been reached, therefore overcoming the physical limit imposed by the diffusion process.
Additionally, the geometry of the p-columns was also optimized by a more effective diffusion
process which enabled up to 40% reduction of RDS(on) * area if compared to the previous
MD II generation.
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Parasitic capacitances overview
2
AN3994
Parasitic capacitances overview
When dealing with high speed switching applications, the most critical MOSFET parameters
limiting its dynamic response are the parasitic capacitances.
Figure 5 shows the physical origin of the parasitic component in an N-channel Power
MOSFET:
Figure 5.
N-channel Power MOSFET structure and intrinsic capacitances
Source metal
Intermediate dielectric
4
Polysilicon gate
Gate oxide
N++
source
6
5
1
2
3
N++ source
P/P+ Body
P/P+ Body
7
N-
drain
AM10768v1
Figure 6.
Equivalent model of Power MOSFET intrinsic capacitances
$
#HE
'
#ET
#HT
3
!-V
Cgs is mainly due to the overlap between the gate and the source metallization (“3” and “4”
components in Figure 5 and 6). Capacitors “5” and “6” are MIS (metal-insulatorsemiconductor) capacitors between the gate and the p-body. The Cgs value is linked to the
geometry of the device and it's almost independent of the voltage applied.
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AN3994
Parasitic capacitances overview
Cgd is the sum of two contributions: the first one is related to the overlap of the JFET region
and the gate electrode (“1” component in Figure 5 and 6). The second component is the
capacitance of the depletion region under the gate (“2” component in Figure 5 and 6).
The equivalent capacitance Cgd decreases as the drain source voltage applied increases.
Cds capacitance is the junction capacitance of the body-drain diode (“7” components in
Figure 5 and 6). Its value varies as the p-body / n-drift junction thickness changes with the
VDS applied, according to the following formula:
Equation 1
C ds ∝ ( VDS )
The relevant datasheets report the static equivalent capacitance values in the electrical
characteristics as the following:
Equation 2
C iss = C gs ⊕ C gd
measured @ VGS=0 V, VDS=25 V
Equation 3
Crss = C gd
measured @ VGS=0 V, VDS=25 V
Equation 4
C oss = C ds ⊕ C gd
measured @ VGS=0 V, VDS=25 V
Cgd is also called “Miller capacitance”, as it’s placed in the feedback loop between the input
and the output of the device. It's value can be much larger in switching operations,
contributing to the achievement of a dynamic input capacitance of the MOSFET larger than
the sum of the static capacitances.
In order to simplify the switching performance comparison among MOSFETs from different
manufacturers or even different MOSFET technologies of the same brand, it can be useful
to consider the gate charge parameters instead of capacitances. Figure 7 shows a clamped
inductive load switching test circuit which helps to analyze the parasitic capacitance
behavior during the MOSFET switching. The considerations reported in the following
sections are valid if the driving source is supposed to provide any Ig current to the MOSFET
input capacitances and the circuit is ideal with no stray inductances.
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Parasitic capacitances overview
Figure 7.
AN3994
Clamped inductive load test circuit used to carry out the dynamic tests
on the MOSFETs
6 $$ 6
6 '- 6
),
2'ON
,
$
)$
2'OFF
!-V
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AN3994
3
MOSFET standard turn-on and turn-off analysis
MOSFET standard turn-on and turn-off analysis
The turn-on event of the MOSFET can be split into four time intervals, as Figure 8 shows.
The analysis starts from the hypothesis of a constant load current IL flowing through the
inductor L and the diode D before the commutation (turn-on) process.
After the MOSFET input has been connected to the voltage source (VSOURCE=VGM), the
VGS voltage starts to increase (PHASE “1”), but no drain current can flow till the VGS
reaches the Vth value. The MOSFET is still in OFF state, while the diode is conducting the
load current. The gate current IGon is charging the Ciss capacitance.
The ON gate current during the t0 to t2 time interval follows the exponential trend of
Equation 5:
Equation 5
t
−
V
IGon(t 0 ,t 2 )( t) = GM e RGtot Ciss
RGtot
RGtot theoretically includes the RGon value (see Figure 7) and the other resistive
components of the driving circuit.
Equation 6 assumes that the Ciss (VDS) is constant during this time interval, which is a
correct hypothesis, due to a very low dependence of the input capacitances on the VDS
applied.
Phase “2” is the phase of ID rise. When VGS reaches the threshold value, ID begins to rise
and at the same time, the load current begins to be shared between the diode and the
MOSFET. Until the ID is lower than the load current and the diode is in an ON state, the VDS
stays constant at the maximum value except for a little drop in the real voltage waveform due
to the stray inductances along the switching circuit. The IGon current is still charging the
Cgs+Cgd capacitances. At t2 instant the VGS reaches the plateau value.
The rate of ID current during the t1 to t2 time interval satisfies Equation 6:
Equation 6
dID gmIGon( t1, t2 )
=
dt
Ciss
During phase “3” and phase “4” VGS is at a constant value, ID has reached the full load
condition and the diode is turned off. This enables the VDS to decrease. The MOSFET is in
the active region and the IG current is now flowing only through the Cgd capacitance that’s
discharging from a starting value of (VDS-VPL), while the Cds capacitance is discharging
from VDS down to the VDS(on) value.
The ON gate current during the time interval (t2 to t4) is a fixed value and it satisfies
Equation 7:
Equation 7
IGon(t 2 ,t 4 ) =
VGM − VPL
RGtot
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MOSFET standard turn-on and turn-off analysis
Figure 8.
AN3994
Turn-on of a MOSFET in a clamped inductive load
)6
0(!3% hv
6 $3
v
0(!3%h 0(!3%
0(!3% hv
0(!3% hv
0(!3% hv
)$
)'
6 '-
6'3
6'3TH
1TH 1
T
T
1
T
1
1
T
T
T
!-V
Figure 9.
Equivalent capacitive model of a MOSFET
,
$
6$$
$
2'
6'$
#'$
)$'
'
6'-
)$3
)$
6'3
#'3
6$3
#$3
)'3
3
!-V
Falling rate of VDS during the (t2 to t4) time interval is shown in Equation 8:
Equation 8
V − VPL
dVDS IGon( t 2 ,t 4 )
=
= GM
dt
C gd
R Gtot ⊗ C gd
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AN3994
MOSFET standard turn-on and turn-off analysis
During phase “4” the voltage across the MOSFET has reached the ID*RDS(on)=VDS(on)
value, and the device has entered the ohmic region. The VGS increases up to the maximum
value VGM.
Figure 10. Turn-off of a MOSFET in a clamped inductive load
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Similarly, the turn-off event can be split into four time intervals, as shown in Figure 10.
Phase “1” is the time interval needed to discharge the input capacitance Ciss from its initial
value (+VGM) down to the plateau level. The gate current is supplied by both Cgs and Cgd
capacitors.
The IGoff current during the time interval (t'0 to t'1) follows the same exponential trend of the
turn-on during the (t0, t2) time interval according to Equation 9:
Equation 9
IGoff(t ' ,t ' ) = −IGon( t0 ,t 2 )
0 1
During phase “2” the gate voltage has reached a fixed value (the plateau level) and the VDS
rises from ID*RDS(on)=VDS(on) up to the final value, where it is clamped by the diode. As VGS
is constant in this time interval, the OFF gate current flowing through the RGtot is the
charging current of the Cgd that is charging from a negative starting voltage value (see
Figure 8 for reference) up to the VDS value, while the Cds capacitor is charging up to VDS.
IGoff current during this phase follows Equation 10:
Equation 10
IGoff(t ' ,t ' ) =
1 3
VPL
RGtot
Phase “3” is the phase of the diode turn-on: load current begins to be shared between the
MOSFET and the diode while the VGS decreases from the plateau down to the Vth value.
Doc ID 022380 Rev 1
13/53
MOSFET standard turn-on and turn-off analysis
AN3994
This causes the lowering of the drain current down to zero. During this time interval, the gate
current is mainly coming from the Cgs capacitor.
IGoff current during this phase has the following expression:
Equation 11
t − t '3
−
V
IGoff( t' ,t ' ) (t ) = PL e RGtotC iss
3 4
R Gtot
t>t‘3
During phase “4”, the Ciss fully discharges and the VGS reaches the zero value.
14/53
Doc ID 022380 Rev 1
AN3994
4
Gate charge curve impact on dynamic responses
Gate charge curve impact on dynamic responses
When generally dealing with MOSFET turn-on and turn-off, it implies the charging or
discharging of its input capacitances. The charge transfer needed to change the voltage
across these capacitors leads to unavoidable power losses which are dissipated on the gate
resistors in the driving path during each switching cycle. A second but not less significant
aspect is that the amount of charge directly impacts how fast the MOSFET response is
during transients. For this reason, the gate charge curve analysis displayed in the datasheet
is quite important in order to obtain a first outlook of the MOSFET dynamics.
As for the turn-on event, the Qth charge supplied during the t0 to t1 (Figure 8) time interval is
approximately:
Equation 12
Q th = Ciss ⊗ Vth
As VGS reaches the threshold value, Vth and ID start to flow. The charge to be provided
during the (t1 to t2) time interval can be calculated by integrating the IGon (t1 to t2) current as
follows:
Equation 13
t
t2
Q12
Vgm − RG TOT Ciss
=
e
dt
R Gtot
∫
t1
if we assume:
Equation 14
t 2 = t1 + Δt
Equation 13 can be solved and the value of ΔT can be calculated as:
Equation 15
Δt = t 2 − t1 = −R Gtot ⊗ Ciss ⊗ ln(1 −
Q 12
Q th
)
The total charge supplied to the gate during the time interval (t2 to t3) can be easily
calculated by multiplying the constant IGon value with the time interval (t2 to t3) as follows:
Equation 16
Q 23 = IGon(t 2 ,t 3 ) ⊗ (t 3 − t 2 ) =
VGM − VPL
R Gtot
⊗ (t3 − t2 )
Equation 17
t3 − t2 =
Q23
(VGM − VPL )
Doc ID 022380 Rev 1
R Gtot
15/53
Gate charge curve impact on dynamic responses
AN3994
Time intervals (t2 - t1) and (t3 - t2) theoretically calculated by Equation 5 and 17 are the two
ones mainly involved in the turn-on event.
As similarly done for the turn-on, once the Q'23+Q'34 = Q23+Q12 (if referred to the turn-off,
see Figure 10) portion of the gate charge has been read from the gate charge curve, the two
time intervals (t'3 - t'2) and (t'4 - t'3) which are mainly involved in the turn-off event can be
theoretically calculated as follows:
Equation 18
( t'3 − t '2 ) =
Q'23 *R Gtot
VPL
Equation 19
( t'4 − t 3' ) = −RGtot * Ciss * ln(1 −
Q'34
VPL * Ciss
)
Time intervals of Equation 15, 17 and Equation 18, 19 have been calculated by assuming
that the MOSFET works at Tj=25 °C. If the MOSFET is supposed to work in a real
application, the Vth dependence ON temperature must be considered.
Having read the total gate charge Qg=Qth+Q12+Q23+Q34+Q4 (value at the VGM voltage level
which is usually 10 V) (the curve VGS vs. Qg is displayed in the MOSFET datasheet), the
total power loss needed to charge the gate is:
Equation 20
PGATE = Q g * VGM * fsw
So, by comparing the total gate charge of two MOSFETs, measured under the same test
conditions of ID, VDS, IG, it is possible to understand which of them requires the lowest
driving energy if the same VGM and fsw is considered.
Table 1 shows the total Qg values of four couples of MD V/MD II Power MOSFETs with
similar RDS(on). The Qg value of each device has been calculated from the VGS(t) curve of
each device (see Figure 11 and 12 for reference) and measured on bench at the same ID
and VDS levels at Tc=25 °C. The newest MD V guarantees a lower Qg value than its
equivalent MD II part, this leads to less effort in terms of driving energy requirements.
Table 1.
16/53
Experimentally measured Qg of four couples of MD V/MD II
Part number
RDS(on)max@10 V, 25°C
Qg@400 V, ID(A)
STP16N65M5
279 mΩ
28.4 nC@6 A
STP18NM60N
285 mΩ
31.2 nC@6 A
STP21N65M5
179 mΩ
40.4 nC@8 A
STP24NM60N
190 mΩ
42.3 nC@8 A
STP35N65M5
98 mΩ
77.4 nC@15 A
STB36NM60N
105 mΩ
80.1 nC@15 A
STB42N65M5
79 mΩ
96 nC@16 A
STW48NM60N
70 mΩ
122 nC@16 A
Doc ID 022380 Rev 1
AN3994
Gate charge curve impact on dynamic responses
Figure 11. Vg(t) curve measured on
STB42NM60N @16 A, 400 V,
IG=1.5 mA
Figure 12. Vg(t) curve measured on
STW48NM60N @16 A, 400 V,
IG=1.5 mA
In addition to the gate drive power losses, another contribution to the total switching loss is
due to the ID-VDS cross.
If the turn-on event is considered, the main contribution over the total power dissipation is
provided during phase “2” (current rise) and “3” (voltage lowering) of Figure 8, so the time
intervals mainly involved are (t1 to t2), when the gate voltage is between Vth and VPL, and
the time interval (t2 to t3) when the gate voltage is at the Miller value. Both of them have
been calculated by Equation 15 and 17. As for turn-off, the two time intervals mainly
involved in the event are (t'2 to t'3) when the voltage rises up to the clamp value, and (t'3 to
t'4) when the ID current falls (refer to Figure 10). Both of them have been theoretically
calculated by Equation 18 and 19.
The correspondence between the gate charge curve and the switching times involved in the
turn-on/off event is verified until no other external phenomenon arises to change the I-V
cross time duration (negligible layout parasitic inductances/capacitors, no/negligible peak
recovery current of the clamp diode).
Figure 13, 15 and Figure 14, 16 show the turn-on and the turn-off of the fourth compared
couple of Table 1, experimentally measured at the same current/voltage conditions of the
gate charge test in Figure 11 and 12 with an external RGon=47 Ω. The effect of these
parameters is shown in Table 2 which reports the theoretical turn-on and turn-off switching
times calculated by Equation 15, 17 and Equation 18, 19 compared to the turn-on and turnoff times experimentally measured on the same devices.
Table 2.
Experimentally and theoretically measured switching times and related static
parameters
Experimental Theoretical Experimental Theoretical
tsw(off)(tot)
tsw(on)(tot)
tsw(on)(tot)
tsw(off)(tot)
VPL
Q12
Q23
@16 A
Q’34
Q’23
STB42N65M5
5.6V
5.2nC
5nC
≈115ns
133ns
≈80ns
89ns
STW48NM60N
4.8V
4.5nC
4.5nC
≈105ns
114ns
≈90ns
96ns
Doc ID 022380 Rev 1
17/53
Gate charge curve impact on dynamic responses
AN3994
Referring to Equation 15, 17 and Equation 18, 19, it's clear that Q12+Q23 and the VPL are
the two main actors impacting on the turn-on switching times. Similarly, Q'23+Q'34 and VPL
mainly influence the turn-off switching times. It's important to note that a device with higher
VPL than another, also exhibits higher Vth at the same ID current.
As far as the MD V and MD II devices in Table 2 are concerned, the STB42N65M5 shows
slightly higher Q12 and Q23 charge portions than the STW48NM60N. If the other static
parameters are supposed to be the same for both devices, this should be enough to have
both turn-on times and turn-off times of the MD V device which are wider than MD II ones.
Additionally, the MD V part exhibits a higher VPL value than the MD II: this further worsens
both (t2 - t1) and (t3 - t2) contributions (see Equation 15 and 17) on the turn-on switching
times. On the other hand, a higher VPL helps to reduce turn-off switching times, as can be
verified by inspecting Equation 18 and 19. In the end, turn-on times of the MD V are wider
than the MD II device due to a higher gate charge portion and VPL, while the same static
parameters favor the MD V at turn-off.
The different impact of the VPL on turn-on and turn-off is also evident from Equation 7, 10,
11, as a higher plateau level of the MD V is directly linked to a lower IGon charging current
during the entire turn-on event; the same higher VPL of the MD V results in a higher IGoff
discharging current which helps to speed up the turn-off event.
The theoretical switching times calculated by Equation 15, 17 and Equation 18, 19 can also
be used to obtain a preliminary idea of what value of RGtot in the driving stage must be
adopted to guarantee a specific time interval for the turn-on or turn-off. It is anyway
important to remark that the ON and OFF energy losses depend on several factors, like:
18/53
1.
the circuit the MOSFET is working in (the test circuit considered in this work is a simple
single ended clamped inductive load circuit);
2.
the output capacitance of the MOSFET which exhibits a different voltage dependence if
different SJ MOSFET families are considered (this impacts on the voltage
raising/lowering of the MOSFET during the transients);
3.
the parasitic capacitances and inductors of the layout which can significantly impact on
the current and voltage slopes. All these effects sometimes modify the energy loss
wave, and this is the reason why there is not always an exact correspondence between
the switching time interval comparison and the energy value comparison in the same
match.
Doc ID 022380 Rev 1
AN3994
Gate charge curve impact on dynamic responses
Figure 13. Turn-on of STB42N65M5 @16 A,
400 V, 47 Ω
Figure 14. Turn-on of STW48NM60N @16 A,
400 V, 47 Ω
Figure 15. Turn-off of STB42N65M5 @16 A,
400 V, 47 Ω
Figure 16. Turn-off of STW48NM60N @16 A,
400 V, 47 Ω
So, VGS vs. Qg curve is very important for at least two reasons: it provides information on
the energy required to turn on/off the MOSFET and at the same time, it gives a rough idea of
the MOSFET dynamics.
Doc ID 022380 Rev 1
19/53
Latest ST MD II and MD V technology at a glance
5
AN3994
Latest ST MD II and MD V technology at a glance
With the MDmesh V family, STMicroelectronics reaches the lowest RDS(on) value per
package among its HV SJ MOSFET technology product range. For example, Figure 17
reports the lowest RDS(on)max achievable by the last two MD II and MD V product families.
Figure 17. Minimum RDS(on) per package achievable by MD II and MD V
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34$.-
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347.-.
349.-.
349 .- 347.-
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The MD V shows lower specific RDS(on) if compared to its predecessor. As a consequence
of this improvement, the RDS(on) per package is also lowered, therefore allowing the same
device to be housed in a smaller package, which was not possible before. Besides the
RDS(on), it is important to take into account the driving energy required to turn on/off the
device. In order to satisfy this requirement, the MD V guarantees lower total gate charge
than the MD II at the same ID,VDS and RDS(on) values (as shown in Table 1), allowing to
significantly reduce the driving losses and increase the total system efficiency. The reduced
RDS(on) values per package of MD V leads to a slight increase in thermal resistance, but this
is counterbalanced by an overall static and dynamic energy loss improvement if compared
to the previous MD II generation. Some exceptions on this last statement arise when small
devices of the two families are compared at very low current levels, as is shown in the next
section.
20/53
Doc ID 022380 Rev 1
AN3994
6
MD II and MD V: which is the lowest loss one?
MD II and MD V: which is the lowest loss one?
A dynamic on bench comparison has been carried out on four different MD V/MD II
MOSFET couples in order to provide a reliable idea of their dynamic performances. All tests
have been issued by the same simple clamped inductive load test circuit (refer to Figure 7)
where the effects of parasitic elements have been reduced in order to make the effective
MOSFET behavior more understandable.
A 600 V,10 A SiC diode has been used as the clamp diode. The matches obtained under
evaluation are those displayed in Table 1. The following graphs show the energy ON, the
energy OFF, the di/dt, the dv/dt both at turn-on and turn-off of each compared match for
different RG values, and two ID current levels.
6.1
STB42N65M5 vs. STW48NM60N
Figure 18. STB42N65M5 vs. STW48NM60N Eon @ 8 A/16 A, 400 V
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Figure 19. STB42N65M5 vs. STW48NM60N di/dt at turn-on @ 8 A/16 A, 400 V
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21/53
MD II and MD V: which is the lowest loss one?
AN3994
Figure 20. STB42N65M5 vs. STW48NM60N dv/dt at turn-on @ 8 A/16 A 400 V
DVDT AT TURN ON ! 6 4C
34".- VS 347.-.
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Figure 21. STB42N65M5 vs. STW48NM60N zoom of dv/dt at turn-on @ 8 A/16 A 400 V
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22/53
Doc ID 022380 Rev 1
5' 2KP
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AN3994
MD II and MD V: which is the lowest loss one?
Figure 22. STB42N65M5 vs. STW48NM60N Eoff @ 8 A/16 A, 400 V
%OFF ! 6 4C
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Figure 23. STB42N65M5 vs. STW48NM60N di/dt at turn-off @ 8 A/16 A, 400 V
DIDT AT TURN OFF ! 6 4C
34".- VS 347.-.
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23/53
MD II and MD V: which is the lowest loss one?
AN3994
Figure 24. STB42N65M5 vs. STW48NM60N dv/dt at turn-off @ 8 A/ 16 A, 400 V
DVDT AT TURN OFF ! 6 4C
34".- VS 347.-.
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STP35N65M5 vs. STB36NM60N
Figure 25. STP35N65M5 vs. STB36NM60N Eon @ 7.5 A/15 A, 400 V
%ON ! ! 6 4C #
340.- VS 34".-.
( —ON
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24/53
Doc ID 022380 Rev 1
5' 2KP
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AN3994
MD II and MD V: which is the lowest loss one?
Figure 26. STP35N65M5 vs. STB36NM60N di/dt at turn-on @ 7.5 A/15 A, 400 V
DIDT AT TURN ON ! ! 6 4C #
340.- VS 34".-.
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Figure 27. STP35N65M5 vs. STB36NM60N dv/dt at turn-on @ 7.5 A/15 A 400 V
DVDT AT TURN ON ! ! 6 4C #
340.- VS 34".-.
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25/53
MD II and MD V: which is the lowest loss one?
AN3994
Figure 28. STP35N65M5 vs. STB36NM60N Eoff @ 7.5 A/15 A, 400 V
%
OFF
! ! 6 4C #
340.- VS 34".-.
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Figure 29. STP35N65M5 vs. STB36NM60N di/dt at turn-off @ 7.5 A/15 A, 400 V
DIDT AT TURN OFF ! ! 6 4C #
340.- VS 34".-.
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26/53
Doc ID 022380 Rev 1
5' 2KP
!-V
AN3994
MD II and MD V: which is the lowest loss one?
Figure 30. STP35N65M5 vs. STB36NM60N dv/dt at turn-off @ 7.5 A/15 A, 400 V
67310$
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67310$
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STP21N65M5 vs. STP24NM60N
Figure 31. STP21N65M5 vs. STP24NM60N Eon @ 4 A/ 8 A, 400 V
67310$
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27/53
MD II and MD V: which is the lowest loss one?
AN3994
Figure 32. STP21N65M5 vs. STP24NM60N di/dt at turn-on @ 4 A/8 A, 400 V
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Figure 33. STP21N65M5 vs. STP24NM60N dv/dt at turn-on @ 4 A/8 A, 400 V
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28/53
Doc ID 022380 Rev 1
5' 2KP
!-V
AN3994
MD II and MD V: which is the lowest loss one?
Figure 34. STP21N65M5 vs. STP24NM60N Eoff @ 4 A/8 A, 400 V
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Figure 35. STP21N65M5 vs. STP24NM60N di/dt at turn-off @ 4 A/8 A, 400 V
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29/53
MD II and MD V: which is the lowest loss one?
AN3994
Figure 36. STP21N65M5 vs. STP24NM60N dv/dt at turn-off @ 4 A/8 A, 400 V
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STP16N65M5 vs. STP18NM60N
Figure 37. STP16N65M5 vs. STP18NM60N Eon @ 3 A/6 A, 400 V
67310$
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67310$
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%ON ! ! 6 4C #
340.- VS 340.-.
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5
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30/53
Doc ID 022380 Rev 1
!-V
AN3994
MD II and MD V: which is the lowest loss one?
Figure 38. STP16N65M5 vs. STP18NM60N di/dt at turn-on @ 3 A/ 6 A, 400 V
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Figure 39. STP16N65M5 vs. STP18NM60N dv/dt at turn-on @ 3 A/6 A, 400 V
DVDT AT TURN ON
! ! 6 4C #
340.- VS 340.-.
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31/53
MD II and MD V: which is the lowest loss one?
AN3994
Figure 40. STP16N65M5 vs. STP18NM60N Eoff @ 3 A/6 A, 400 V
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Figure 41. STP16N65M5 vs. STP18NM60N di/dt at turn-off @ 3 A/6 A, 400 V
DIDT AT TURN OFF ! ! 6 4
340.- VS 340.-.
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Doc ID 022380 Rev 1
5' 2KP
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AN3994
MD II and MD V: which is the lowest loss one?
Figure 42. STP16N65M5 vs. STP18NM60N dv/dt at turn-off @ 3 A/6 A, 400 V
DVDT AT TURN OFF ! ! 6 4 # #
340.- VS 340.-.
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Comments about energy ON comparison
Considerations about energy comparison between the MD V and the MD II depend on the
gate resistor selected by the user.
As for turn-on energy, the bigger sizes of the MD V list considered in this work
(STP42N65M5 and STP35N65M5) perform worse than their equivalent MD II parts in the
entire RG range at the two current levels selected for the tests. This is due to the negative
gate charge impact (the Q12+Q23 portion, as explained in Section 4) together with the
higher threshold and plateau value of these parts if compared to the MD II devices.
Smaller sizes show a slightly different dynamic behavior: MD V parts (STP21N65M5 and
STP16 N65M5) perform worse than their equivalent MD II parts at relative medium/high RG
values (i.e. RG>10 Ω for the STP21N65M5, and RG>22 Ω for the STP16N65M5). This
situation changes if low RG values are used. Under the latter driving condition, the MD V
performs better than the MD II but, it is not advised to adopt very low RG values in most
common situations due to the increased voltage/current slopes of these small devices and
the consequent increased risk of spurious oscillations.
Anyway, if an MD V part (belonging to the list in Table 1) is used in any circuit with a specific
RGon value, and it needs to be replaced with an equivalent MD II part by keeping the same
Eon energy, this can be easily obtained by increasing its RGon value according to the charts
showing the Eon comparison reported in this work. The same way of proceeding can be
adopted if an MD V device must be used instead of an MD II equivalent part.
6.6
Comments about energy OFF comparison
As for turn-off, all MD V devices show better performances than their equivalent MD II parts.
Some exceptions arise for the smaller sizes (STP21N65M5 and STP16N65M5) when
current levels are significantly lower than the nominal current (see Figure 34 and 40).
The slightly worse MD V energy at very low current levels is linked to the behavior of the
MOSFET intrinsic capacitances. Output capacitance is charged up to VCLAMP during
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MD II and MD V: which is the lowest loss one?
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turn-off and the energy stored during this event is added to the effective energy dissipated at
turn-on in the next cycle in hard switching conditions, according to Equation 21:
Equation 21
E off (diss) = E off (measured) − E(C o )
E on (diss) = E on (measured) + E(C 0 )
As the current becomes lower and lower, the effective energy dissipated by the MOSFET
decreases and the measured OFF energy is only the energy required by the output
capacitance to enable the turn-off. This is the reason why all Eoff curves exhibit a flat trend at
low current/low RGoff values. If the energy required by the MD V output capacitances is
higher than that of the MD II, this leads to a higher measured Eoff value for the MD V if
compared to the MD II at the same ID, VCLAMP values.
A specific test was performed on all MD V/MD II matches analyzed in this work to confirm
the different output capacitance behavior. As output capacitance of a MOSFET is voltage
dependant, a constant equivalent capacitance which stores the same energy of the output
switch capacitance in the entire (0 V to VCLAMP=0 V to 400 V) excursion has been
calculated. The MOSFET is really being turned off in an unclamped inductive load test
circuit and the total energy stored in the inductor is:
Equation 22
E(inductive) =
1
⊗ L * I2
2
This inductive energy is supposed to be applied to a constant capacitance which charges up
to VCLAMP:
Equation 23
1
2
⊗ C 0AV ⊗ V 2 CLAMP =
1
2
⊗ L ⊗ I2
Table 3 shows the CoAV measured on all MD V/MD II devices:
Table 3.
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CoAV experimentally measured on MD V/MD II devices
Part number
C0AV@400 V
STP16N65M5
67 pF
STP18NM60N
64 pF
STP21N65M5
79 pF
STP24NM60N
75 pF
STP35N65M5
131 pF
STB36NM60N
109 pF
STB42N65M5
155 pF
STW48NM60N
162 pF
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MD II and MD V: which is the lowest loss one?
Table 3 explains why the measured Eoff energies of MD V STP16N65M5, STP21N65M5 and
STP35N65M5 are slightly worse than the MD II at very low current values and low RGoff
values.
Anyway, the difference in terms of Eoff between the small sizes of MD V and MD II is so
small that the two families can be considered as having the same dynamic performances
under the above specified conditions of current and RG.
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7
MOSFET critical parameters in high switching
environments
7.1
Parasitic inductance influence on switching losses
When considering the Power MOSFET switching characteristics, the influence of parasitic
inductances must be carefully considered. Among the three main actors in a power circuit
(the gate loop inductance, the common source inductance, and the main switching loop
inductance) the common source inductance and the main switching loop inductance are the
most critical and their respective action can not always be identified. Anyway, in most
practical cases it is possible to understand what kind of parasitic inductance has the greater
contribution over the other one by directly inspecting the switching waveforms.
If MOSFET transient is considered, the instantaneous drain current ID(t) and the
instantaneous gate to source voltage VGS(t) satisfies Equation 24:
Equation 24
iD (t ) = g fs ⊗ (VGS (t ) − Vth )
The drain to source voltage VDS changes its value due to the voltage across the parasitic
inductances according to the formula:
Equation 25
VDS = VDD −
dID
⊗ (L s ⊕ L D )
dt
(See Figure 43.)
Gate to source voltage VGS(t) satisfies Equation 26:
Equation 26
VGM = R Gtot (Cgs
dVGS
dVGD
d(I + I )
) + v GS (t ) + L S D GS
− Cgd
dt
dt
dt
Figure 43. Equivalent capacitive model of a MOSFET with parasitic inductances at
turn-on
,$
6$$
$
2'
6'$
#'$
)$'
'
6'-
)$3
)$
6'3
#'3
6$3
#$3
)'3
3
,3
!-V
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MOSFET critical parameters in high switching environments
Both parasitic inductances (drain and common source) impact on the VGS(t) and IG(t)
waveforms, as the voltage across the Ls is directly subtracted (or added in the case of a
turn-off event) from the input VGM, while the voltage induced across the LD changes the
voltage value of the Cds capacitance.
The effect of both inductances on the VGS(t), ID(t) and VDS depends on the relative values of
LD and Ls, rather than RG and the internal MOSFET capacitances Cgd and Cgs.
Under high current levels and low Ls values, the MOSFET experiences high voltage
overshoot during turn-off. Additionally, the voltage across the LD during the positive di/dt at
turn-on is subtracted from the VDS voltage across the switch and this is evident as a
“missing step” in the voltage waveform.
Figure 44. Turn-on of STW77N65M5@400 V, 13 A, 25 °C
VDS“missing step” at turn-on
due to high parasitic L D
AM10807v1
Figure 44 shows the turn-on of the STW77N65M5 working in the STEVAL-ISF001V1 3 kW
PFC, where the parasitic source inductance has been dramatically cut thanks to the 4-pin
solution (explained in Section 7.2). Nevertheless, the parasitic drain component is still
present, causing the typical “missing step” in the voltage waveform.
On the contrary, as the Ls value becomes significant if compared to the LD value, the driving
loop circuit has a relevant impact on the switching behavior, slowing down the ID current.
This implies an energy loss which worsens both at turn-on and at turn-off.
In the following sections, the impact of common source inductance and the main switching
loop inductance is analyzed by making the hypothesis of neglecting one of the two
contributors.
7.2
Common source inductance
The source inductance plays the most important role in influencing the switching
performances of a Power MOSFET, especially when high current levels need to be
commutated.
When dealing with source inductance, it is necessary to split it between an internal
component (the source bond wire inside the MOSFET package) and external components
including the inductance wiring between the source pin and the common ground of the PCB.
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MOSFET critical parameters in high switching environments
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Since no optimization can be done over the internal component, particular care must be
taken in controlling and reducing the external source inductance as much as possible.
The source inductance is involved in two different phenomena during the switching
transient; the most visible one arises during phase “2” of turn-on and phase “3” of turn-off
(see Figure 8 and 10).
If the turn-on event is considered, phase “2” is the phase of drain current rising. The VGS
voltage is between the Vth and the plateau level VPL, as the Ciss capacitor is being charged
by the gate current Ig. Figure 45 shows the equivalent driving circuit referred to in this
specific phase:
Figure 45. Equivalent driving circuit of a MOSFET at turn-on with parasitic source
inductance
5 *727
*
9 /V
9 *0
6
/V
!-V
The high di/dt during turn-on (positive rate of ID) induces a voltage VLs across the source
inductor (positive value, as shown in Figure 45) whose value satisfies Equation 27:
Equation 27
VLs = L s
d(ID ⊕ IGS )
d(I )
≈ Ls D
dt
dt
This induced VLs causes a lack of gate current due to less available voltage across the total
gate resistor causing a dI/dt reduction and, as a negative consequence, a worsening I-V
cross.
The source inductance, on the other hand, acts as a negative feedback in the gate driving
loop, as the reduced dI/dt results in a smaller VLs, this reduced voltage across Ls leads to an
increase in dI/dt. A balance is therefore established thanks to the source inductor, between
the gate current and the drain current.
As far as the turn-off (phase “3”) is concerned, the Ls acts in a similar way by inducing a
voltage VLs over the source inductor which is negative if referred to Figure 45 as the drain
current is falling down. This voltage leads to a positive Ig which has the unavoidable effect of
slowing down the drain current.
As long as the VLs across the inductor is considerably less than the gate source voltage
value in the commutation time interval, the effect of Ls can be neglected.
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MOSFET critical parameters in high switching environments
On the contrary, when high drain currents/high ΔI/dt are involved, the induced voltage VLs
becomes large enough to significantly interfere with the gate bias.
A second order effect related to the source inductance is that RGtot, Ls, and Ciss (at turn-on)
are the RLC components of a series resonant circuit, as shown in Figure 46.
Figure 46. Simplified equivalent series resonant model of the driving circuit of a
MOSFET
2 'TOT
'
#
ISS
3
6'-
,S
!-V
As far as the resonance aspect is concerned, the phenomenon is due to the Ls inductor and
the MOSFET input capacitor energy exchange (if turn-off is considered, the capacitor
involved is the drain source Cds). This results in the output current (gate current IG) and
voltage oscillatory spikes which can lead to unwanted turn-on if the VGS voltage reaches the
threshold value.
The Q factor of the resonant circuit which is also related to the Ls value and is responsible of
the output signal time response, can be reduced by increasing the total gate resistor
components along the driving loop (which comprises the external RG, the MOSFET intrinsic
RG and the driver output impedance).
If especially small sizes are involved, a higher gate resistor causes under damped
oscillations in the gate drive voltage waveforms but results in turn-on/turn-off time widening.
On the other hand, if RG values need to be lowered to optimize the energy losses at turn-on
and turn-off, the user must accept the possibility of spurious gate driving waveforms.
7.3
Minimizing common source inductance: layout optimization
and Kelvin source connection on STW77N65M5
The negative impact on turn-on and turn-off energy losses, due to the source inductance,
can be minimized by taking particular care of the layout during the design phase: the gate
driving loop should be as short as possible to minimize the total parasitic loop inductance
and more precisely, the common source wiring between the commutation loop and the gate
loop should be as short as possible (ideally zero) to minimize the slowing action of the Ls on
the drain current. This could be accomplished by placing the driving stage GND directly
connected to the source pin of the switch or very close to it, as shown in Figure 47.
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MOSFET critical parameters in high switching environments
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Figure 47. Gate driving and main switching loops for a MOSFET in a BOOST-like
topology
#/--54!4)/. ,//0
,
$
$2
'!4% $2)6).' ,//0
!-V
A simple clamped inductive load circuit test was adopted to evaluate the differences
between two layout configurations and their respective effect on the switch performance. It's
important to remark that all layout options described in the following sections have been
implemented on the same test circuit.
All tests have been carried on the STW77N65M5, as the advantage offered by the layout
optimization and the 4-pin solution (which is described shortly) is as important as high
current levels are involved.
In the first layout configuration, the common source path between the main switching loop
and the driving loop is a few cm long, while in the second layout configuration, the common
source path has been shortened to the length of the source pin. In both cases, the drain
parasitic loop inductance has been neglected thanks to a very short distance between the
bus capacitors and the switch. The following curves show the Eon and the Eoff energies of
STW77N65M5 which were issued with the same RG, gate driving signal (0 V to 10 V), and
VDD=400 V conditions.
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MOSFET critical parameters in high switching environments
Figure 48. STW77 energy ON difference between the standard layout and the
optimized layout
3WITCHING ON
347.-
% ON —*
OPTIMIZED COMMON PATH
NOT OPTIMIZED COMMON PATH
6 6 6'3 6 2' OHM
$$
) !
!-V
$
Figure 49. STW77 energy OFF difference between the standard layout and the
optimized layout
6ZLWFKLQJRII
67:10
% OFF —*
RSWLPL]HGFRPPRQSDWK
QRWRSWLPL]HGFRPPRQSDWK
6 6 6'3 6 2' OHM
$$
) !
$
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!-V
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MOSFET critical parameters in high switching environments
Figure 50. STW77N65M5 Eoff @ 20 A, 2.2 Ω
with non-optimized common path
AN3994
Figure 51. STW77N65M5 Eoff @ 20 A, 2.2 Ω
with non-optimized common path
0OSITIVE )' CAUSED BY THE INDUCED
VOLTAGE OVER THE PARASITIC ,3 DURING
THE NEGATIVE DIDT 4HE EFFECT IS AN
UNDESIRED TURN ON AND THE %PGG
WORSENING
0
/&&
!-V
Figure 52. STW77N65M5 Eoff @ 20 A, 2.2 Ω with optimized common path
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MOSFET critical parameters in high switching environments
Figure 53. STW77N65M5 Eoff @ 40 A, 2.2 Ω
with non-optimized common path
Figure 54. STW77N65M5 Eoff @ 40 A, 2.2 Ω
with non-optimized common path
Figure 55. STW77N65M5 Eoff @ 40 A, 2.2 Ω, 400 V with optimized common path
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MOSFET critical parameters in high switching environments
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Figure 56. STW77N65M5 Eon@20 A, 2.2 Ω with Figure 57. STW77N65M5 Eon@20 A, 2.2 Ω
no n-optimized common path
with non-optimized common path
)(PO LACK DUE TO THE INDUCED
VOLTAGE OVER THE PARASITIC
, 3 DURING THE POSITIVE DIDT
!-V
Figure 58. STW77N65M5 Eon@20 A, 2.2 Ω
with optimized common path
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Figure 59. STW77N65M5 Eon@20 A, 2.2 Ω
with optimized common path
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MOSFET critical parameters in high switching environments
Figure 60. STW77N65M5 Eon@40 A, 2.2 Ω with Figure 61. STW77N65M5 Eon@40 A, 2.2 Ω with
non-optimized common path
non-optimized common path
Figure 62. STW77N65M5 Eon@40 A, 2.2 Ω
with optimized common path
Figure 63. STW77N65M5 Eon@40 A, 2.2 Ω
with optimized common path
The impact of the parasitic inductance becomes heavier as the current increases, as clearly
shown by the trend of Eon and Eoff in Figure 50 and 63.
The turn-on is impacted more by the parasitic Ls rather than the Eoff, as the di/dt starts at
the very beginning of the turn-on phase, just after the VGS has reached the threshold. In this
situation the dI/dt and the VGS are severely slowed down and the plateau region is greatly
widened even if low RG values are used. So, as evident from Figure 60, the main
contribution over the IV cross is provided by the di/dt portion.
As for turn-off, the first part of the IV cross during the plateau region is not affected by the Ls,
and can be sped up by adopting a proper RG value. Additionally, the voltage across the
switch rises in the last portion of the plateau region, due to the particular output capacitance
dependence with voltage; so, this first contribution on the total energy OFF is negligible and
independent of Ls. As voltage across the switch reaches the clamp value, the ID drops down:
the Ls acts during this phase, but its impact is not heavy, as clear from the waveforms in
Figure 54.
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MOSFET critical parameters in high switching environments
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Figure 64. Schematic of 4-pin solution
DRAIN
PIN GATE
PIN DRIVER SOURCE
PIN POWER SOURCE
PIN !-V
The best way to minimize the inductance influence is to adopt the Kelvin source connection
(see Figure 64); this solution dramatically cuts the common path between the drain current
and the gate current as the Kelvin pin is directly referenced to the driving stage GND. The
result is that the energy losses are reduced and the rate of drain current during transients is
sped up. Figure 65 and 66, showing the differences in terms of energy ON and energy OFF
between a standard 3-pin with an optimized layout and the 4-pin, refer to the same PCB
circuit of the previous sets of experimental waveforms of Figure 48 and 49: this leads to the
obvious conclusion that the 4-pin solution allows the user to speed up the SJ MOSFET with
excellent results, not reachable by the 3-pin solution even if optimized in terms of layout
configuration.
Figure 65. STW77N65M5 energy ON difference between the optimized layout (3-pin)
and 4-pin solution
3WITCHING ON
347.-
% ON —*
SLQ
SLQRSWLPL]HGOD\RXW
6 6 6'3 6 2' OHM
$$
) !
$
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AN3994
MOSFET critical parameters in high switching environments
Figure 66. STW77N65M5 energy ON difference between the optimized layout (3-pin)
and 4-pin solution
3WITCHING OFF
347.-
SLQ
SLQRSWLPL]HGOD\RXW
6 6 6'3 6 2' OHM
% ON —*
$$
) !
$
!-V
Figure 67. STW77N65M5 energy OFF difference between the optimized layout (3-pin)
and 4-pin solution
)
'OFF
0/&&
)$
6$3
!-V
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MOSFET critical parameters in high switching environments
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Figure 68. STW77N65M5 Eoff@20 A, 2.2 Ω, 400 V 4-pin solution
Figure 69. STW77N65M5 Eon@20 A, 2.2 Ω
4-pin solution
Figure 70. STW77N65M5 Eon @20 A, 2.2 Ω
4-pin solution
) '/.
)$
6$3
!-V
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MOSFET critical parameters in high switching environments
Figure 71. STW77N65M5 Eon@40 A, 2.2 Ω
4-pin solution
7.4
Figure 72. STW77N65M5 Eon@40 A, 2.2 Ω
4-pin solution
Minimizing common source inductance impact at turn-off:
negative VGMoff
Threshold voltage for the Power MOSFET has a negative temperature coefficient and this
aspect must be carefully considered especially at turn-off, when parasitic inductances
resonate with the output MOSFET capacitor and lead to oscillations in gate to source
voltage waveforms. If threshold voltage is lowered because of high operation temperature,
the risk of unwanted turn-on significantly increases.
In order to improve the MOSFET immunity against noise, a negative VGM during turn-off is
suggested.
The negative bias at turn-off also counterbalances the induced voltage VLs across the
common source inductance (which is negative if referred to Figure 73).
If the negative VGMoff is properly chosen to avoid any gate oxide damages, it contributes to
the reduction of the positive gate charge amount injected during the ID falling down and
consequently to the reduction of the negative Ls impact on energy losses.
Figure 73. Basic driving stage of a Power MOSFET at turn-off with negative VGM
2
'TOT
'
3
6
'-OFF
6
,S
,S
!-V
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Figure 74 shows the STW77N65M5 turn-off at the test conditions below:
●
VDS=400 V
●
ID=52 A
●
VGMoff=0 V
●
RGoff=4.7 Ω
Figure 74. STW77N65M5 Eoff@52 A, 4.7 Ω, 400 V, VGMoff=-5 V
) '/&&
6'3
6$3
)$
!-V
Figure 75 shows the STW77N65M5 turn-off when the negative bias voltage is adopted
under the same test conditions and the same layout configuration:
●
VDS=400 V
●
ID=52 A
●
VGMoff=-5 V
●
RGoff=4.7 Ω
Figure 75. STW77N65M5 Eoff@52 A, 4.7 Ω, 400 V, VGMoff=-5 V
By comparing the two turn-off waveforms, it's clear that negative bias contributes to the
speeding-up of the drain current falling down and to drastically reduce the energy losses at
turn-off.
In this specific test, the energy OFF with negative VGM is about half of the standard zero
gate bias.
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7.5
MOSFET critical parameters in high switching environments
Switching loop inductance
The main switching loop inductance comprises several components along the power circuit,
including the internal inductances of the MOSFET and the diode packages, rather than the
PCB interconnections. The voltage across Ls during turn-off transient (phase of the negative
di/dt) results in high voltage VDS overshoot which can exceed the bus voltage and lead to
MOSFET failure. Additionally, the drain inductance resonates with the MOSFET or diode
capacitance, causing severe ringing over the voltage and current waveforms.
The LD impact on the turn-on waveform has been analyzed in Section 7.1.
It's not easy to control the parasitic component of the switching loop as it is commonly wider
than the other paths. Anyway, it is best to take care of it during the design phase in order to
further improve the MOSFET dynamic performances.
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Revision history
8
AN3994
Revision history
Table 4.
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Document revision history
Date
Revision
02-Dec-2011
1
Changes
Initial release.
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