Features Description The FAN3268 dual 2 A gate driver is optimized to drive a high-side P-channel MOSFET and a low-side Nchannel MOSFET in motor control applications operating from a voltage rail up to 18 V. The driver has TTL input thresholds and provides buffer and level translation functions from logic inputs. Internal circuitry provides an under-voltage lockout function that prevents the output switching devices from operating if the VDD supply voltage is below the operating level. Internal 100 kΩ resistors bias the non-inverting output low and the inverting output to VDD to keep the external MOSFETs off during startup intervals when logic control signals may not be present. 4.5 V to 18 V Operating Range Drives High-Side PMOS and Low-Side NMOS in Motor Control or Buck Step-Down Applications Inverting Channel B Biases High-Side PMOS Device Off (with internal 100 kΩ Resistor) when VDD is below UVLO Threshold TTL Input Thresholds 2.4 A Sink / 1.6 A Source at VOUT=6 V Internal Resistors Turn Driver Off If No Inputs MillerDrive™ Technology 8-Lead SOIC Package Rated from –40°C to +125°C Ambient Automotive Qualified to AEC-Q100 (F085 Version) Applications Motor Control with PMOS / NMOS Half-Bridge Configuration Buck Converters with High-Side PMOS Device; 100% Duty Cycle Operation Possible Logic-Controlled Load Circuits with High-Side PMOS Switch Automotive-Qualified Systems (F085 version) The FAN3268 driver incorporates MillerDrive™ architecture for the final output stage. This bipolarMOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability. The FAN3268 has two independent enable pins that default to on if not connected. If the enable pin for noninverting channel A is pulled low, OUTA is forced low; if the enable pin for inverting channel B is pulled low, OUTB is forced high. If an input is left unconnected, internal resistors bias the inputs such that the external MOSFETs are off. Related Resources AN-6069 — Application Review and Comparative Evaluation of Low-Side Gate Drivers +VRAIL (4.5−18V) FAN3268 Controller 1 ENA A 2 3 4 ENB GND 7 VDD B 8 MOTOR 6 5 CBYP Figure 1. Typical Motor Drive Application © 2009 Semiconductor Components Industries, LLC. September-2017, Rev. 2 Publication Order Number: FAN3268/D FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver FAN3268 2 A Low-Voltage PMOS-NMOS Bridge Driver Part Number Logic FAN3268TMX FAN3268TMX-F085 (1) Input Threshold Packing Method Non-Inverting Channel and Inverting Channel + Dual Enables TTL 2,500 Units on Tape & Reel Non-Inverting Channel and Inverting Channel + Dual Enables TTL 2,500 Units on Tape & Reel 1. Qualified to AEC-Q100 Package Outline ENA 1 8 ENB INA 2 7 OUTA GND 3 6 VDD INB 4 5 OUTB Figure 2. Pin Configuration (Top View) Thermal Characteristics (2) Package 8-Pin Small Outline Integrated Circuit (SOIC) ΘJL ΘJT ΘJA ΨJB ΨJT 40 31 89 43 3 (3) (4) (5) (6) (7) Units °C/W Notes: 2. 3. 4. 5. 6. 7. Estimates derived from thermal simulation; actual values depend on the application. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 5. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. Psi_JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 5. www.onsemi.com 2 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Ordering Information Pin# Name 1 ENA Enable Input for Channel A. Pull pin low to inhibit driver A. ENA has TTL thresholds. 8 ENB Enable Input for Channel B. Pull pin low to inhibit driver B. ENB has TTL thresholds. 3 GND Ground. Common ground reference for input and output circuits. 2 INA Input to Channel A. 4 INB Input to Channel B. 7 OUTA Gate Drive Output A: Held low unless required input(s) are present and VDD is above the UVLO threshold. OUTB Gate Drive Output B (inverted from the input): Held high unless required input is present and VDD is above UVLO threshold. 5 6 VDD Description Supply Voltage. Provides power to the IC. Output Logic FAN3268 (Channel A) ENA 0 0 1 (8) 1 (8) INA 0 (8) FAN3268 (Channel B) OUTA ENB 0 0 1 0 (8) 0 1 (8) 1 1 1 (8) 0 0 Note: 8. Default input signal if no external connection is made. www.onsemi.com 3 INB 0 (8) OUTB 1 1 1 (8) 1 1 0 0 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Pin Definitions VDD VDD 100kΩ 100kΩ ENA 1 INA 8 ENB 7 OUTA 6 VDD 5 OUTB 2 100kΩ 100kΩ GND 3 UVLO VDD_OK 100kΩ INB 4 100kΩ Figure 3. Block Diagram www.onsemi.com 4 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Block Diagram Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.3 20.0 V VDD VDD to GND VEN ENA, ENB to GND GND - 0.3 VDD + 0.3 V VIN INA, INB to GND GND - 0.3 VDD + 0.3 V OUTA, OUTB to GND GND - 0.3 VDD + 0.3 V VOUT TL Lead Soldering Temperature (10 Seconds) TJ Junction Temperature TSTG Storage Temperature Symbol Parameter +260 ºC -55 +150 ºC -65 +150 ºC Min. Max. Unit 4.5 18.0 V VDD Supply Voltage Range VEN Enable Voltage (ENA, ENB) 0 VDD V VIN Input Voltage (INA, INB) 0 VDD V TA Operating Ambient Temperature -40 +125 ºC www.onsemi.com 5 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Absolute Maximum Ratings Unless otherwise noted, VDD=12 V and TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit SUPPLY VDD Operating Range 4.5 IDD Supply Current Inputs / EN Not Connected 18.0 V 0.75 1.20 mA FAN3268T UVLO VON Device Turn-On Voltage INA=ENA=VDD, INB=ENB=0 V 3.5 3.9 4.3 V VOFF Device Turn-Off Voltage INA=ENA=VDD, INB=ENB=0 V 3.3 3.7 4.1 V FAN3268TMX_F085 UVLO (Automotive-Qualified Versions) VON VOFF INPUT Device Turn-On Voltage (12) INA=ENA=VDD, INB=ENB=0 V 3.3 3.9 4.5 V Device Turn-Off Voltage (12) INA=ENA=VDD, INB=ENB=0 V 3.1 3.7 4.3 V 0.8 1.2 (9) FAN3268T VIL INx Logic Low Threshold VIH INx Logic High Threshold VHYS Logic Hysteresis Voltage V 1.6 2.0 V 0.2 0.4 0.8 V 0.8 1.2 FAN3268TMX_F085 (Automotive-Qualified Versions) VIL VIH VHYS INx Logic Low Threshold (12) INx Logic High Threshold Logic Hysteresis Voltage (12) (12) 0.1 V 1.6 2.0 V 0.4 0.8 V Continued on the following page… www.onsemi.com 6 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Electrical Characteristics Unless otherwise noted, VDD=12 V and TJ=-40°C to +125°C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit ENABLE VENL Enable Logic Low Threshold EN from 5 V to 0 V VENH Enable Logic High Threshold EN from 0 V to 5 V VHYS Logic Hysteresis Voltage RPU 0.8 1.6 (10) Enable Pull-up Resistance 1.2 V 2.0 V 0.4 V 100 kΩ Out at VDD/2, CLOAD=0.1 µF, f=1 kHz 2.4 A Out at VDD/2, CLOAD=0.1 µF, f=1 kHz -1.6 A CLOAD=0.1 µF, f=1 kHz 3 A (10) OUTPUT ISINK Out Current, Mid-Voltage, Sinking ISOURCE Out Current, Mid-Voltage, (10) Sourcing IPK_SINK Out Current, Peak, Sinking IPK_SOURCE (10) Out Current, Peak, Sourcing tRISE Output Rise Time tFALL Output Fall Time (10) (11) (11) (10) CLOAD=0.1 µF, f=1 kHz -3 CLOAD=1000 pF 12 22 ns A CLOAD=1000 pF 9 17 ns FAN3268T tD1 tD2 Propagation Delay (11) 0 - 5 VIN, 1 V/ns Slew Rate 7 14 25 ns Propagation Delay (11) 0 - 5 VIN, 1 V/ns Slew Rate 10 19 34 ns 0 - 5 VIN, 1 V/ns Slew Rate 7 14 32 ns 0 - 5 VIN, 1 V/ns Slew Rate 8 19 34 ns VOH=VDD–VOUT, IOUT=–1 mA 15 40 mV IOUT=1 mA 10 25 mV FAN3268TMX_F085 (Automotive-Qualified Versions) tD1 tD2 VOH VOL Propagation Delay (11)(12) Propagation Delay (11)(12) High Level Output Voltage Low Level Output Voltage (12) (12) Notes: 9. EN inputs have TTL thresholds; refer to the ENABLE section. 10. Not tested in production. 11. See the Timing Diagrams of Figure 4 and Figure 5. 12. Apply only to Automotive Version(FAN3268TMX_F085) Timing Diagrams 90% 90% Output Output 10% 10% Input V INH or V INL Enable Input V INH or V Enable INL tD1 tD2 tD2 tRISE tD1 tFALL tFALL Figure 4. Non-Inverting Figure 5. Inverting www.onsemi.com 7 tRISE FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Electrical Characteristics (Continued) Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted. Figure 6. IDD (Static) vs. Supply Voltage (13) Figure 7. IDD (No-Load) vs. Frequency Figure 8. IDD (1 nF Load) vs. Frequency Figure 9. IDD (Static) vs. Temperature Figure 10. Input Thresholds vs. Supply Voltage (13) Figure 11. Input Thresholds vs. Temperature www.onsemi.com 8 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted. Figure 12. UVLO Threshold vs. Temperature Figure 13. Propagation Delays vs. Supply Voltage Figure 14. Propagation Delays vs. Supply Voltage Figure 15. Propagation Delays vs. Temperature Figure 16. Propagation Delays vs. Temperature www.onsemi.com 9 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted. Figure 17. Fall Time vs. Supply Voltage Figure 18. Rise Time vs. Supply Voltage Figure 19. Rise and Fall Times vs. Temperature Figure 20. Rise/Fall Waveforms with 1 nF Load www.onsemi.com 10 Figure 21. Rise/Fall Waveforms with 10 nF Load FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Typical Performance Characteristics Typical characteristics are provided at TA=25°C and VDD=12 V unless otherwise noted. Figure 22. Quasi-Static Source Current with VDD=12 V Figure 23. Quasi-Static Sink Current with VDD=12 V Figure 24. Quasi-Static Source Current with VDD=8 V Figure 25. Quasi-Static Sink Current with VDD=8 V Note: 13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high, static IDD increases by the current flowing through the corresponding pull-up/down resistor shown in the block diagram in Figure 3. Test Circuit VDD 120µF Al. El. 4.7µF ceramic Current Probe LECROY AP015 IN 1kHz IOUT 1µF ceramic VOUT CLOAD 0.1µF Figure 26. Quasi-Static IOUT / VOUT Test Circuit www.onsemi.com 11 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Typical Performance Characteristics Input Thresholds VDD The FAN3268 driver has TTL input thresholds and provides buffer and level translation functions from logic inputs. The input thresholds meet industry-standard TTL-logic thresholds, independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2 V is considered logic high. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6 V/µs or faster, so a rise time from 0 to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. Input stage VOUT Figure 27. MillerDrive™ Output Architecture Static Supply Current In the IDD (static) typical performance characteristics (see Figure 6), the curve is produced with all inputs / enables floating (OUT is low) and indicates the lowest static IDD current for the tested configuration. For other states, additional current flows through the 100 kΩ resistors on the inputs and outputs shown in the block diagram (see Figure 3). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. MillerDrive™ Gate Drive Technology FAN3268 gate drivers incorporate the MillerDrive™ architecture shown in Figure 1. For the output stage, a combination of bipolar and MOS devices provide large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between one and two thirds VDD and the MOS devices pull the output to the high or low rail. The purpose of the MillerDrive™ architecture is to speed up switching by providing high current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. For applications with zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched on. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slower rise or fall time at the MOSFET gate is needed. Under-Voltage Lockout Internal circuitry provides an under-voltage lockout function that prevents the output switching devices from operating if the VDD supply voltage is below the operating level. When VDD is rising, but below the 3.9 V operational level, internal 100 kΩ resistors bias the noninverting output low and the inverting output to VDD to keep the external MOSFETs off during startup intervals when logic control signals may not be present. After the part is active, the supply voltage must drop 0.2 V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. VDD Bypass Capacitor Guidelines To enable this IC to turn a device on quickly, a local highfrequency bypass capacitor CBYP with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 µF to 47 µF commonly found on driver and controller bias circuits. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply to ≤5%. This is often achieved with a value≥20 times the equivalent load capacitance CEQV, defined here as QGATE/VDD. Ceramic capacitors of 0.1 µF to 1 µF or larger are common choices, as are dielectrics, such as X5R and X7R, with good temperature characteristics and high pulse current capability. If circuit noise affects normal operation, the value of CBYP may be increased to 50-100 times the CEQV or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10 nF mounted closest to the VDD and GND pins to carry the higher frequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the CBYP would be twice as large as when a single channel is switching. www.onsemi.com 12 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Applications Information Operational Waveforms The FAN3268 gate driver incorporates fast-reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 2 A to facilitate voltage transition times from under 10ns to over 150 ns. The following layout and connection guidelines are strongly recommended: Figure 28 shows startup waveforms for non-inverting channel A. At power-up, the driver output for channel A remains low until the VDD voltage reaches the UVLO turnon threshold, then OUTA operates in-phase with INA. VDD UVLO Turn-on threshold Keep high-current output and power ground paths separate from logic and enable input signals and signal ground paths. This is especially critical when dealing with TTL-level logic thresholds at driver inputs and enable pins. INA Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed switching, while reducing the loop area that can radiate EMI to the driver inputs and surrounding circuitry. OUTA If the inputs to a channel are not externally connected, the internal 100 kΩ resistors indicated on block diagrams command a low output (channel A) or a high output (channel B). In noisy environments, it may be necessary to tie inputs or enables of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output retriggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. For best results, make connections to all pins as short and direct as possible. The turn-on and turn-off current paths should be minimized. Figure 28. Non-Inverting Startup Waveforms Figure 29 illustrates startup waveforms for inverting channel B. At power-up, the driver output for channel B is tied to VDD through an internal 100 kΩ resistor until the VDD voltage reaches the UVLO turn-on threshold, then OUTB operates out of phase with INB. VDD UVLO Turn-on threshold INB OUTB Figure 29. Inverting Startup Waveforms www.onsemi.com 13 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Layout and Connection Guidelines Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL=PGATE + PDYNAMIC (1) Gate Driving Loss: The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at switching frequency, fSW , is determined by: PGATE=QG • VGS • fSW • n (2) where n is the number of driver channels in use (1 or 2). As an example of a power dissipation calculation, consider an application driving two MOSFETs with a gate charge of 60 nC with VGS=VDD=7 V. At a switching frequency of 500 kHz, the total power dissipation is: PGATE=60nC • 7V • 500kHz • 2=0.42W (5) PDYNAMIC=3mA • 7V • 2=0.042W (6) PTOTAL=0.46W (7) The SOIC-8 has a junction-to-board thermal characterization parameter of ψ JB=43°C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150°C; with 80% derating, TJ would be limited to 120°C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120°C: TB=TJ - PTOTAL • ψ JB (8) TB=120°C – 0.46W • 43°C/W=100°C (9) Dynamic Pre-drive / Shoot-through Current: A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors, can be obtained using the “IDD (No-Load) vs. Frequency” graphs in Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC=IDYNAMIC • VDD • n (3) Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming ψ JB was determined for a similar thermal design (heat sinking and air flow): TJ =PTOTAL • ψ JB + TB (4) where: TJ =driver junction temperature ψ JB =(psi) thermal characterization parameter relating temperature rise to total power dissipation TB =board temperature in location defined in Note 2 under Thermal Resistance table. www.onsemi.com 14 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Thermal Guidelines Part Number FAN3111C Related Products Type Gate (14) Drive (Sink/Src) Input Threshold Single 1 A +1.1 A / -0.9 A CMOS (15) Logic Package Single Channel of Dual-Input/Single-Output SOT23-5, MLP6 Single Non-Inverting Channel with External Reference SOT23-5, MLP6 FAN3111E Single 1 A +1.1 A / -0.9 A External FAN3100C Single 2 A +2.5 A / -1.8 A CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6 FAN3100T Single 2 A +2.5 A / -1.8 A TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6 FAN3226C Dual 2 A +2.4 A / -1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3226T Dual 2 A +2.4 A / -1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3227C Dual 2 A +2.4 A / -1.6 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3227T Dual 2 A +2.4 A / -1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3228C Dual 2 A +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 FAN3228T Dual 2 A +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 FAN3229C Dual 2 A +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 FAN3229T Dual 2 A +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 FAN3268T Dual 2 A +2.4 A / -1.6 A TTL Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables SOIC8 FAN3223C Dual 4 A +4.3 A / -2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3223T Dual 4 A +4.3 A / -2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224C Dual 4 A +4.3 A / -2.8 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3224T Dual 4 A +4.3 A / -2.8 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 FAN3225C Dual 4 A +4.3 A / -2.8 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 FAN3225T Dual 4 A +4.3 A / -2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 FAN3121C Single 9 A +9.7 A / -7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8 FAN3121T Single 9 A +9.7 A / -7.1 A TTL Single Inverting Channel + Enable SOIC8, MLP8 FAN3122T Single 9 A +9.7 A / -7.1 A CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8 FAN3122C Single 9 A +9.7 A / -7.1 A TTL Single Non-Inverting Channel + Enable SOIC8, MLP8 Notes: 14. Typical currents with OUT at 6 V and VDD=12 V. 15. Thresholds proportional to an externally supplied reference voltage. www.onsemi.com 15 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Table 1. 0.65 A 4.90±0.10 (0.635) 5 8 B 1.75 6.00±0.20 1 PIN ONE INDICATOR 5.60 3.90±0.10 4 1.27 1.27 0.25 C B A LAND PATTERN RECOMMENDATION SEE DETAIL A 0.175±0.75 0.22±0.30 C 1.75 MAX 0.10 0.42±0.09 OPTION A - BEVEL EDGE (0.86) x 45° R0.10 GAGE PLANE R0.10 OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED 8° 0° SEATING PLANE 0.65±0.25 (1.04) DETAIL A SCALE: 2:1 A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08Arev15 Figure 30. 8-Lead Small Outline Integrated Circuit (SOIC) www.onsemi.com 16 FAN3268 —2 A Low-Voltage PMOS-NMOS Bridge Driver Physical Dimensions ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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