TI1 OPA842 Wideband, low distortion, unity-gain stable, voltage-feedback operational amplifier Datasheet

OPA842
www.ti.com
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
Wideband, Low Distortion, Unity-Gain Stable, Voltage-Feedback
OPERATIONAL AMPLIFIER
Check for Samples: OPA842
FEATURES
DESCRIPTION
•
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The OPA842 provides a level of speed and dynamic
range previously unattainable in a monolithic op amp.
Using unity-gain stable, voltage-feedback architecture
with two internal gain stages, the OPA842 achieves
exceptionally low harmonic distortion over a wide
frequency range. The classic differential input
provides all the familiar benefits of precision op amps,
such as bias current cancellation and very low
inverting current noise compared with wideband
current
differential
gain/phase
performance,
low-voltage noise, and high output current drive make
the OPA842 ideal for most high dynamic range
applications.
1
2
UNITY-GAIN BANDWIDTH: 400MHz
GAIN-BANDWIDTH PRODUCT: 200MHz
LOW INPUT VOLTAGE NOISE: 2.6nV/√Hz
VERY LOW DISTORTION: –93dBc (5MHz)
HIGH OPEN-LOOP GAIN: 110dB
FAST 12-BIT SETTLING: 22ns (0.01%)
LOW DC VOLTAGE OFFSET: 300mV Typical
PROFESSIONAL LEVEL DIFF GAIN/PHASE
ERROR: 0.003%/0.008°
APPLICATIONS
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ADC/DAC BUFFER DRIVER
LOW DISTORTION IF AMPLIFIER
ACTIVE FILTER CONFIGURATION
LOW-NOISE DIFFERENTIAL RECEIVER
HIGH-RESOLUTION IMAGING
TEST INSTRUMENTATION
PROFESSIONAL AUDIO
OPA642 UPGRADE
Unity-gain stability makes the OPA842 particularly
suitable
for
low-gain
differential
amplifiers,
transimpedance amplifiers, gain of +2 video line
drivers, wideband integrators, and low-distortion
analog-to-digital converter (ADC) buffers. Where
higher gain or even lower harmonic distortion is
required, consider the OPA843—a higher-gain
bandwidth and lower-noise version of the OPA842.
OPA842 RELATED PRODUCTS
INPUT NOISE
GAIN-BANDWIDTH
VOLTAGE (nV/√Hz) PRODUCT (MHz)
SINGLES
OPA843
2.0
800
OPA846
1.1
2500
OPA847
0.8
3700
+5V
+5V
2kW
RS
0.1mF 24.9W
VIN
REFT
(+3V)
2kW
IN
OPA842
50W
100pF
ADS850
14-Bit
10MSPS
-5V
402W
2kW
IN
0.1mF
402W
2kW
(+2V)
REFB
(+1V)
VREF
SEL
AC-Coupled to 14-Bit ADS850 Interface
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2010, Texas Instruments Incorporated
OPA842
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR
OPA842
SO-8
D
-40°C to +85°C
OPA842
OPA842
SOT23-5
DBV
-40°C to +85°C
OAQI
(1)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
OPA842ID
Rails, 100
OPA842IDR
Tape and Reel, 2500
OPA842IDBVT
Tape and Reel, 250
OPA842IDBVR
Tape and Reel, 3000
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see
device product folder at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range, unless otherwise noted.
Power Supply
OPA842
UNIT
±6.5
VDC
Internal Power Dissipation
See Thermal Analysis
Differential Input Voltage
±1.2
Input Voltage Range
±VS
V
–65 to +125
°C
Storage Temperature Range (Tstg): D, DBV
Junction Temperature (TJ)
ESD Ratings
(1)
V
+175
°C
Human Body Model (HBM)
2000
V
Charge Device Model (CDM)
1500
V
Machine Model (MM)
200
V
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
D PACKAGE
SO-8
(TOP VIEW)
DRB PACKAGE
SOT23-5
(TOP VIEW)
NC
1
8
NC
Inverting Input
2
7
+VS
Noninverting Input
3
6
Output
-VS
4
5
NC
Output
-VS
Noninverting Input
1
5
+VS
4
Inverting Input
2
3
4
5
NC = No connection.
3
2
1
OAQI
Pin Orientation/Package Marking
2
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
www.ti.com
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS: VS = ±5V
Boldface limits are tested at +25°C. At TA = +25°C, VS = ±5V, RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted.
See Figure 37 for ac performance.
OPA842ID, IDBV
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
+25°C (2)
0°C to
+70°C (3)
UNIT
MIN/
MAX
TEST
LEVELS (1)
MHz
typ
C
100
MHz
min
B
29
MHz
min
B
14
14
MHz
min
B
135
135
MHz
min
B
TEST CONDITIONS
+25°C
G = +1, RF = 25Ω
350
G = +2
150
105
101
G = +5
45
30
29
G = +10
21
15
200
136
-40°C to
+85°C (3)
AC Performance (see Figure 37)
Closed-Loop Bandwidth (VO =
100mVPP)
Gain-Bandwidth Product
Bandwidth for 0.1dB Gain Flatness
Harmonic Distortion
xx x second-Harmonic
xx x third-Harmonic
Two-Tone, Third-Order Intercept
G = +2, RL = 100Ω, VO = 100mVPP
56
MHz
typ
C
G = +1, RL = 100Ω, RF = 25Ω
105
MHz
typ
C
G = +2, f = 5MHz, VO = 2VPP
RL = 100Ω
–80
–78
–77
–76
dBc
max
B
RL = 500Ω
–94
–92
–91
–90
dBc
max
B
RL = 100Ω
–97
–96
–95
–94
dBc
max
B
RL = 500Ω
–93
–91
–90
–90
dBc
max
B
G = +2, f = 10MHz
44
dBm
typ
C
Input Voltage Noise
f > 1MHz
2.6
2.8
3.0
3.1
nV/√Hz
max
B
Input Current Noise
f > 1MHz
2.7
2.8
2.9
3.0
pA/√Hz
max
B
Rise and Fall Time
0.2V Step
2.3
3.3
3.4
3.5
ns
max
B
Slew Rate
2V Step
400
300
250
225
V/ms
min
B
Settling Time to 0.01%
2V Step
22
ns
typ
C
Settling Time to 0.1%
2V Step
15
19.6
20.3
21.3
ns
max
B
Settling Time to 1.0%
2V Step
9
10.2
11.3
12.5
ns
max
B
Differential Gain
G = +2, NTSC, RL = 150Ω
0.003
%
typ
C
Differential Phase
G = +2, NTSC, RL = 150Ω
0.008
degrees
typ
C
DC PERFORMANCE (4)
Open-Loop Voltage Gain (AOL)
VO = 0V
110
100
96
92
dB
min
A
Input Offset Voltage
VCM = 0V
±0.30
±1.2
±1.4
±1.5
mV
max
A
Average Offset Voltage Drift
VCM = 0V
±4
±4
mV/°C
max
B
Input Bias Current
VCM = 0V
–36
–37
mA
max
A
Input Bias Current Drift
VCM = 0V
25
25
nA/°C
max
B
Input Offset Current
VCM = 0V
±1.15
±1.17
mA
max
A
Input Offset Current Drift
VCM = 0V
±2
±2
nA/°C
max
B
–20
±0.35
–35
±1.0
INPUT
Common-Mode Input Range (5)
(CMIR)
Common-Mode Rejection Ratio
(CMRR)
VCM = ±1V, Input-Referred
±3.2
±3.0
±2.9
±2.8
V
min
A
95
85
84
82
dB
min
A
Input Impedance
xx x Differential Mode
VCM = 0V
14 || 1
kΩ || pF
typ
C
xx x Common-Mode
VCM = 0V
3.1 || 1.2
MΩ || pF
typ
C
(1)
(2)
(3)
(4)
(5)
Test levels: (A) 100% tested at +25°C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
Junction temperature = ambient temperature for +25°C specifications.
Junction temperature = ambient at low temperature limits; junction temperature = ambient +23°C at high temperature limit for overtemperature min/max specifications.
Current is considered positive out-of-node. VCM is the input common-mode voltage.
Tested < 3dB below minimum specified CMRR at ±CMIR limits.
3
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5V (continued)
Boldface limits are tested at +25°C. At TA = +25°C, VS = ±5V, RF = 402Ω, RL = 100Ω, and G = +2, unless otherwise noted.
See Figure 37 for ac performance.
OPA842ID, IDBV
MIN/MAX OVER
TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
+25°C
+25°C (2)
0°C to
+70°C (3)
-40°C to
+85°C (3)
UNIT
MIN/
MAX
TEST
LEVELS (1)
OUTPUT
Output Voltage Swing
Current Output, Sourcing
Closed-Loop Output Impedance
RL > 1kΩ, Positive Output
3.2
3.0
±2.9
±2.8
V
min
A
RL > 1kΩ, Negative Output
–3.7
–3.5
–3.4
–3.3
V
min
A
RL = 100Ω, Positive Output
3.0
2.8
2.7
2.6
V
min
A
RL = 100Ω, Negative Output
–3.5
–3.3
–3.2
–3.1
V
min
A
VO = 0V
±100
±90
±85
±80
mA
min
A
G = +2, f = 1kHz
0.00038
Ω
typ
C
V
typ
C
V
min
A
V
typ
C
POWER SUPPLY
Specified Operating Voltage
±5
Maximum Operating Voltage
±6
Minimum Operating Voltage
±6
±6
±3.5
Maximum Quiescent Current
VS = ±5V
20.2
20.8
22.2
22.5
mA
max
A
Minimum Quiescent Current
VS = ±5V
20.2
19.6
19.1
18.3
mA
min
A
Power-Supply Rejection Ratio
(+PSRR, –PSRR)
|VS| = 4.5V to 5.5V, Input-Referred
100
90
88
85
dB
min
A
THERMAL CHARACTERISTICS
Specified Operating Range: D, DBV
–40 to +85
°C
typ
C
—
—
—
—
xx x D xxxx x SO-8
125
°C/W
typ
C
xx x DBV xxx SOT23
150
°C/W
typ
C
Thermal Resistance, qJA
Junction-to-Ambient
4
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
www.ti.com
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS: VS = ±5V
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
NONINVERTING SMALL−SIGNAL
FREQUENCY RESPONSE
3
G = +1
RF = 25W
0
Normalized Gain (3dB/div)
Normalized Gain (3dB/div)
3
INVERTING SMALL−SIGNAL
FREQUENCY RESPONSE
G = +2
-3
VO = 0.1VPP
G = +5
-6
G = +10
-9
-12
-15
0
G = -1
-3
G = -5
-9
-12
G = -10
-15
See Figure 38
See Figure 37
-18
-18
1
10
100
1
500
10
Frequency (MHz)
Figure 1.
Figure 2.
NONINVERTING LARGE−SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE−SIGNAL
FREQUENCY RESPONSE
6
Normalized Gain (3dB/div)
9
0.1VPP
0.5VPP
1.0VPP
VO = 2VPP
VO = 5VPP
-3
RL = 100W
G = -2V/V
RG = 200W
3
0
Gain (3dB/div)
RL = 100W
G = +2V/V
500
0.1VPP
1VPP
2VPP
6
3
0
100
Frequency (MHz)
9
5VPP
-3
-6
-9
-6
-12
-9
-15
See Figure 37
See Figure 38
-18
-12
1
10
100
1
500
10
Frequency (MHz)
100
Figure 3.
Figure 4.
NONINVERTING PULSE RESPONSE
INVERTING PULSE RESPONSE
0.8
0.4
0
0
Small Signal 100mV
Left Scale
-100
-200
-0.4
-0.8
-1.2
See Figure 37
Output Voltage (100mV/div)
Right Scale
100
Output Voltage (400mV/div)
G = +2
Large Signal 1V
1.2
200
0.8
Right Scale
100
0.4
0
0
Small Signal 100mV
Left Scale
-100
-200
-0.4
-0.8
-1.2
See Figure 38
Time (5ns/div)
Output Voltage (400mV/div)
G = -2
RG = 200W
1.2
200
500
Frequency (MHz)
Large Signal 1V
Output Voltage (100mV/div)
G = -2
VO = 0.1VPP
-6
Time (5ns/div)
Figure 5.
Figure 6.
5
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
5MHz HARMONIC DISTORTION
vs LOAD RESISTANCE
1MHz HARMONIC DISTORTION
vs LOAD RESISTANCE
-75
-85
VO = 2VPP
-80
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
VO = 2VPP
2nd Harmonic
-85
-90
-95
-90
-95
2nd Harmonic
-100
-105
3rd Harmonic
3rd Harmonic
See Figure 37
-100
100
150
200
250
300
350
400
450
See Figure 37
-110
500
100
150
200
Load Resistance (W)
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs OUTPUT VOLTAGE
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
-90
3rd Harmonic
-100
500
1
10
RL = 200W
f = 5MHZ
-85
-90
2nd Harmonic
-95
3rd Harmonic
-100
-105
See Figure 37
See Figure 37
-110
-110
20
0.1
1
Frequency (MHz)
10
Output Voltage Swing (VPP)
Figure 9.
Figure 10.
HARMONIC DISTORTION
vs NONINVERTING GAIN
HARMONIC DISTORTION
vs INVERTING GAIN
-70
VO = 2VPP
RL = 200W
f = 5MHz
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
450
-80
2nd Harmonic
-80
400
Figure 8.
-80
-70
350
Figure 7.
VO = 2VPP
RL = 200W
G = +2
0.5
300
Load Resistance (W)
-60
-70
250
2nd Harmonic
-90
3rd Harmonic
-100
VO = 2VPP
RL = 200W
f = 5MHz
RF = 402W
-80
2nd Harmonic
-90
-100
3rd Harmonic
See Figure 37
-110
See Figure 38
-110
1
10
1
Noninverting Gain (V/V)
10
Inverting Gain |V/V|
Figure 11.
Figure 12.
6
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
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SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
TWO−TONE, THIRD−ORDER
INTERMODULATION INTERCEPT
INPUT VOLTAGE AND CURRENT NOISE
100
50
PI
50W
Intercept Point (+dBm)
Voltage Noise (nV/ÖHz)
Current Noise (pA/ÖHz)
45
10
Current Noise
2.7pA/ÖHz
Voltage Noise
10
2
10
3
10
402W
402W
35
30
25
4
10
5
10
6
10
20
7
5
10
15
20
25
35
40
45
50
Figure 14.
RECOMMENDED RS vs CAPACITIVE LOAD
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Normalized Gain to Capacitive Load (dB)
100
10
1
10
30
Frequency (MHz)
Figure 13.
RS (W)
PO
40
Frequency (Hz)
1
OPA842
50W
2.6nV/ÖHz
1
50W
100
3
0
C = 10pF
-3
C = 47pF
C = 22pF
-6
C = 100pF
-9
VI
RS
VO
50W OPA842
-12
CL
1kW
402W
-15
402W
-18
10
1k
100
500
Frequency (MHz)
Capacitive Load (pF)
Figure 15.
Figure 16.
GAIN = +1 FLATNESS
PULSE RESPONSE G = +1
0.2
Large Signal 1V
Output Voltage (100mV/div)
Gain (dB)
0
VO = 0.1VPP
RF = 25W
RL = 100W
-0.1
-0.2
-0.3
-0.4
200
1.2
0.8
Right Scale
100
0.4
0
-100
0
Small Signal
Left Scale
-200
-0.4
-0.8
Output Voltage (400mV/div)
0.1
-1.2
-0.5
-0.6
0
25
50
75
100
125
150
175
200
Time (2ns/div)
Frequency (MHz)
Figure 17.
Figure 18.
7
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Product Folder Link(s): OPA842
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www.ti.com
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
COMMON−MODE REJECTION RATIO AND
POWER−SUPPLY REJECTION RATIO vs FREQUENCY
OPEN−LOOP GAIN AND PHASE
120
120
0
-PSRR
100
Open-Loop Gain (dB)
CMRR
80
+PSRR
60
40
80
-60
ÐAOL
60
20
2
3
10
4
10
10
5
6
10
8
7
10
-120
20
-150
0
-180
10
10
10
1
10
2
10
3
10
5
10
6
10
7
10
8
10
Figure 20.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS
CLOSED-LOOP OUTPUT IMPEDANCE
vs FREQUENCY
Output Impedance (W)
RL = 100
0
1W Internal
Power Limit
RL = 25
RL = 50
-1
-2
1W Internal
Power Limit
0.1
0.01
0.001
0.0001
-3
-4
-0.15
-210
1
2
1
9
10
3
VO (V)
10
Figure 19.
4
0.00001
-0.10
-0.05
0
0.05
0.10
0.15
10
2
10
3
IO (mA)
NONINVERTING OVERDRIVE RECOVERY
3
6
10
7
10
8
2
1
4
Input
Right Scale
6
Output Voltage (2V/div)
RL = 100W
G=2
See Figure 37
4
RL = 100W
G=2
See Figure 38
3
2
2
1
0
0
-2
-1
0
0
-2
-1
-4
-2
-6
-3
-6
-4
-8
-8
10
-4
Time (40ns/div)
-2
Output
Left Scale
Input Voltage (1V/div)
Output
Left Scale
5
8
Input Voltage (1V/div)
4
10
INVERTING OVERDRIVE RECOVERY
4
6
4
Figure 22.
8
Input
Right Scale
10
Frequency (Hz)
Figure 21.
Output Voltage (2V/div)
4
Frequency (Hz)
Frequency (Hz)
2
-90
40
-20
1
10
-30
Open-Loop Phase (°)
CMRR (dB)
PSRR (dB)
100
0
20log (AOL)
-3
-4
Time (40ns/div)
Figure 23.
Figure 24.
8
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
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SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
SETTLING TIME
VIDEO DIFFERENTIAL GAIN/DIFFERENTIAL PHASE
0.250
G=2
Differential Gain (%)
0.150
0.100
0.050
0
-0.050
-0.100
0.006
0.06
DG Negative Video
DP Negative
Video
0.04
0.004
DP Positive Video
0.02
0.002
Differential Phase (°)
VO = 2V Step
RL = 100W
G=2
0.200
Percent of Final Value (%)
0.08
0.008
DG Positive Video
-0.150
-0.200
See Figure 37
-0.250
0
5
10
15
20
25
30
35
40
45
0
0
1
50
2
3
Figure 25.
Figure 26.
TYPICAL DC DRIFT OVER TEMPERATURE
0
-12.5
-0.5
Input Bias Current
Right Scale
-25
125
-1
-50
-25
0
25
50
75
100
Output Current (5mA/div)
Input Offset Voltage
Left Scale
115
22
Supply Current
20
110
Right Scale
18
105
16
100
Sink/Source Output Current
95
14
Left Scale
90
12
85
10
8
125
80
-50
Ambient Temperature (°C)
0
-25
25
75
50
Supply Current (2mA/div)
12.5
0.5
24
120
Input Bias and Offset Current (A)
Input Offset Voltage (mV)
SUPPLY AND OUTPUT CURRENT vs TEMPERATURE
25
100x (Input Offset Current)
Right Scale
0
5
Video Loads
Time (ns)
1
4
100
Ambient Temperature (°C)
Figure 27.
Figure 28.
COMMON-MODE INPUT RANGE AND OUTPUT SWING
vs SUPPLY VOLTAGE
COMMON-MODE AND DIFFERENTIAL INPUT IMPEDANCE
6
10
Input Impedance (W)
Voltage Range (V)
4
2
0
±Voltage Output
±Voltage Input
-2
-4
10
10
10
10
-6
3
4
5
6
10
7
Common-Mode Impedance
6
5
4
Differential Impedance
3
2
10
2
Supply Voltage (V)
10
3
10
4
10
5
10
6
10
7
10
8
10
9
Frequency (Hz)
Figure 29.
Figure 30.
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TYPICAL CHARACTERISTICS: VS = ±5V (continued)
At TA = +25°C, G = +2, RF = 402Ω, and RL = 100Ω, unless otherwise noted.
DIFFERENTIAL SMALL-SIGNAL
FREQUENCY RESPONSE
DIFFERENTIAL PERFORMANCE TEST CIRCUIT
3
+5V
GD = 1
OPA842
GD =
Normalized Gain (dB)
0
402W
RG
-5V
VI
RG
402W
RG
402W
RL
VO
GD = 2
-3
GD = 5
-6
GD = 10
-9
-12
-15
+5V
-18
1
10
100
500
Frequency (MHz)
OPA842
-5V
Figure 31.
Figure 32.
DIFFERENTIAL LARGE-SIGNAL FREQUENCY RESPONSE
DIFFERENTIAL DISTORTION vs LOAD RESISTANCE
9
-85
6
Harmonic Distortion (dBc)
Gain (dB)
0.2VPP
1VPP
2VPP
GD = 2
RL = 400W
3
0
-3
5VPP
-6
8VPP
-9
G=2
f = 5MHz
VO = 4VPP
-90
-95
2nd Harmonic
-100
-105
3rd Harmonic
-12
-110
10
100
50
500
100
150
Figure 33.
350
400
450
500
DIFFERENTIAL DISTORTION vs OUTPUT VOLTAGE
RL = 400W
GD = +2
f = 5MHz
-85
Harmonic Distortion (dBc)
Harmonic Distortion (dBc)
300
-80
RL = 400W
VO = 4VPP
GD = +2
-70
250
Figure 34.
DIFFERENTIAL DISTORTION vs FREQUENCY
-60
200
Load Resistance (W)
Frequency (MHz)
-80
-90
2nd Harmonic
-100
-90
-95
2nd Harmonic
-100
-105
3rd Harmonic
-110
3rd Harmonic
-110
-115
1
10
100
1
Frequency (MHz)
10
Output Voltage Swing (VPP)
Figure 35.
Figure 36.
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APPLICATION INFORMATION
WIDEBAND CURRENT FEEDBACK
OPERATION
WIDEBAND INVERTING OPERATION
The OPA842 combination of speed and dynamic
range is easily achieved in a wide variety of
application circuits, providing that simple principles of
good design practice are observed. For example,
good power-supply decoupling, as shown in
Figure 37, is essential to achieve the lowest possible
harmonic distortion and smooth frequency response.
Operating the OPA842 as an inverting amplifier has
several benefits and is particularly useful when a
matched 50Ω source and input impedance is
required. Figure 38 shows the inverting gain of –2
circuit used as the basis of the inverting mode Typical
Characteristics.
+5V
Proper printed circuit board (PCB) layout and careful
component selection will maximize the performance
of the OPA842 in all applications, as discussed in the
following sections of this data sheet.
Figure 37 shows the gain of +2 configuration used as
the basis for most of the Typical Characteristics. Most
of the curves were characterized using signal sources
with 50Ω driving impedance and with measurement
equipment presenting 50Ω load impedance. In
Figure 37, the 50Ω shunt resistor at the VI terminal
matches the source impedance of the test generator
while the 50Ω series resistor at the VO terminal
provides a matching resistor for the measurement
equipment load. Generally, data sheet specifications
refer to the voltage swing at the output pin (VO in
Figure 37). The 100Ω load, combined with the 804Ω
total feedback network load, presents the OPA842
with an effective load of approximately 90Ω in
Figure 37.
+5V
+VS
0.1mF
+
2.2mF
50W Source
VIN
50W
RS 50W Load
50W
VO
OPA842
RF
402W
RG
402W
0.1mF
+
2.2mF
-VS
-5V
Figure 37. Gain of +2, High-Frequency
Application and Characterization Circuit
0.1mF
RT
147W
0.1mF
50W Source
OPA842
RG
200W
VO
+
2.2mF
50W
50W Load
RF
402W
VI
RM
66.5W
0.1mF
+
2.2mF
-5V
Figure 38. Inverting G = –2 Specifications and
Test Circuit
In the inverting case, just the feedback resistor
appears as part of the total output load in parallel with
the actual load. For the 100Ω load used in the Typical
Characteristics, this gives a total load of 80Ω in this
inverting configuration. The gain resistor is set to get
the desired gain (in this case, 200Ω for a gain of –2)
while an additional input matching resistor (RM) can
be used to set the total input impedance equal to the
source if desired. In this case, RM = 66.5Ω in parallel
with the 200Ω gain setting resistor gives a matched
input impedance of 50Ω. This matching is only
needed when the input needs to be matched to a
source impedance, as in the characterization testing
done using the circuit of Figure 38. The OPA842
offers extremely good dc accuracy as well as low
noise and distortion. To take full advantage of that dc
precision, the total dc impedance looking out of each
of the input nodes must be matched to get bias
current cancellation. For the circuit of Figure 38, this
requires the 147Ω resistor shown to ground on the
noninverting input. The calculation for this resistor
includes a dc-coupled 50Ω source impedance along
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with RG and RM. Although this resistor will provide
cancellation for the bias current, it must be
well-decoupled (0.1mF in Figure 38) to filter the noise
contribution of the resistor and the input current
noise.
As the required RG resistor approaches 50Ω at higher
gains, the bandwidth for the circuit in Figure 38 will
far exceed the bandwidth at that same gain
magnitude for the noninverting circuit of Figure 37.
This occurs due to the lower noise gain for the circuit
of Figure 38 when the 50Ω source impedance is
included in the analysis. For instance, at a signal gain
of –8 (RG = 50Ω, RM = open, RF = 402Ω) the noise
gain for the circuit of Figure 38 will be 1 + 402Ω/(50Ω
+ 50Ω) = 5 due to the addition of the 50Ω source in
the noise gain equation. This gives considerable
higher bandwidth than the noninverting gain of +8.
Using the 200MHz gain bandwidth product for the
OPA842, an inverting gain of –8 from a 50Ω source
to a 50Ω RG will give approximately 40MHz
bandwidth, whereas the noninverting gain of +8 will
give 25MHz.
BUFFERING HIGH-PERFORMANCE ADCs
To achieve full performance from a high dynamic
range ADC, considerable care must be exercised in
the design of the input amplifier interface circuit. The
example circuit on the front page shows a typical
ac-coupled interface to a very high dynamic range
converter. This ac-coupled example allows the
OPA842 to be operated using a signal range that
swings symmetrically around ground (0V). The 2VPP
swing is then level-shifted through the blocking
capacitor to a midscale reference level, which is
created by a well-decoupled resistive divider off the
converter internal reference voltages. To have a
negligible effect on the rated spurious-free dynamic
range (SFDR) of the converter, the amplifier SFDR
should be at least 10dB greater than the converter.
The OPA842 has no effect on the rated distortion of
the ADS850, given its 82dB SFDR at 2VPP, 5MHz.
The greater than 92dB SFDR for the OPA842 in this
configuration will not degrade the converter.
Successful application of the OPA842 for ADC driving
requires careful selection of the series resistor at the
amplifier output, along with the additional shunt
capacitor at the ADC input. To some extent, selection
of this RC network will be determined empirically for
each model of the converter. Many high-performance
CMOS ADCs, like the ADS850, perform better with
the shunt capacitor at the input pin. This capacitor
provides low source impedance for the transient
currents produced by the sampling process. Improved
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SFDR is often obtained by adding this external
capacitor, whose value is often recommended in this
converter data sheet. The external capacitor, in
combination with the built-in capacitance of the ADC
input, presents a significant capacitive load to the
OPA842. Without a series isolation resistor, an
undesirable peaking or loss of stability in the amplifier
may result.
Since the dc bias current of the CMOS ADC input is
negligible, the resistor has no effect on overall gain or
offset accuracy. Refer to the Typical Characteristic
graph, RS vs Capacitive Load (Figure 15) to obtain a
good starting value for the series resistor. This will
ensure flat frequency response to the ADC input.
Increasing the external capacitor value will allow the
series resistor to be reduced. Intentionally
bandlimiting using this RC network can also be used
to limit noise at the converter input.
VIDEO LINE DRIVING
Most video distribution systems are designed with
75Ω series resistors to drive a matched 75Ω cable. In
order to deliver a net gain of 1 to the 75Ω matched
load, the amplifier is typically set up for a voltage gain
of +2, compensating for the 6dB attenuation of the
voltage divider formed by the series and shunt 75Ω
resistors at either end of the cable.
The circuit of Figure 37 applies to this requirement if
all references to 50Ω resistors are replaced by 75Ω
values. Often, the amplifier gain is further increased
to 2.2, which recovers the additional dc loss of a
typical long cable run. This change would require the
gain resistor (RG) in Figure 37 to be reduced from
402Ω to 335Ω. In either case, both the gain flatness
and the differential gain/phase performance of the
OPA842 will provide exceptional results in video
distribution applications. Differential gain and phase
measure the change in overall small-signal gain and
phase for the color sub-carrier frequency (3.58MHz in
NTSC systems) versus changes in the large-signal
output level (which represents luminance information
in a composite video signal). The OPA842, with the
typical 150Ω load of a single matched video cable,
shows less than 0.01%/0.01° differential gain/phase
errors over the standard luminance range for a
positive video (negative sync) signal. Similar
performance would be observed for negative video
signals.
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SINGLE OP AMP DIFFERENTIAL AMPLIFIER
The voltage-feedback architecture of the OPA842,
with its high Common-Mode Rejection Ratio (CMRR),
will provide exceptional performance in differential
amplifier configurations. Figure 39 shows a typical
configuration. The starting point for this design is the
selection of the RF value in the range of 200Ω to 2kΩ.
Lower values reduce the required RG, increasing the
load on the V2 source and on the OPA842 output.
Higher values increase output noise and exacerbate
the effects of parasitic board and device
capacitances. Following the selection of RF, RG must
be set to achieve the desired inverting gain for V2.
Remember that the bandwidth will be set
approximately by the Gain Bandwidth Product (GBP)
divided by the noise gain (1 + RF/RG). For accurate
differential operation (that is, good CMRR), the ratio
R2/R1 must be set equal to RF/RG.
THREE OP AMP DIFFERENCING
(Instrumentation Topology)
The primary drawback of the single op amp
differential amplifier is its relatively low input
impedance. Where high impedance is required at the
differential input, a standard instrumentation amplifier
(INA) topology may be built using the OPA842 as the
differencing stage. Figure 40 shows an example of
this, in which the two input amplifiers are packaged
together as a dual voltage-feedback op amp, the
OPA2822. This approach saves board space, cost,
and power compared to using two additional OPA842
devices, and still achieves very good noise and
distortion performance due to the moderate loading
on the input amplifiers.
+5V
V1
OPA2822
+5V
Power-supply decoupling not shown.
R1
V1
50W
R2
OPA842
RG
RF
V2
RF
(V - V2)
RG 1
VO =
when
RF1
500W
Power-supply decoupling not shown.
500W
+5V
OPA842
RG
500W
RF1
500W
R2 RF
=
R1 RG
500W
VO
-5V
500W
500W
OPA2822
-5V
V2
Figure 39. High-Speed, Single Differential
Amplifier
Usually, it is best to set the absolute values of R2 and
R1 equal to RF and RG, respectively; this equalizes
the divider resistances and cancels the effect of input
bias currents. However, it is sometimes useful to
scale the values of R2 and R1 in order to adjust the
loading on the driving source V1. In most cases, the
achievable low-frequency CMRR will be limited by the
accuracy of the resistor values. The 85dB CMRR of
the OPA842 itself will not determine the overall circuit
CMRR unless the resistor ratios are matched to
better than 0.003%. If it is necessary to trim the
CMRR, then R2 is the suggested adjustment point.
-5V
Figure 40. Wideband Three-Op Amp Differencing
Amplifier
In this circuit, the common-mode gain to the output is
always 1, due to the four matched 500Ω resistors,
whereas the differential gain is set by (1 + 2RF1/RG),
which is equal to 2 using the values in Figure 40. The
differential to single-ended conversion is still
performed by the OPA842 output stage. The
high-impedance inputs allow the V1 and V2 sources to
be terminated or impedance matched as required. If
the V1 and V2 inputs are already truly differential,
such as the output from a signal transformer, then a
single matching termination resistor may be used
between them. Remember, however, that a defined
dc signal path must always exist for the V1 and V2
inputs; for the transformer case, a center-tapped
secondary connected to ground would provide an
optimum dc operating point.
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DAC TRANSIMPEDANCE AMPLIFIER
High-frequency digital-to-analog converters (DACs)
require a low-distortion output amplifier to retain the
SFDR performance into real-world loads. A
single-ended output drive implementation is shown in
Figure 41. In this circuit, only one side of the
complementary output drive signal is used. The
diagram shows the signal output current connected
into the virtual ground-summing junction of the
OPA842, which is set up as a transimpedance stage
or I-V converter. The unused current output of the
DAC is connected to ground. If the DAC requires its
outputs terminated to a compliance voltage other than
ground for operation, then the appropriate voltage
level may be applied to the noninverting input of the
OPA842.
OPA842
High-Speed
DAC
f-3dB =
corner
frequency
GBP
2pRFCD
(f–3dB)
of
(2)
ACTIVE FILTERS
Most active filter topologies will have exceptional
performance using the broad bandwidth and
unity-gain stability of the OPA842. Topologies
employing capacitive feedback require a unity-gain
stable, voltage-feedback op amp. Sallen-Key filters
simply use the op amp as a noninverting gain stage
inside an RC network. Either current- or
voltage-feedback op amps may be used in
Sallen-Key implementations.
See Figure 42 for an example Sallen-Key low-pass
filter, in which the OPA842 is set up to deliver a
low-frequency gain of +2. The filter component values
have been selected to achieve a maximally flat
Butterworth response with a 5MHz, –3dB bandwidth.
The resistor values have been slightly adjusted to
compensate for the effects of the 150MHz bandwidth
provided by the OPA842 in this configuration. This
filter may be combined with the ADC driver
suggestions to provide moderate (two-pole) Nyquist
filtering, limiting noise, and out-of-band harmonics
into the input of an ADC. This filter will deliver the
exceptionally low harmonic distortion required by high
SFDR ADCs such as the ADS850 (14-bit, 10MSPS,
82dB SFDR).
VO = IDRF
RF
CF
ID
which will give a
approximately:
CD
GBP ? Gain Bandwidth
Product (Hz) for the OPA842
ID
C1
150pF
Figure 41. Wideband, Low-Distortion DAC
Transimpedance Amplifier
+5V
R1
124W
The dc gain for this circuit is equal to RF. At high
frequencies, the DAC output capacitance will produce
a zero in the noise gain for the OPA842 that may
cause peaking in the closed-loop frequency
response. CF is added across RF to compensate for
this noise-gain peaking. To achieve a flat
transimpedance frequency response, this pole in the
feedback network should be set to:
1
=
2pRFCF
GBP
4pRFCD
(1)
R2
505W
V1
C2
100pF
VO
OPA842
RF
402W
Power-supply
decoupling not shown.
-5V
RG
402W
Figure 42. 5MHz Butterworth Low-Pass Active
Filter
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MACROMODELS AND APPLICATIONS SUPPORT
DESIGN-IN TOOLS
DEMONSTRATION FIXTURES
Two printed circuit boards (PCBs) are available to
assist in the initial evaluation of circuit performance
using the OPA842 in its two package options. Both of
these are offered free of charge as unpopulated
PCBs, delivered with a user's guide. The summary
information for these fixtures is shown in Table 1.
Table 1. Demonstration Fixtures by Package
PRODUCT
PACKAGE
ORDERING
NUMBER
LITERATURE
NUMBER
OPA842ID
SO-8
DEM-OPA-SO-1A
SBOU009
OPA842IDBV
SOT23-5
DEM-OPA-SOT-1A
SBOU010
The demonstration fixtures can be requested at the
Texas Instruments web site (www.ti.com) through the
OPA842 product folder.
Computer simulation of circuit performance using
SPICE is often a quick way to analyze the
performance of the OPA842 and its circuit designs.
This is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can play a major role on circuit performance. A
SPICE model for the OPA842 is available through the
TI web page (www.ti.com). The applications group is
also available for design assistance. These models
predict typical small-signal ac, transient steps, dc
performance, and noise under a wide variety of
operating conditions. The models include the noise
terms found in the Electrical Characteristics of the
data sheet. These models do not attempt to
distinguish between the package types in the
small-signal ac performance.
OPERATING SUGGESTIONS
OPTIMIZING RESISTOR VALUES
Since the OPA842 is a unity-gain stable,
voltage-feedback op amp, a wide range of resistor
values may be used for the feedback and gain setting
resistors. The primary limits on these values are set
by dynamic range (noise and distortion) and parasitic
capacitance considerations. For a noninverting
unity-gain follower application, the feedback
connection should be made with a 25Ω resistor—not
a direct short. This will isolate the inverting input
capacitance from the output pin and improve the
frequency response flatness. Usually, the feedback
resistor value should be between 200Ω and 1kΩ.
Below 200Ω, the feedback network will present
additional output loading which can degrade the
harmonic distortion performance of the OPA842.
Above 1kΩ, the typical parasitic capacitance
(approximately 0.2pF) across the feedback resistor
may cause unintentional band limiting in the amplifier
response.
A good rule of thumb is to target the parallel
combination of RF and RG (see Figure 37) to be less
than about 200Ω. The combined impedance RF || RG
interacts with the inverting input capacitance, placing
an additional pole in the feedback network, and thus
a zero in the forward response. Assuming a 2pF total
parasitic on the inverting node, holding RF || RG <
200Ω will keep this pole above 400MHz. By itself, this
constraint implies that the feedback resistor RF can
increase to several kΩ at high gains. This is
acceptable as long as the pole formed by RF and any
parasitic capacitance appearing in parallel is kept out
of the frequency range of interest.
In the inverting configuration, an additional design
consideration must be noted. RG becomes the input
resistor and therefore the load impedance to the
driving source. If impedance matching is desired, RG
may be set equal to the required termination value.
However, at low inverting gains, the resultant
feedback resistor value can present a significant load
to the amplifier output. For example, an inverting gain
of 2 with a 50Ω input matching resistor (equal to RG)
would require a 100Ω feedback resistor, which would
contribute to output loading in parallel with the
external load. In such a case, it would be preferable
to increase both the RF and RG values, and then
achieve the input matching impedance with a third
resistor to ground (see Figure 38). The total input
impedance becomes the parallel combination of RG
and the additional shunt resistor.
BANDWIDTH vs GAIN
Voltage-feedback op amps exhibit decreasing
closed-loop bandwidth as the signal gain is
increased. In theory, this relationship is described by
the GBP shown in the specifications. Ideally, dividing
GBP by the noninverting signal gain (also called the
Noise Gain, or NG) will predict the closed-loop
bandwidth. In practice, this only holds true when the
phase margin approaches 90 degrees, as it does in
high-gain configurations. At low signal gains, most
amplifiers will exhibit a more complex response with
lower phase margin. The OPA842 is optimized to
give a maximally flat second-order Butterworth
response in a gain of 2. In this configuration, the
OPA842 has approximately 60 degrees of phase
margin and will show a typical –3dB bandwidth of
150MHz. When the phase margin is 60 degrees, the
closed-loop bandwidth is approximately √2 greater
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than the value predicted by dividing GBP by the noise
gain. Increasing the gain will cause the phase margin
to approach 90 degrees and the bandwidth to more
closely approach the predicted value of (GBP/NG). At
a gain of +10, the 21MHz bandwidth shown in the
Electrical Characteristics agrees with that predicted
using the simple formula and the typical GBP of
200MHz.
OUTPUT DRIVE CAPABILITY
The OPA842 has been optimized to drive the
demanding load of a doubly-terminated transmission
line. When a 50Ω line is driven, a series 50Ω into the
cable and a terminating 50Ω load at the end of the
cable are used. Under these conditions, the cable
impedance will appear resistive over a wide
frequency range, and the total effective load on the
OPA842 is 100Ω in parallel with the resistance of the
feedback network. The Electrical Characteristics
show a +2.8V/–3.3V swing into this load—which will
then be reduced to a +1.4V/–1.65V swing at the
termination resistor. The ±90mA output drive over
temperature provides adequate current drive margin
for this load. Higher voltage swings (and lower
distortion) are achievable when driving higher
impedance loads.
A single video load typically appears as a 150Ω load
(using standard 75Ω cables) to the driving amplifier.
The OPA842 provides adequate voltage and current
drive to support up to three parallel video loads (50Ω
total load) for an NTSC signal. With only one load,
the OPA842 achieves an exceptionally low
0.003%/0.008° dG/dP error.
DRIVING CAPACITIVE LOADS
One of the most demanding, and yet very common,
load conditions for an op amp is capacitive loading. A
high-speed, high open-loop gain amplifier like the
OPA842 can be very susceptible to decreased
stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. In
simple terms, the capacitive load reacts with the
open-loop output resistance of the amplifier to
introduce an additional pole into the loop and thereby
decrease the phase margin. This issue has become a
popular topic of application notes and articles, and
several external solutions to this problem have been
suggested. When the primary considerations are
frequency response flatness, pulse response fidelity,
and/or distortion, the simplest and most effective
solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor
between the amplifier output and the capacitive load.
This does not eliminate the pole from the loop
response, but rather shifts it and adds a zero at a
higher frequency. The additional zero acts to cancel
the phase lag from the capacitive load pole, thus
increasing the phase margin and improving stability.
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The Typical Characteristics show the recommended
RS vs Capacitive Load (see Figure 15) and the
resulting frequency response at the load. The
criterion for setting the recommended resistor is
maximum bandwidth, flat frequency response at the
load. Since there is now a passive low-pass filter
between the output pin and the load capacitance, the
response at the output pin itself is typically somewhat
peaked, and becomes flat after the roll-off action of
the RC network. This is not a concern in most
applications, but can cause clipping if the desired
signal swing at the load is very close to the amplifier’s
swing limit. Such clipping would be most likely to
occur in pulse response applications where the
frequency peaking is manifested as an overshoot in
the step response.
Parasitic capacitive loads greater than 2pF can begin
to degrade the performance of the OPA842. Long
PCB traces, unmatched cables, and connections to
multiple devices can easily cause this value to be
exceeded. Always consider this effect carefully, and
add the recommended series resistor as close as
possible to the OPA842 output pin (see Board Layout
section).
DISTORTION PERFORMANCE
The OPA842 is capable of delivering an exceptionally
low distortion signal at high frequencies and low
gains. The distortion plots in the Typical
Characteristics show the typical distortion under a
wide variety of conditions. Most of these plots are
limited to 100dB dynamic range. The OPA842
distortion does not rise above –100dBc until either
the signal level exceeds 0.5V and/or the fundamental
frequency exceeds 500kHz. Distortion in the audio
band is ≤ –120dBc. Generally, until the fundamental
signal reaches very high frequencies or powers, the
second-harmonic will dominate the distortion with a
negligible third-harmonic component. Focusing then
on the second-harmonic, increasing the load
impedance improves distortion directly. Remember
that the total load includes the feedback network— in
the noninverting configuration this is the sum of
RF + RG, whereas in the inverting configuration this is
just RF (see Figure 37). Increasing the output voltage
swing increases harmonic distortion directly.
Increasing the signal gain will also increase the
second-harmonic distortion. Again, a 6dB increase in
gain will increase the second- and third-harmonics by
6dB even with a constant output power and
frequency. Finally, the distortion increases as the
fundamental frequency increases due to the roll off in
the loop gain with frequency. Conversely, the
distortion will improve going to lower frequencies
down to the dominant open-loop pole at
16
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
www.ti.com
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
approximately 600Hz. Starting from the –100dBc
second-harmonic for 2VPP into 200Ω, G = +2
distortion at 1MHz (from the Typical Characteristics),
the second-harmonic distortion at 20kHz should be
approximately:
ENI
EO
OPA842
RS
IBN
–100dB – 20log (1MHz/20kHz) = –134dBc
The OPA842 has an extremely low third-order
harmonic distortion. This also gives an exceptionally
good two-tone, third-order intermodulation intercept,
as shown in the Typical Characteristics. This intercept
curve is defined at the 50Ω load when driven through
a 50Ω-matching resistor to allow direct comparisons
to RF MMIC devices. This network attenuates the
voltage swing from the output pin to the load by 6dB.
If the OPA842 drives directly into the input of a
high-impedance device, such as an ADC, this 6dB
attenuation is not taken. Under these conditions, the
intercept will increase by a minimum 6dBm. The
intercept is used to predict the intermodulation
spurious for two closely spaced frequencies. If the
two test frequencies, f1 and f2, are specified in terms
of average and delta frequency, fO = (f1 + f2)/2 and
Δf = |f2 – f1|/2, the two thirdorder, close-in spurious
tones will appear at fO ± (3 • Δf). The difference
between the two equal test-tone power levels and
these intermodulation spurious power levels is given
by 2 • (IM3 – PO), where IM3 is the intercept taken
from the Typical Characteristic curve and PO is the
power level in dBm at the 50Ω load for one of the two
closely-spaced test frequencies. For instance, at
10MHz, the OPA842 at a gain of +2 has an intercept
of 45dBm at a matched 50Ω load. If the full envelope
of the two frequencies needs to be 2VPP, this requires
each tone to be 4dBm. The third-order
intermodulation spurious tones will then be
2 • (45 – 4) = 82dBc below the test-tone power level
(–80dBm). If this same 2VPP two-tone envelope were
delivered directly into the input of an ADC without the
matching loss or loading of the 50Ω network, the
intercept would increase to at least 51dBm. With the
same signal and gain conditions driving directly into a
light load, the spurious tones will then be at least
2 • (51 – 4) = 94dBc below the 1VPP test-tone signal
levels.
NOISE PERFORMANCE
The OPA842 complements its ultralow harmonic
distortion with low input noise terms. Both the
input-referred
voltage
noise
and
the
two
input-referred current noise terms combine to give a
low output noise under a wide variety of operating
conditions. Figure 43 shows the op amp noise
analysis model with all the noise terms included. In
this model, all the noise terms are taken to be noise
voltage or current density terms in either nV/√Hz or
pA/√Hz.
ERS
RF
Ö4kTRS
IBI
RG
4kT
RG
Ö4kTRF
4kT = 16E - 20J
at 290 kelvins
Figure 43. Op Amp Noise Analysis Model
The total output spot noise voltage is computed as
the square root of the squared contributing terms to
the output noise voltage. This computation is adding
all the contributing noise powers at the output by
superposition, then taking the square root to get back
to a spot noise voltage. Equation 3 shows the general
form for this output noise voltage using the terms
presented in Figure 43.
EO =
(E
2
NI
(
+ (IBNRS)2 + 4kTRS NG2 + (IBIRF)2 + 4kTRFNG
(3)
Dividing this expression by the noise gain [NG = (1 +
RF/RG)] will give the equivalent input-referred spot
noise voltage at the noninverting input, as shown in
Equation 4.
EN =
2
NI
E
I R
+ (IBNRS) + 4kTRS + BI F
NG
2
(
2
( + 4kTR
NG
F
(4)
Evaluating these two equations for the OPA842
circuit presented in Figure 37 will give a total output
spot noise voltage of 6.6nV/√Hz and an equivalent
input spot noise voltage of 3.3nV/√Hz.
Narrow band communications systems are more
commonly concerned with the noise figure for the
amplifier. The total input referred voltage noise
expression (see Equation 4), may be used to
calculate the noise figure. Equation 5 shows this
noise figure expression using the NG of Equation 4
for the noninverting configuration where the input
terminating resistor, RT, has been set to match the
source impedance, RS (see Figure 37).
kT = 4E - 21J at 290 kelvins
EN 2
NF = 10log 2 +
kTRS
(5)
Evaluating Equation 5 for the circuit of Figure 37
gives a noise figure = 17.6dB.
17
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
DC OFFSET CONTROL
The OPA842 can provide excellent dc signal
accuracy due to its high open-loop gain, high
common-mode rejection, high power-supply rejection,
and low input offset voltage and bias current offset
errors. To take full advantage of this low input offset
voltage, careful attention to input bias current
cancellation is also required. The high-speed input
stage for the OPA842 has a relatively high input bias
current (20mA typ into the pins) but with a very close
match between the two input currents—typically
0.35mA input offset current. The total output offset
voltage may be considerably reduced by matching
the source impedances looking out of the two inputs.
For example, one way to add bias current
cancellation to the circuit of Figure 37 would be to
insert a 175Ω series resistor into the noninverting
input from the 50Ω terminating resistor. When the
50Ω source resistor is dc-coupled, this will increase
the source impedance for the noninverting input bias
current to 200Ω. Since this is now equal to the
impedance looking out of the inverting input
(RF || RG), the circuit will cancel the gains for the bias
currents to the output leaving only the offset current
times the feedback resistor as a residual dc error
term at the output. Using a 402Ω feedback resistor,
this output error will now be less than
1mA • 402Ω = 0.4mV at +25°C.
THERMAL ANALYSIS
The OPA842 will not require heat sinking or airflow in
most applications. Maximum desired junction
temperature would set the maximum allowed internal
power dissipation as described below. In no case
should the maximum junction temperature be allowed
to exceed +175°C.
Operating junction temperature (TJ) is given by
TA + PD • qJA. The total internal power dissipation (PD)
is the sum of quiescent power (PDQ) and additional
power dissipated in the output stage (PDL) to deliver
load power. Quiescent power is simply the specified
no-load supply current times the total supply voltage
across the part. PDL will depend on the required
output signal and load but would, for a grounded
resistive load, be at a maximum when the output is
fixed at a voltage equal to 1/2 of either supply voltage
(for equal bipolar supplies). Under this worst-case
condition, PDL = VS2/(4 • RL), where RL includes
feedback network loading.
Note that it is the power in the output stage and not in
the load that determines internal power dissipation.
As a worst-case example, compute the maximum TJ
using an OPA842IDBV (SOT23-5 package) in the
circuit of Figure 37 operating at the maximum
specified ambient temperature of +85°C.
www.ti.com
PD = 10V • 22.5mA + 52/[4 • (100Ω || 800Ω)] =
291mW
Maximum TJ = +85°C + (0.29W • (150°C/W) =
129°C
BOARD LAYOUT
Achieving
optimum
performance
with
a
high-frequency amplifier such as the OPA842
requires careful attention to board layout parasitics
and external component types. Recommendations
that will optimize performance include:
a) Minimize parasitic capacitance to any ac
ground for all of the signal I/O pins. Parasitic
capacitance on the output and inverting input pins
can cause instability: on the noninverting input, it can
react with the source impedance to cause
unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins
should be opened in all of the ground and power
planes around those pins. Otherwise, ground and
power planes should be unbroken elsewhere on the
board.
b) Minimize the distance (< 0.25in., or 0.635cm)
from the power-supply pins to high-frequency
0.1mF decoupling capacitors. At the device pins,
the ground and power-plane layout should not be in
close proximity to the signal I/O pins. Avoid narrow
power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The
power-supply connections should always be
decoupled with these capacitors. Larger (2.2mF to
6.8mF) decoupling capacitors, effective at lower
frequency, should also be used on the main supply
pins. These may be placed somewhat farther from
the device and may be shared among several
devices in the same area of the PCB.
c) Careful selection and placement of external
components will preserve the high-frequency
performance of the OPA842. Resistors should be a
very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially leaded resistors can
also provide good high-frequency performance.
Again, keep the leads and PCB trace length as short
as possible. Never use wire-wound type resistors in a
highfrequency application. Since the output pin and
inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series
output resistor, if any, as close as possible to the
output pin. Other network components, such as
noninverting input termination resistors, should also
be placed close to the package. Where double-side
component mounting is allowed, place the feedback
resistor directly under the package on the other side
of the board between the output and inverting input
pins. Even with a low parasitic capacitance shunting
the external resistors, excessively high resistor values
18
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
www.ti.com
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
can create significant time constants that can
degrade performance. Good axial metal-film or
surface-mount resistors have approximately 0.2pF in
shunt with the resistor. For resistor values greater
than 1.5kΩ, this parasitic capacitance can add a pole
and/or a zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible
consistent with load-driving considerations. It has
been suggested here that a good starting point for
design would be to set RG || RF ≤ 200Ω. Doing this
will automatically keep the resistor noise terms low,
and minimize the effect of the parasitic capacitance.
d) Connections to other wideband devices on the
board may be made with short, direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to the
next device as a lumped capacitive load. Relatively
wide traces (50mils to 100mils) should be used,
preferably with ground and power planes opened up
around them. Estimate the total capacitive load and
set RS from the plot of Recommended RS vs
Capacitive Load (Figure 15). Low parasitic capacitive
loads (less than 5pF) may not need an RS since the
OPA842 is nominally compensated to operate with a
2pF parasitic load. Higher parasitic capacitive loads
without an RS are allowed as the signal gain
increases (increasing the unloaded phase margin). If
a long trace is required, and the 6dB signal loss
intrinsic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω
environment is normally not necessary on board, and
in fact, a higher impedance environment will improve
distortion as shown in the distortion versus load plots.
With a characteristic board trace impedance defined
based on board material and trace dimensions, a
matching series resistor into the trace from the output
of the OPA842 is used as well as a terminating shunt
resistor at the input of the destination device.
Remember also that the terminating impedance will
be the parallel combination of the shunt resistor and
input impedance of the destination device; this total
effective impedance should be set to match the trace
impedance. If the 6dB attenuation of a doublyterminated transmission line is unacceptable, a long
trace can be series terminated at the source end
only. Treat the trace as a capacitive load in this case
and set the series resistor value as shown in the plot
of RS vs Capacitive Load. This will not preserve
signal integrity as well as a doubly-terminated line. If
the input impedance of the destination device is low,
there will be some signal attenuation due to the
voltage divider formed by the series output into the
terminating impedance.
e) Socketing a high-speed part like the OPA842 is
not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network,
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the OPA842 onto the board.
INPUT AND ESD PROTECTION
The OPA842 is built using a very high speed
complementary bipolar process. The internal junction
breakdown voltages are relatively low for these very
small geometry devices. These breakdowns are
reflected in the Absolute Maximum Ratings table. All
device pins have limited ESD protection using internal
diodes to the power supplies, as shown in Figure 44.
+VCC
External
Pin
-VCC
Figure 44. Internal ESD Protection
These diodes provide moderate protection to input
overdrive voltages above the supplies as well. The
protection diodes can typically support 30mA
continuous current. Where higher currents are
possible (for example, in systems with ±15V supply
parts driving into the OPA842), current-limiting series
resistors should be added into the two inputs. Keep
these resistor values as low as possible since high
values degrade both noise performance and
frequency response. Figure 45 shows an example
protection circuit for I/O voltages that may exceed the
supplies.
+5V
50W Source
Power-supply
decoupling not shown.
174W
V1
50W
50W D1
D2
OPA842
RF
301W
50W
301W
RG
VO
-5V
D1 = D2 IN5911 (or equivalent)
Figure 45. Gain of +2 with Input Protection
19
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
OPA842
SBOS267D – NOVEMBER 2002 – REVISED SEPTEMBER 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (December, 2008) to Revision D
Page
•
Updated document format to current standards ................................................................................................................... 1
•
Deleted lead temperature specifications from Absolute Maximum Ratings table ................................................................ 2
•
Added minimum operating voltage specification to Electrical Characteristics table ............................................................. 4
Changes from Revision B (March, 2006) to Revision C
•
Page
Changed minimum storage temperature range from −40°C to −65°C ................................................................................. 2
20
Copyright © 2002–2010, Texas Instruments Incorporated
Product Folder Link(s): OPA842
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
OPA842ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
842
OPA842IDBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAQI
OPA842IDBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAQI
OPA842IDBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAQI
OPA842IDBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAQI
OPA842IDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
842
OPA842IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
842
OPA842IDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OPA
842
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
OPA842IDBVR
SOT-23
DBV
5
3000
180.0
OPA842IDBVT
SOT-23
DBV
5
250
OPA842IDR
SOIC
D
8
2500
B0
(mm)
K0
(mm)
P1
(mm)
8.4
3.2
3.1
1.39
4.0
180.0
8.4
3.2
3.1
1.39
330.0
12.4
6.4
5.2
2.1
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
8.0
Q3
4.0
8.0
Q3
8.0
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA842IDBVR
SOT-23
DBV
5
3000
210.0
185.0
35.0
OPA842IDBVT
SOT-23
DBV
5
250
210.0
185.0
35.0
OPA842IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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