Freescale MAC7112MAF50 Microcontroller family hardware specification Datasheet

Freescale Semiconductor
Advance Information
MAC7100EC
Rev. 1.2, 02/2006
MAC7100 Microcontroller Family
Hardware Specifications
Covers MAC7101, MAC7106, MAC7111, MAC7116, MAC7121,
MAC7126, MAC7131, MAC7136, MAC71411
32-bit Embedded Controller Division
1. With preliminary information on MAC7112, MAC7122, MAC7142 devices.
This document provides electrical specifications, pin
assignments, and package diagrams for MAC7100
family of microcontroller devices. For functional
characteristics, refer to the MAC7100 Microcontroller
Family Reference Manual (MAC7100RM).
1
Overview
The MAC7100 Family of microcontrollers (MCUs) are
members of a pin-compatible family of 32-bit
Flash-memory-based devices developed specifically for
embedded automotive applications. The pin-compatible
family concept enables users to select between different
memory and peripheral options for scalable designs. All
MAC7100 Family members are composed of a 32-bit
ARM7TDMI-S™ central processing unit, up to 1 Mbyte
of embedded Flash EEPROM for program storage, up to
32 Kbytes of embedded Flash for data and/or program
storage, and up to 48 Kbytes of RAM. The family is
implemented with an enhanced DMA (eDMA) controller
to improve performance for transfers between memory
and many of the on-chip peripherals. The peripheral set
includes asynchronous serial communications interfaces
(eSCI), serial peripheral interfaces (DSPI),
Table of Contents
1 Overview .................................................................1
2 Ordering Information ...............................................2
3 Electrical Characteristics.........................................4
3.1 Parameter Classification......................................4
3.2 Absolute Maximum Ratings.................................4
3.3 ESD Protection and Latch-up Immunity ..............5
3.4 Operating Conditions...........................................6
3.5 Input/Output Characteristics................................7
3.6 Power Dissipation and Thermal Characteristics..8
3.7 Power Supply ....................................................11
3.8 Clock and Reset Generator ...............................15
3.9 External Bus Timing ..........................................20
3.10 Analog-to-Digital Converter ...............................24
3.11 Serial Peripheral Interface .................................29
3.12 FlexCAN Interface .............................................32
3.13 Common Flash Module .....................................32
4 Device Pin Assignments .......................................36
4.1 MAC7141 Pin Diagram......................................41
4.2 MAC7142 Pin Diagram......................................42
4.3 MAC7121 / MAC7126 Pin Diagram ...................43
4.4 MAC7122 Pin Diagram......................................44
4.5 MAC7101 / MAC7106 Pin Diagram ...................45
4.6 MAC7111 / MAC7116 Pin Diagram ...................46
4.7 MAC7112 Pin Diagram......................................47
4.8 MAC7131 Pin Diagram......................................48
4.9 MAC7136 Pin Diagram......................................49
5 Mechanical Information.........................................50
Revision History ....................................................51
This document contains information on a new product under development. Freescale
Semiconductor reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2004-2006. All rights reserved.
• Preliminary
Ordering Information
inter-integrated circuit (I2C™) bus controllers, FlexCAN interfaces, an enhanced modular I/O subsystem
(eMIOS), 10-bit analog-to-digital converter (ATD) module(s), general-purpose timers (PIT) and two
special-purpose timers (RTI and SWT). The peripherals share a large number of general purpose
input-output (GPIO) pins, all of which are bidirectional and available with interrupt capability to trigger
wake-up from low-power chip modes. Refer to Table 2 for a comparison of family members and
availability of peripheral modules on each device.
The use of a PLL allows power drain and performance to be balanced to best fit requirements. The
operating frequency of devices in the family is up to a maximum of 50 MHz. The internal data paths
between the CPU core, eDMA, memory and peripherals are all 32 bits wide, further improving
performance for 32-bit applications. The MAC7111, MAC7116, MAC7131 and MAC7136 also offer a
16-bit wide external data bus with 22 address lines. The family of devices is capable of operating over a
junction temperature range of –40° C to 150° C.
2
Ordering Information
M AC 7 1 0 1 C PV 50 xx
Qualification Status
Core Code
Core Number
Generation / Family
Package Option
Device Number
Temperature Range
Package Identifier
Speed (MHz)
Optional Package Identifiers
Temperature Option
C = –40° C to 85° C
V = –40° C to105° C
M = –40° C to125° C
FU =
AF =
PV =
AG =
VF =
VM =
Package Option
100 LQFP
100 LQFP, RoHS
112 / 144 LQFP
112 / 144 LQFP, RoHS
208 MAP BGA
208 MAP BGA, RoHS
Figure 1. Order Part Number Example
The mask set of a device is marked with a four-character code consisting of a letter, two numerical digits,
and a letter, for example L49P. Slight variations to the mask set identification code may result in an
optional numerical digit preceding the standard four-character code, for example 0L49P.
Table 1. MAC7100 Family Mask Set to Part Number Correspondence
Mask Set
Status
Part Number(s)
0L49P
Engineering samples
PAC7101, PAC7111, PAC7121, PAC7131, PAC7141
1L49P
Limited production, pre-qualification
PAC7101, PAC7111, PAC7121, PAC7131, PAC7141
0L47W
Limited production, pre-qualification
PAC7101, PAC7111, PAC7121, PAC7131, PAC7141
1L47W
Fully-qualified, production
0L61W
Engineering samples
PAC7112, PAC7122, PAC7142
0L38Y
Engineering samples
PAC7106, PAC7116, PAC7126, PAC7136
1L38Y
Fully-qualified, production
MAC7101, MAC7111, MAC7121, MAC7131, MAC7141
MAC7106, MAC7116, MAC7126, MAC7136
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
2
Preliminary
Freescale Semiconductor
Ordering Information
Program Flash
512 KBytes
32 KBytes
External Bus
CAN Modules
eSCI Modules
DSPI Modules
MAC7136
MAC7126
MAC7116
MAC7106
MAC7142
1 MByte
32 KBytes
SRAM
ATD
MAC7122
256 KBytes
Data Flash
Modules 1
MAC7112
MAC7141
MAC7131
MAC7121
Module Options
MAC7111
MAC7101
Table 2. MAC7100 Family Device Derivatives
16 KBytes
48 KBytes
—
Yes
—
Yes
—
—
—
—
—
Yes
—
Yes
A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
B
Yes
—
—
Yes
—
—
—
—
Yes
—
—
Yes
A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
C
Yes
Yes
Yes
Yes
—
—
—
—
Yes
Yes
Yes
Yes
D
Yes
Yes
Yes
Yes
—
—
—
—
Yes
Yes
Yes
Yes
A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
B
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
C
Yes
Yes
Yes
Yes
—
Yes
Yes
—
Yes
Yes
Yes
Yes
D
Yes
Yes
Yes
Yes
Yes
—
—
—
Yes
Yes
Yes
Yes
A
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes 2
B
Yes
Yes
Yes 3
Yes
Yes
Yes
Yes 3
Yes
Yes
Yes
Yes 3
Yes 2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
I2C Module
eMIOS Module
16 channels, 16-bit
Timer Module
10 channels, 24-bit
10
16
10
16
4
16
10
4
10
16
10
16
B
16
16
15
16
16
16
15
16
16
16
15
16
C
12
16
1
16
—
16
1
—
12
16
1
16
D
10 4
16 4
11 4
16 4
10 4
16
11
10
10
16
11
16
E
16
16
16
16
16
16
16
16
16
16
16
16
F
16
16
16
16
16
16
16
16
16
16
16
16
G
16
16
16
16
10
16
16
10
16
16
16
16
H
16
—
—
16
—
—
—
—
16
—
—
16
I
—
—
—
—
—
—
—
—
—
—
—
16
Total (max.)
112 4
112 4
85 4
112
85
72
112
112
85
144
Package
144
LQFP
144
LQFP
112
LQFP
144
LQFP
112
LQFP
100
LQFP
144
LQFP
144
LQFP
112
LQFP
208
BGA
General-Purpose
I/O Ports/Pins
A
128 4
208
BGA
72 4
100
LQFP
NOTES:
1. 16 channels, 8/10-bit, per module.
2. Four additional chip selects available.
3. PB11 / PCS2_B not available on non-L49P-mask devices; PB10 / PCS5_B / PCSS_B not available on mask L47W devices.
4. Reduce these values by one for mask set L49P devices (PD2 is not available for general-purpose use).
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
3
Electrical Characteristics
3
Electrical Characteristics
This section contains electrical information for MAC7100 Family microcontrollers. The information is
preliminary and subject to change without notice.
MAC7100 Family devices are specified and tested over the 5 V and 3.3 V ranges. For operation at any
voltage within that range, the 3.3 V specifications generally apply. However, no production testing is done
to verify operation at intermediate supply voltage levels.
3.1
Parameter Classification
The electrical parameters shown in this appendix are derived by various methods. To provide a better
understanding to the designer, the following classification is used. Parameters are tagged accordingly in
the column labeled “C” of the parametric tables, as appropriate.
Table 3. Parametric Value Classification
P
Parameters guaranteed during production testing on each individual device.
C
Parameters derived by the design characterization and by measuring a statistically relevant sample size across
process variations.
T
Parameters derived by design characterization on a small sample size from typical devices under typical conditions
(unless otherwise noted). All values shown in the typical column are within this classification, even if not so tagged.
D
Parameters derived mainly from simulations.
3.2
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. Functional operation outside these maximums is not
guaranteed. Stress beyond these limits may affect reliability or cause permanent damage to the device.
MAC7100 Family devices contain circuitry protecting against damage due to high static voltage or electrical
fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs
are tied to an appropriate logic voltage level (for example, either VSS51 or VDD51).
Table 4. Absolute Maximum Ratings
Num
Rating
A1a
I/O Drivers Supply Voltage
A2
Digital Logic Supply Voltage 1
1
Symbol
Min
Max
Unit
VDDX
–0.3
+6.0
V
VDD2.5
–0.3
+3.0
V
VDDPLL
–0.3
+3.0
V
VDDA
–0.3
+6.0
V
VRH, VRL
–0.3
+6.0
V
A3
PLL Supply Voltage
A4
Analog Supply Voltage
A5
Analog Reference
A6
Voltage difference VDDX to VDDA
ΔVDDX
–0.3
+0.3
V
A7
Voltage difference VSSX to VSSA
ΔVSSX
–0.3
+0.3
V
A8
Voltage difference VRH – VRL
VRH – VRL
–0.3
+6.0
V
1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
4
Preliminary
Freescale Semiconductor
Electrical Characteristics
Table 4. Absolute Maximum Ratings (continued)
Num
Rating
Symbol
Min
Max
Unit
VDDA – VRH
–0.3
+6.0
V
A9
Voltage difference VDDA – VRH
A10
Digital I/O Input Voltage
VIN
–0.3
+6.0
V
A11
XFC, EXTAL, XTAL inputs
VILV
–0.3
+3.0
V
A12
TEST input
VTEST
–0.3
—2
V
IDL
–25
+25
mA
ID
–25
+25
mA
IDA
–25
+25
mA
IDT
–0.25
0
mA
Tstg
–65
+155
°C
Instantaneous Maximum
Current 3
Single pin limit for XFC, EXTAL, XTAL 4
A13
5
A14
Single pin limit for all digital I/O pins
A15
Single pin limit for all analog input pins 5
2
A16
Single pin limit for TEST
A17
Storage Temperature Range
NOTES:
1. The device contains an internal voltage regulator to generate the logic and PLL supply from the I/O supply. The
absolute maximum ratings apply when the device is powered from an external source.
2. This pin is clamped low to VSSX, but not clamped high, and must be tied low in applications.
3. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor,
use the larger of the calculated values using VPOSCLAMP = VDDA + 0.3V and VNEGCLAMP = –0.3 V.
4. These pins are internally clamped to VSSPLL and VDDPLL.
5. All I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
3.3
ESD Protection and Latch-up Immunity
All ESD testing is in conformity with CDF-AEC-Q100 Stress test qualification for Automotive Grade
Integrated Circuits. During the device qualification ESD stresses were performed for the Human Body
Model (HBM), the Machine Model (MM) and the Charge Device Model.
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise.
Table 5. ESD and Latch-up Test Conditions
Model
Human Body
Machine
Latch-up
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ohm
Storage Capacitance
C
100
pF
Number of Pulses per pin
positive
negative
—
—
3
3
Series Resistance
R1
0
Ohm
Storage Capacitance
C
200
pF
Number of Pulse per pin
positive
negative
—
—
3
3
Minimum input voltage limit
–2.5
V
Maximum input voltage limit
7.5
V
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
5
Electrical Characteristics
Table 6. ESD and Latch-Up Protection Characteristics
Num
B1
C
Rating
Symbol
Min
Max
Unit
VHBM
2000
—
V
C Human Body Model (HBM)
B2
C Machine Model (MM)
VMM
200
—
V
B3
C Charge Device Model (CDM)
VCDM
500
—
V
B4
C Latch-up Current at TA = 125°C
positive
negative
ILAT
+100
–100
—
C Latch-up Current at TA = 27°C
positive
negative
ILAT
B5
3.4
mA
—
mA
+200
–200
Operating Conditions
Unless otherwise noted, the following conditions apply to all parametric data. Refer to the temperature
rating of the device (C, V, M) with respect to ambient temperature (TA) and junction temperature (TJ). For
power dissipation calculations refer to Section 3.6, “Power Dissipation and Thermal Characteristics.”
Table 7. MAC7100 Family Device Operating Conditions
Num
C1
Rating
Symbol
Min
Typ
Max
Unit
VDDX
3.15
5
5.5
V
I/O Drivers Supply Voltage
Voltage 1
VDD2.5
2.35
2.5
2.75
V
VDDPLL
2.35
2.5
2.75
V
Analog Supply Voltage
VDDA
3.15
5
5.5
V
Voltage Difference VDDX to VDDA
ΔVDDX
–0.1
0
0.1
V
C2
Digital Logic Supply
C3
PLL Supply Voltage 1
C4
C5
C6
Voltage Difference VSSX to VSSA
ΔVSSX
–0.1
0
0.1
V
C7
Oscillator Frequency
fOSC 2
0.5
—
16
MHz
C8
System Clock Frequency
fSYS 2
0.5
—
50
MHz
TJ
–40
—
110
°C
TA
–40
25
85
°C
C9a MAC71xxC
Operating Junction Temperature Range 3
Operating Ambient Temperature
Range 3
C10a MAC71xxV
Operating Junction Temperature
Range 3
–40
—
130
°C
Operating Ambient Temperature Range 3
TJ
C10b
TA
–40
25
105
°C
C11a MAC71xxM
Operating Junction Temperature Range 3
TJ
–40
—
150
°C
TA
–40
25
125
°C
C9b
C11b
Operating Ambient Temperature
Range 3
NOTES:
1. These ratings apply only when the VREG is disabled and the device is powered from an external source.
2. Throughout this document, tOSC refers to 1 ÷ fOSC, and tSYS refers to 1 ÷ fSYS.
3. Refer to Section 3.6, “Power Dissipation and Thermal Characteristics,” for more details about the relation between
ambient temperature TA and device junction temperature TJ.
3.4.1
Input/Output Pins
The I/O pins operate at a nominal level of 3.3 V to 5 V. This class of pins is comprised of the clocks, control
and general purpose/peripheral pins. The internal structure of these pins is identical; however, some
functionality may be disabled (for example, for analog inputs the output drivers, pull-up/down resistors
are permanently disabled).
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
6
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.4.2
Oscillator Pins
The pins XFC, EXTAL, XTAL are dedicated to the oscillator and operate at a nominal level of 2.5V.
3.5
Input/Output Characteristics
This section describes the characteristics of all I/O pins in both 3.3 V and 5 V operating conditions. All
parameters are not always applicable; for example, not all pins feature pull up/down resistances.
Table 8. 5.0 V I/O Characteristics
Conditions shown in Table 7 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
D1a P Input High Voltage
VIH
0.65 ×
VDD5 1
—
—
V
D1b T Input High Voltage
VIH
—
—
VDD5 +
0.3 1
V
D2a P Input Low Voltage
VIL
—
—
0.35 ×
VDD5 1
V
D2b T Input Low Voltage
VIL
VSS5 –
0.3 1
—
—
V
—
250
—
mV
–1 2
—
12
μA
VDD5 –
0.8
—
—
V
VOL
—
—
0.8
V
IPUL
—
—
–130
μA
P Internal Pull Up Device Current,
tested at VIH Min.
IPUH
–10
—
—
μA
P Internal Pull Down Device Current,
tested at VIH Min.
IPDH
—
—
130
μA
D10 P Internal Pull Down Device Current,
tested at VIL Max.
IPDL
10
—
—
μA
D11 D Input Capacitance
Cin
—
6
—
pF
IICS
IICP
–2.5
–25
D3
C Input Hysteresis
D4
P Input Leakage Current (pins in high impedance input mode)
V = V 5 or V 5 1
D5
P Output High Voltage (pins in output mode)
Partial Drive IOH = –2mA
Full Drive IOH = –10mA
P Output Low Voltage (pins in output mode)
Partial Drive IOL = +2mA
Full Drive IOL = +10mA
P Internal Pull Up Device Current,
tested at VIL Max.
V
D8
D9
in
D6
D7
VHYS
DD
Iin
SS
OH
3
D12 T Injection current
Single Pin limit
Total Device Limit. Sum of all injected currents
—
mA
2.5
25
D13 P Port Interrupt Input Pulse filtered 4
tPULSE
—
—
3
μs
D14 P Port Interrupt Input Pulse passed 4
tPULSE
10
—
—
μs
NOTES:
1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half
for each 8°C to 12°C in the temperature range from 50°C to 125°C.
3. Refer to Section 3.7.1, “Current Injection,” for more details
4. Parameter only applies in STOP or Pseudo STOP mode.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
7
Electrical Characteristics
Table 9. 3.3 V I/O Characteristics
Conditions shown in Table 7, with VDDX = 3.3 V –5%/+10% and a temperature maximum of +140°C unless otherwise noted.
Num C
Rating
Symbol
Min
Typ
Max
Unit
0.65 ×
VDD5 1
—
—
V
E1a P Input High Voltage
V
E1b
T Input High Voltage
VIH
—
—
VDD5 +
0.3 1
V
E2a P Input Low Voltage
VIL
—
—
0.35 ×
VDD5 1
V
E2b
T Input Low Voltage
VIL
VSS5 –
0.3 1
—
—
V
E3
C Input Hysteresis
—
IH
V
250
—
mV
Iin
–1 2
—
12
μA
HYS
E4
P Input Leakage Current (pins in high impedance input mode)
Vin = VDD5 or VSS5 1
E5
P Output High Voltage (pins in output mode)
Partial Drive IOH = –0.75mA
Full Drive IOH = –4.5mA
VOH
VDD5 –
0.4
—
—
V
E6
P Output Low Voltage (pins in output mode)
Partial Drive IOL = +0.9mA
Full Drive IOL = +5.5mA
VOL
—
—
0.4
V
E7
P Internal Pull Up Device Current,
tested at V Max.
IPUL
—
—
–60
μA
E8
P Internal Pull Up Device Current,
tested at VIH Min.
IPUH
–6
—
—
μA
E9
P Internal Pull Down Device Current,
tested at V Min.
IPDH
—
—
60
μA
E10 P Internal Pull Down Device Current,
tested at V Max.
IPDL
6
—
—
μA
E11 D Input Capacitance
Cin
—
6
—
pF
IICS
IICP
–2.5
–25
E13 P Port Interrupt Input Pulse filtered 4
tPULSE
—
—
3
μs
E14 P Port Interrupt Input Pulse passed 4
tPULSE
10
—
—
μs
IL
IH
IL
E12
T Injection current 3
Single Pin limit
Total Device Limit. Sum of all injected currents
—
mA
2.5
25
NOTES:
1. Refer to Section 3.7, “Power Supply,” for definition of VSS5 and VDD5.
2. Maximum leakage current occurs at maximum operating temperature. Current decreases by approximately one-half
for each 8°C to 12°C in the temperature range from 50°C to 125°C.
3. Refer to Section 3.7.1, “Current Injection,” for more details
4. Parameter only applies in STOP or Pseudo STOP mode.
3.6
Power Dissipation and Thermal Characteristics
Power dissipation and thermal characteristics are closely related. The user must assure that the maximum
operating junction temperature is not exceeded.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
8
Preliminary
Freescale Semiconductor
Electrical Characteristics
Note that the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for junction-toambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA
(Theta-JMA) will be used for both junction-to-ambient on a 2s2p test board in natural convection and for
junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated that the
generic name, θJA, will continue to be commonly used.
The average chip-junction temperature (TJ) in °C is obtained from the formula:
T J = T A + P D ⋅ Θ JA
Eqn. 1
where
T J = Junction Temperature ( ° C)
T A = Ambient Temperature ( ° C)
P D = Total Chip Power Dissipation (W)
Θ JA = Package Thermal Resistance ( ° C/W)
The total power dissipation is calculated as:
P D = P INT + P IO
Eqn. 2
where
P INT = Chip Internal Power Dissipation (W)
P IO = Input / Output Power Dissipation (W)
Two cases must be considered for PINT:
1. Internal voltage regulator enabled:
P INT = ( I DD R × V DD R ) + ( I DD A × V DD A )
Eqn. 3
2. Internal voltage regulator disabled (VDDR = VSSR = system ground):
P INT = ( I DD 2.5 × V DD 2.5 ) + ( I DD PLL × V DD PLL ) + ( I DD A × V DD A )
Eqn. 4
PIO is the sum of all output currents on input/output pins associated with VDDX:
P IO =
∑R
DSON
⋅ ( I IOi ) 2
Eqn. 5
i
where
V OL
R DSON = --------- (for outputs driven low)
I OL
Eqn. 6
V DD X – V OH
R DSON = ------------------------------- (for outputs driven high)
I OL
Eqn. 7
or
Table 10. Thermal Resistance 1/8 Simulation Model Packaging Parameters
Component
Mold Compound
Leadframe (Copper)
Die Attach
Conductivity
0.9 W/m K
263 W/m K
1.7 W/m K
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
9
Electrical Characteristics
3.6.1
Thermal Resistance Simulation Details
Table 11. Thermal Resistance for Case Outline 983–02, 100 Lead 14x14 mm LQFP, 0.5 mm Pitch
Rating
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Junction to Case
Junction to Package Top
Environment
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural Convection
Symbol
Value
Unit
Comments
RθJA
RθJMA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
44
34
37
29
18
7
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
5
6
Table 12. Thermal Resistance for Case Outline 987–01, 112 Lead 20x20 mm LQFP, 0.65 mm Pitch
Rating
Environment
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Junction to Case
Junction to Package Top
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural Convection
Symbol
Value
Unit
Comments
RθJA
RθJMA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
42
34
35
30
22
7
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
5
6
Table 13. Thermal Resistance for Case Outline 918–03, 144 Lead 20x20 mm LQFP, 0.5 mm Pitch
Rating
Environment
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Junction to Case
Junction to Package Top
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural Convection
Symbol
Value
Unit
Comments
RθJA
RθJMA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
42
34
35
30
22
7
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
5
6
Table 14. Thermal Resistance for Case Outline 1159A-01, 208 Lead 17x17 mm MAP BGA, 1.0 mm Pitch
Rating
Environment
Junction to Ambient (Natural Convection)
Junction to Ambient (Natural Convection)
Junction to Ambient (@ 200 ft./min.)
Junction to Ambient (@ 200 ft./min.)
Junction to Board
Junction to Case
Junction to Package Top
Single layer board (1s)
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
Natural Convection
Symbol
Value
Unit
Comments
RθJA
RθJMA
RθJMA
RθJMA
RθJB
RθJC
ΨJT
46
29
38
26
19
7
2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3
1, 3
4
5
6
Comments:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,
ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board (JESD51-3) horizontal.
3. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface
of the board at the center lead. For fused lead packages, the adjacent lead is used.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and junction temperature per JEDEC
JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
10
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.7
Power Supply
The MAC71xx Family utilizes several pins to supply power to the oscillator, PLL, digital core, I/O ports
and ATD. In the context of this section, VDD5 is used for VDDA, VDDR or VDDX; VSS5 is used for VSSA,
VSSR or VSSX unless otherwise noted. IDD5 denotes the sum of the currents flowing into the VDDA,
VDDX, and VDDR. VDD is used for VDD2.5, and VDDPLL, VSS is used for VSS2.5 and VSSPLL. IDD is
used for the sum of the currents flowing into VDD2.5 and VDDPLL.
3.7.1
Current Injection
The power supply must maintain regulation within the VDD5 or VDD2.5 operating range during
instantaneous and operating maximum current conditions. If positive injection current (Vin > VDD5) is
greater than IDD5, the injection current may flow out of VDD5 and could result in the external power supply
going out of regulation. It is important to ensure that the external VDD5 load will shunt current greater than
the maximum injection current. The greatest risk will be when the MCU is consuming very little power
(for example, if no system clock is present, or if the clock rate is very low).
3.7.2
Power Supply Pins
The VDDR – VSSR pair supplies the internal voltage regulator. The VDDA – VSSA pair supplies the A/D
converter and the reference circuit of the internal voltage regulator. The VDDX – VSSX pair supplies the
I/O pins. VDDPLL – VSSPLL pair supplies the oscillator and PLL.
All VDDX pins are internally connected by metal. All VSSX pins are internally connected by metal. All
VSS2.5 pins are internally connected by metal. VDDA, VDDX and VDDR as well as VSSA, VSSX and VSSR
are connected by anti-parallel diodes for ESD protection.
3.7.3
Supply Current Characteristics
Table 15 and Table 16 list supply current characteristics for MAC71x1 and MAC71x6 devices at 40 MHz
and 50 MHz operation, respectively. Characteristics for MAC71x2 devices are to be determined (TBD).
All current measurements are without output loads. Unless otherwise noted the currents are measured in
single chip mode, internal voltage regulator enabled at the specified system frequency, using a 4 MHz
oscillator in low power mode. Production testing is performed using a square wave signal at the EXTAL
input. In expanded modes, the currents are highly dependent on the load and duty cycle on the address,
data and control signals, thus no general numbers can be given. A good estimate is to take the single chip
currents and add the currents due to the external loads.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
11
Electrical Characteristics
Table 15. MAC71x1/6 1 Device Supply Current Characteristics – 40 MHz
Conditions shown in Table 7, with fSYS = 40 MHz.
Num C
Rating
F1
P Run Supply Current, Single Chip
F2
C Doze Supply Current
F3
Typ
Max
Unit
IDDRreg
100
130
mA
Run ≥ Doze ≥ Pseudo Stop
IDDDreg
400 / 500 3
600 / 700 3
μA
25° C 2
400 / 500 3
600 / 700 3
μA
C
85° C 2
800 / 1000 3
2000 / 2500 3
μA
C
C2
3500 / 4000
3
μA
5500 / 6000
3
μA
P Pseudo Stop Supply Current
(OSC on)
P
–40°
105°
P
F4
Symbol
C2
125° C
P Stop Supply Current
(TJ = TA assumed)
P
–40°
IDDPSreg
2
C2
IDDSreg
1200 / 1500
3
1500 / 2000
3
30
150
μA
30
150
μA
85° C
2
330
2500
μA
C
105° C
2
470
3500
μA
P
125° C 2
660
5000
μA
25° C 2
C
NOTES:
1. MAC71x2 characteristics are to be determined (TBD).
2. 85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.
3. RTI disabled / enabled.
Table 16. MAC71x1/6 1 Device Supply Current Characteristics – 50 MHz
Conditions shown in Table 7, with fSYS = 50 MHz.
Num C
Rating
Symbol
Typ
Max
Unit
120
150
mA
G1
P Run Supply Current, Single Chip
IDDRreg
G2
C Doze Supply Current
IDDDreg
G3
P Pseudo Stop Supply Current
(OSC on)
P
C
G4
–40° C 2
25° C
85°
IDDPSreg
2
Run ≥ Doze ≥ Pseudo Stop
400 / 500 3
600 / 700 3
3
3
400 / 500
C2
800 / 1000
3
600 / 700
2000 / 2500
μA
μA
3
μA
C
105° C 2
1200 / 1500 3
3500 / 4000 3
μA
P
125° C 2
1500 / 2000 3
5500 / 6000 3
μA
30
150
μA
30
150
μA
P Stop Supply Current
(TJ = TA assumed)
P
–40°
C2
25° C
IDDSreg
2
C
85° C 2
330
2500
μA
C
105° C 2
470
3500
μA
P
2
660
5000
μA
125° C
NOTES:
1. MAC71x2 characteristics are to be determined (TBD).
2. 85°C, 105°C, and 125°C refer to the "C", "V", and "M" Temperature Options, respectively.
3. RTI disabled / enabled.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
12
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.7.4
Voltage Regulator Characteristics
Table 17. VREG Operating Conditions
Num
C
Characteristic
Symbol
Min
Typical
Max
Unit
3.15
—
5.5
V
2.45
1.60
—1
2.5
2.5
—1
2.75
2.75
—1
V
V
V
2.35
2.00
1.60
—1
2.5
2.5
2.5
—1
2.75
2.75
2.75
—1
V
V
V
V
H1
P Input Voltages
VVDDRA
H2
P Output Voltage, Digital Logic
Full Performance Mode
Reduced Power Mode
Shutdown Mode
VDD2.5
P Output Voltage, PLL
Full Performance Mode
Reduced Power Mode 2
Reduced Power Mode 3
Shutdown Mode
VDDPLL
H3
H4
H5
H6
P Low Voltage Interrupt 4
Assert Level
Negate Level
VLVIA
VLVID
4.10
4.25
4.37
4.52
4.66
4.77
V
V
P Low Voltage Reset 5
Assert Level
VLVRA
2.25
2.35
—
V
P Power On Reset 6
Assert Level
Negate Level
VPORA
VPORD
0.97
—
—
—
—
2.05
V
V
NOTES:
1. High impedance output.
2. Current IDDPLL = 1 mA (Low Power Oscillator).
3. Current IDDPLL = 3 mA (Standard Oscillator).
4. Monitors VDDA, active only in full performance mode. This interrupt indicates that I/O and ATD performance may be
degraded due to low supply voltage.
5. Monitors VDD2.5, active only in full performance mode. Only POR is active in reduced performance mode.
6. Monitors VDD2.5, active in all modes.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
13
Electrical Characteristics
3.7.5
Chip Power Up and Voltage Drops
The VREG sub-modules LVI (low voltage interrupt), POR (power on reset) and LVR (low voltage reset)
handle chip power-up or drops of the supply voltage. Refer to Figure 2.
Voltage
VDDA
VLVID
VLVIA
VDD2.5
VLVRD
VLVRA
VPORD
LVI Enabled
LVI
LVI Disabled
due to LVR
Time
POR
LVR
Note: Not to scale.
Figure 2. VREG Chip Power-up and Voltage Monitoring
3.7.6
Output Loads
The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external
DC load is allowed. Capacitive loads are specified in Table 18. Capacitors with X7R dielectricum are
required.
Table 18. VREG Recommended Load Capacitances
Rating
Load Capacitance per VDD2.5 pin 1
Load Capacitance on VDDPLL pin
Symbol
Min
Typ
Max
Unit
CLVDD
200
220
12000
nF
CLVDDfcPLL
90
220
5000
nF
NOTES:
1. Refer to Table 38 for the specific number of VDD2.5 pins on various packages. Each VDD2.5 pin should have the
recommended loading as described in Section 3.7.3, “Circuit Board Layout,” of the MAC7100 Microcontroller Family
Reference Manual (MAC7100RM).
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
14
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.8
Clock and Reset Generator
This section describes the electrical characteristics for the oscillator, phase-locked loop, clock monitor and
reset generator.
3.8.1
Oscillator Characteristics
The MAC7100 Family features an internal low power loop controlled Pierce oscillator and a full swing
Pierce oscillator/external clock mode. The selection of loop controlled Pierce oscillator or full swing
Pierce oscillator/external clock depends on the level of the XCLKS signal at the rising edge of the RESET
signal. Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the
oscillation is checked for each start from either power on, STOP or oscillator fail. tCQOUT specifies the
maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation
is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device
also features a clock monitor. A Clock Monitor Failure is asserted if the frequency of the incoming clock
signal is below the Clock Monitor Assert Frequency fCMFA.
Table 19. Oscillator Characteristics
Num C
J1a
Rating
C Crystal oscillator range (loop controlled Pierce)
Pierce) 2 3
Symbol
Min
Typ
Max
Unit
fOSC 1
4.0
—
16
MHz
1
0.5
—
40
MHz
IOSC
100
—
—
μA
J1b
C Crystal oscillator range (full swing
J2
P Startup Current
J3
C Oscillator start-up time (loop controlled Pierce)
tUPOSC
—
34
50 5
ms
J4
D Clock Quality check time-out
tCQOUT
0.45
—
2.5
s
J5
P Clock Monitor Failure Assert Frequency
fCMFA
50
100
200
KHz
J6
P External square wave input frequency
3
fEXT
0.5
—
50
MHz
J7
D External square wave pulse width low
tEXTL
9.5
—
—
ns
J8
D External square wave pulse width high
tEXTH
9.5
—
—
ns
J9
D External square wave rise time
tEXTR
—
—
1
ns
J10
D External square wave fall time
tEXTF
—
—
1
ns
J11
D Input Capacitance (EXTAL, XTAL pins)
CIN
—
7
—
pF
fOSC
NOTES:
1. If CLKSEL[PLLSEL] is clear then the system clock (fSYS) is equal to fOSC, otherwise it is equal to fVCO (table
Table 20, K3). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS.
2. Depending on the crystal; a damping series resistor might be necessary
3. XCLKS asserted (low) during reset
4. fOSC = 4 MHz, C = 22 pF (refer to the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for circuit
board layout recommendations, including oscillator capacitor placement and values).
5. Maximum value is for extreme cases using high Q, low frequency crystals
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
15
Electrical Characteristics
3.8.2
PLL Filter Characteristics
The oscillator provides the reference clock for the PLL as shown in Figure 3. The voltage controlled
oscillator (VCO) of the PLL is also the system clock source in self clock mode. In order to operate reliably,
care must be taken to select proper values for external loop filter components.
VDDPLL
Phase
Detector
fOSC
1
REFDV+1
fREF
Δ
CS
CP
VCO
R
Kφ
fCMP
KV
fVCO
Loop Divider
1
1
SYNR+1
2
Figure 3. Basic PLL Functional Diagram
The procedure described below can be used to calculate the resistance and capacitance values using typical
values for K1, f1 and ich from Table 20. First, the VCO Gain at the desired VCO output frequency is
approximated by:
KV = K1 ⋅ e
( f 1 – f VCO )
-------------------------K 1 ⋅ 1V
Eqn. 8
The phase detector relationship is given by:
K Φ = – i ch ⋅ K V
Eqn. 9
ich is the current in tracking mode. The loop bandwidth fC should be chosen to fulfill the Gardner’s stability
criteria by at least a factor of 10, a typical value for the stability factor is 50. ζ = 0.9 ensures a good transient
response.
2 ⋅ ζ ⋅ f REF
f REF
1
------ → f C < ------------f C < ---------------------------------------- ; ( ζ = 0.9 )
4 ⋅ 10
2 10
π ⋅ (ζ + 1 + ζ )
Eqn. 10
And finally the frequency relationship is defined as:
f VCO
n = ---------= 2 ⋅ ( SYNR + 1 )
f REF
Eqn. 11
With the above inputs the resistance can be calculated as:
2⋅π⋅n⋅f
R = ---------------------------CKΦ
Eqn. 12
The capacitance CS can now be calculated as:
2
2⋅ζ
0.516
C S = --------------------- ≈ ------------- ; ( ζ = 0.9 )
π ⋅ fC ⋅ R fC ⋅ R
Eqn. 13
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
16
Preliminary
Freescale Semiconductor
Electrical Characteristics
The capacitance CP should be chosen in the range of:
C S ÷ 20 ≤ C P ≤ C S ÷ 10
Eqn. 14
The stabilization delays shown in Table 20 are dependant on PLL operational settings and external
component selection (for example, the crystal and XFC filter).
3.8.2.1
Jitter Information
With each transition of the clock fCMP, the deviation from the reference clock fREF is measured and input
voltage to the VCO is adjusted accordingly. The adjustment is done continuously with no abrupt changes
in the clock output frequency. Noise, voltage, temperature and other factors cause slight variations in the
control loop resulting in a clock jitter. This jitter affects the real minimum and maximum clock periods as
illustrated in Figure 4. It is important to note that the pre-scaler used by timers and serial modules will
eliminate the effect of PLL jitter to a large extent.
0
1
2
3
N–1
N
tMIN1
tNOM
tMAX1
tMIN(N)
tMAX(N)
Figure 4. Jitter Definitions
The relative deviation of tNOM is at its maximum for one clock period, and decreases towards zero for
larger number of clock periods (N). Thus, jitter is defined as:
t MAX ( N )
t MIN ( N ) ⎞
- , 1 – ------------------J ( N ) = max ⎛ 1 – ------------------⎝
N ⋅ tNOM
N ⋅ t NOM ⎠
Eqn. 15
For N < 100, the following equation is a good fit for the maximum jitter:
j1
J ( N ) = ------- + j2
N
Eqn. 16
J(N)
0 1
5
10
15
20
N
Figure 5. Maximum Bus Clock Jitter Approximation
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
17
Electrical Characteristics
3.8.3
PLL Characteristics
Table 20. PLL Characteristics
Num C
K1
K2
Rating
PLL reference frequency, crystal oscillator range
P Self Clock Mode frequency
K3
D VCO locking range
K4
D Lock Detector transition from Acquisition to Tracking mode
K5
D Lock Detection
K6
Symbol
Min
Typ
fREF
0.5
fSCM
2
1
Max
Unit
—
16
MHz
—
5.5
MHz
8
—
50
MHz
|Δtrk|
3
—
4
%2
|ΔLock|
0
—
1.5
%2
D Un-Lock Detection
|Δunl|
0.5
—
2.5
%2
K7
D Lock Detector transition from Tracking to Acquisition mode
|Δunt|
6
—
8
%2
K8
C PLLON Total Stabilization delay (Auto Mode) 3
tstab
—
0.5 4
35
ms
tacq
—
0.3
4
5
ms
tal
—
0.2 4
25
ms
K11 D Charge pump current acquisition mode
| ich |
—
38.5
—
μA
K12 D Charge pump current tracking mode
| ich |
—
3.5
—
μA
K13 D Jitter fit VCO loop gain parameter
K1
—
–195
—
MHz/V
K14 D Jitter fit VCO loop frequency parameter
f1
—
126
—
MHz
K15 C Jitter fit parameter 1
j1
—
—
1.3
%4
K16 C Jitter fit parameter 2
j2
—
—
0.12
%4
fVCO
K9 D PLLON Acquisition mode stabilization delay
K10 D PLLON Tracking mode stabilization delay 3
3
1
NOTES:
1. If CLKSEL[PLLSEL] is set then the system clock (fSYS) is equal to fVCO, otherwise it is equal to fOSC (table Table 19,
J1a or J1b). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS.
2. Percentage deviation from target frequency
3. PLL stabilization delay is highly dependent on operational requirement and external component values (for
example, crystal and XFC filter component values). Notes 4 and 5 show component values for a typical
configurations. Appropriate XFC filter values should be chosen based on operational requirement of system.
4. fOSC = 4 MHz, fVCO = 40 MHz (REFDV = 0x00, SYNR = 0x04), CS = 2.2 nF, CP = 220 pF, RS = 5.6 KΩ.
5. fOSC = 4 MHz, fVCO = 16 MHz (REFDV = 0x00, SYNR = 0x01), CS = 4.7 nF, CP = 470 pF, RS = 2.7 KΩ.
3.8.4
Crystal Monitor Time-out
The time-out Table 21 shows the delay for the crystal monitor to trigger when the clock stops, either at the high
or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.
Table 21. Crystal Monitor Time-Outs
Min
6
3.8.5
Typ
10
Max
18.5
Unit
μs
Clock Quality Checker
The timing for the clock quality check is derived from the oscillator and the VCO frequency range in
Table 20. These numbers define the upper time limit for the individual check windows to complete.
Table 22. CRG Maximum Clock Quality Check Timings
Clock Check Windows
Check Window
Timeout Window
Value
9.1 to 20.0
0.46 to 1.0
Unit
ms
s
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
18
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.8.6
Startup
Table 23 summarizes several startup characteristics. Refer to Section 4.3.6.10, “CRG Operating Mode
Details,” in the MAC7100 Microcontroller Family Reference Manual (MAC7100RM) for details.
Table 23. CRG Startup Characteristics
Num C
Rating
L1
D Reset input pulse width
L2
D Startup from Reset
L3
D XIRQ, IRQ pulse width, edge-sensitive mode
3.8.6.1
Symbol
Min
Typ
Max
Unit
PWRSTL
2
—
—
tOSC
nRST
192
—
196
tOSC
PWIRQ
20
—
—
ns
Power On and Low Voltage Reset (POR and LVR)
The VPORR and VPORA levels are derived from VDD2.5. The VLVRA level is derived from VDD2.5. They
are also valid if the device is powered externally. After releasing a POR or LVR reset, the oscillator and
clock quality checks start. After tCQOUT (Table 19, J4) if no valid oscillation is detected, the MCU will
start using the internal self-generated clock. The minimum startup time is given by tuposc (Table 19, J3).
3.8.6.2
SRAM Data Retention
SRAM content integrity is guaranteed if the CRGFLG[PORF] bit is not set following a reset operation.
3.8.6.3
External Reset
When external reset is asserted for a time greater than PWRSTL, the CRG generates an internal reset and
the CPU fetches the reset vector without a clock quality check, if there was stable oscillation before reset.
3.8.6.4
Stop Recovery
The MCU can return from stop to run mode in response to an external interrupt or an API. Two delays
occur before the MCU resumes execution. First, the voltage regulator must exit reduced power mode and
return to full performance mode (this assumes that the internal regulator is used rather than driving VDD2.5
and VDDPLL with an external regulator). Second, a clock quality check is performed in the same manner
as for a power-on reset before releasing the clocks to the system.
3.8.6.5
Pseudo Stop Recovery
Recovery from pseudo stop mode is similar to stop mode in that the VREG must return to FPM, but since
the oscillator is not stopped there is no delay for clock stabilization. The MCU is returned to run mode by
internal or external interrupts.
3.8.6.6
Doze Recovery
Recovery from doze mode avoids both the VREG and oscillator recovery periods. The MCU is returned
to run mode by internal or external interrupts.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
19
Electrical Characteristics
3.9
External Bus Timing
Table 24 lists processor bus input timings, which are shown in Figure 6, Figure 7 and Figure 8.
NOTE
All processor bus timings are synchronous; that is, input setup/hold and output delay
with respect to the rising edge of a reference clock. The reference clock is the
CLKOUT output. All other timing relationships can be derived from these values.
Table 24. External Bus Input Timing Specifications 1
Num
M1
C
Rating
Symbol
Min
Max
Unit
tCYC
20
—
ns
tCVCH
13
—
ns
tCHCII
0
—
ns
P CLKOUT period 2
Control Inputs
M2a
M3a
P Control input valid to CLKOUT high 3
P CLKOUT high to control inputs
invalid 3
Data Inputs
M4
P Data input (DATA[15:0]) valid to CLKOUT high
tDIVCH
9
—
ns
M5
P CLKOUT high to data input (DATA[15:0]) invalid
tCHDII
0
—
ns
NOTES:
1. Assumes CLKOUT is configured for full drive strength (via the PIM CONFIG2_D[RDS] bit).
2. CLKOUT is equal to the system clock, fSYS. If CLKSEL[PLLSEL] is set then fSYS is equal to fVCO (table Table 20,
K3); if it is clear then fSYS is equal to fOSC (table Table 19, J1a or J1b). Throughout this document, tCYC is used to
specify a unit of time equal to 1 ÷ CLKOUT (which is equal to tfsys).
3. The TA pin is the only control input on MAC7100 family devices.
CLKOUT (50 MHz)
1.5 V
tSETUP
tHOLD
Input Setup & Hold
Invalid
Input Rise Time
VH = VIH
VL = VIL
Input Fall Time
VH = VIH
VL = VIL
1.5 V Valid 1.5 V
Invalid
tRISE = 1.5 ns
tFALL = 1.5 ns
CLKOUT
M4
M5
Inputs
Figure 6. General Input Timing Requirements
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
20
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.9.1
Read and Write Bus Cycles
Table 25 lists processor bus output timings. Read/write bus timings listed in Table 25 are shown in
Figure 7 and Figure 8.
Table 25. External Bus Output Timing Specifications 1
Num
C
Rating
Symbol
Min
Max
Unit
tCHCV
—
0.5tCYC + 10
ns
tCHBV
—
0.5tCYC + 10
ns
tCHOV
—
0.5tCYC + 10
ns
Control Outputs
M6a
M6b
P CLKOUT high 2 to chip selects (CS[2:0]) valid
2
P CLKOUT high to byte selects (BS[1:0]) valid
high 2
M6c
P CLKOUT
M6d
P CLKOUT high 2 to address strobe (AS) valid
tCHASV
—
0.5tCYC + 10
ns
M7a
P CLKOUT high 2 to control output (BS[1:0], OE) invalid
tCHCOI
0.5tCYC + 2
—
ns
tCHCI
0.5tCYC + 2
—
ns
tCHASI
0.5tCYC + 2
—
ns
M7b
M7c
P CLKOUT
high 2
to output select (OE) valid
to chip selects (CS[2:0]) invalid
2
P CLKOUT high to address strobe (AS) invalid
Address and Attribute Outputs
M8
P CLKOUT high to address (ADDR[21:0]) and control
(R/W) valid
tCHAV
—
10
ns
M9
P CLKOUT high to address (ADDR[21:0]) and control
(R/W) invalid
tCHAI
2
—
ns
Data Outputs
M10
P CLKOUT high to data output (DATA[15:0]) valid
tCHDOV
—
13
ns
M11
P CLKOUT high to data output (DATA[15:0]) invalid
tCHDOI
2
—
ns
M12
D CLKOUT high to data output (DATA[15:0]) high impedance
tCHDOZ
—
9
ns
NOTES:
1. Assumes CLKOUT, CSn, BSn, OE, AS, ADDR[21:0] and DATA[15:0] are configured for full drive strength (via the PIM).
2. The CSn, BSn, OE and AS signals are synchronous to the falling edge of CLKOUT. Therefore, changes on these
signals are triggered by the falling edge of CLKOUT, even though they are specified in relation to the rising edge.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
21
Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
M6d
M6d
M7c
M7c
AS(1)
M6a
M6a
M7b
M7b
CSn
M8
M8
M9
ADDR[21:0]
M1
M6c
M7a
OE
M8
M9
R/W
M6b
M6b
M7a
M7a
BS[1:0]
M10
M4
M11
DATA[15:0]
M5
M12
TA(1)
1. The TA / AS signals are multiplexed on a single pin, so only one function may be used during bus transactions.
Figure 7. Read/Write Bus Cycles, Internal Termination
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
22
Preliminary
Freescale Semiconductor
Electrical Characteristics
S0
S1
S2
S3
S4
S5
S0
S1
CLKOUT
M6a
M7b
CSn
M8
M9
ADDR[21:0]
M6c
M7a
OE
R/W
M6b
M7a
BS[1:0]
M4
M5
DATA[15:0]
M2a
M3a
TA(1)
1. The TA / AS signals are multiplexed on a single pin, so AS is not available when external cycle termination is used.
Figure 8. Read Bus Cycle, External Termination
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
23
Electrical Characteristics
3.10 Analog-to-Digital Converter
Table 26 and Table 27 show conditions under which the ATD operates. The following constraints exist to
obtain full-scale, full range results: VSSA ≤ VRL ≤ VIN ≤ VRH ≤ VDDA. This constraint exists because the
sample buffer amplifier cannot drive beyond the ATD power supply levels. If the input level goes outside of
this range it will effectively be clipped.
Table 26. ATD Operating Characteristics in 5.0 V Range
Conditions shown in Table 7 unless otherwise noted
Num C
Rating
Low
High
Symbol
Min
Typ
Max
Unit
VRL
VRH
VSSA
VDDA ÷ 2
—
—
VDDA ÷ 2
VDDA
V
V
VRH – VRL
4.50
5.00
5.50
V
N1
D Reference Potential
N2
C Differential Reference Voltage 1
N3
D ATD Clock Frequency
fATDCLK
0.5
—
2.0
MHz
N4
D ATD 10-bit Conversion PeriodfATDCLK Cycles 2
NCONV10
@ 2.0MHz fATDCLK TCONV10
14
7
—
—
28
14
Cycles
μs
N5
D ATD 8-bit Conversion PeriodfATDCLK Cycles 2
@ 2.0MHz fATDCLK
NCONV8
TCONV8
12
6
—
—
26
13
Cycles
μs
N6
D Stop Recovery Time (VDDA = 5.0 V)
TREC
—
—
20
μs
N7
P Reference Supply current 1 ATD module on
IREF
—
0.200
0.255
mA
N8
P Reference Supply current 2 ATD modules on
IREF
—
0.400
0.510
mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 4.50 V
2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.
Table 27. ATD Operating Characteristics in 3.3 V Range
Conditions shown in Table 7, with VDDX = 3.3 V –5/+10% and a temperature maximum of +140°C unless otherwise
noted.
Num C
Rating
Low
High
Symbol
Min
Typ
Max
Unit
VRL
VRH
VSSA
VDDA ÷ 2
—
—
VDDA ÷ 2
VDDA
V
V
VRH – VRL
3.15
3.3
3.6
V
P1
D Reference Potential
P2
C Differential Reference Voltage 1
P3
D ATD Clock Frequency
fATDCLK
0.5
—
2.0
MHz
P4
D ATD 10-bit Conversion PeriodfATDCLK Cycles 2
NCONV10
@ 2.0MHz fATDCLK TCONV10
14
7
—
—
28
14
Cycles
μs
P5
D ATD 8-bit Conversion PeriodfATDCLK Cycles 2
@ 2.0MHz fATDCLK
NCONV8
TCONV8
12
6
—
—
26
13
Cycles
μs
P6
D Stop Recovery Time (VDDA = 3.3 V)
TREC
—
—
20
μs
P7
P Reference Supply current 1 ATD module on
IREF
—
0.130
0.170
mA
P8
P Reference Supply current 2 ATD modules on
IREF
—
0.260
0.340
mA
NOTES:
1. Full accuracy is not guaranteed when differential voltage is less than 3.15 V
2. Minimum time assumes a sample period of 2 ATD clocks; maximum time assumes a sample period of 16 ATD clocks.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
24
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.10.1 Factors Influencing Accuracy
Three factors—source resistance, source capacitance and current injection—have an influence on the
accuracy of the ATD.
3.10.1.1 Source Resistance
Due to the input pin leakage current as specified in Table 8 in conjunction with the source resistance there
will be a voltage drop from the signal source to the ATD input. The maximum specified source resistance
RS, results in an error of less than 1/2 LSB (2.5 mV) at the maximum leakage current. If the device or
operating conditions are less than the worst case, or leakage-induced errors are acceptable, larger values
of source resistance are allowed.
3.10.1.2 Source Capacitance
When sampling, an additional internal capacitor is switched to the input. This can cause a voltage drop due
to charge sharing with the external capacitance and the pin capacitance. For a maximum sampling error of
the input voltage ≤ 1 LSB, then the external filter capacitor must be calculated as, Cf ≥ 1024 × (CINS – CINN).
3.10.1.3 Current Injection
There are two cases to consider:
1. A current is injected into the channel being converted. The channel being stressed has conversion
values of 0x3FF (0xFF in 8-bit mode) for analog inputs greater than VRH and 0x000 for values less
than VRL unless the current is higher than specified as disruptive condition.
2. Current is injected into pins in the neighborhood of the channel being converted. A portion of this
current is picked up by the channel (coupling ratio K), This additional current impacts the
accuracy of the conversion depending on the source resistance. The additional input voltage error
on the converted channel can be calculated as VERR = K × RS × IINJ, with IINJ being the sum of
the currents injected into the two pins adjacent to the converted channel.
Table 28. ATD Electrical Characteristics
Conditions are shown in Table 7 unless otherwise noted
Num C
Rating
Q1
C Max input Source Resistance
Q2
C Total Input Capacitance
Non Sampling
Sampling
Symbol
Min
Typ
Max
Unit
RS
—
—
1
kΩ
CINN
CINS
—
—
10
22
—
—
pF
pF
Q3
C Disruptive Analog Input Current
INA
–2.5
—
2.5
mA
Q4
C Coupling Ratio positive current injection
Kp
—
—
TBD
A/A
Q5
C Coupling Ratio negative current injection
Kn
—
—
TBD
A/A
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
25
Electrical Characteristics
3.10.2 ATD Accuracy
Table 29 and Table 30 specify the ATD conversion performance excluding any errors due to current
injection, input capacitance and source resistance.
Table 29. ATD Conversion Performance in 5.0 V Range
Conditions shown in Table 7 except as noted here:
fATDCLK = 2.0 MHz, 4.5 V ≤ VDDA ≤ 5.5 V
Num C
Rating
Symbol
Min
Typ
Max
Unit
R1
P 10-bit Resolution
LSB
—
51
—
mV
R2
P 10-bit Differential Nonlinearity
DNL
–1
—
1
Counts
R3
P 10-bit Integral Nonlinearity
INL
–2.5
±1.5
2.5
Counts
R4
P 10-bit Absolute Error 2
AE
–3
±2.0
3
Counts
—
mV
0.5
Counts
R5
P 8-bit Resolution
LSB
—
20 1
R6
P 8-bit Differential Nonlinearity
DNL
–0.5
—
R7
P 8-bit Integral Nonlinearity
INL
–1.0
±0.5
1.0
Counts
R8
P 8-bit Absolute Error 2
AE
–1.5
±1.0
1.5
Counts
Max
Unit
NOTES:
1. Assumes VREF = VRH – VRL = 5.12 V, other VREF conditions result in different LSB resolutions.
2. These values include the quantization error which is inherently ½ count for any A/D converter.
Table 30. ATD Conversion Performance in 3.3 V Range
Conditions shown in Table 7 except as noted here:
fATDCLK = 2.0 MHz, 3.15 V ≤ VDDA ≤ 3.6 V
Num C
Rating
Symbol
Min
Typ
S1
P 10-bit Resolution
LSB
—
3.25 1
—
mV
S2
P 10-bit Differential Nonlinearity
DNL
–1.5
—
1.5
Counts
S3
P 10-bit Integral Nonlinearity
INL
–3.5
±1.5
3.5
Counts
S4
P 10-bit Absolute Error 2
AE
–5
±2.0
5
Counts
S5
P 8-bit Resolution
LSB
—
13 1
—
mV
S6
P 8-bit Differential Nonlinearity
DNL
–0.5
—
0.5
Counts
S7
P 8-bit Integral Nonlinearity
INL
–1.5
±1.0
1.5
Counts
S8
P 8-bit Absolute Error 2
AE
–1.5
±1.0
1.5
Counts
NOTES:
1. Assumes VREF = VRH – VRL = 3.33 V, other VREF conditions result in different LSB resolutions.
2. These values include the quantization error which is inherently ½ count for any A/D converter.
For the following definitions, see Figure 9.
Differential Non-Linearity (DNL) is defined as the difference between two adjacent switching steps:
Vi – Vi – 1
DNL ( i ) = ---------------------–1
1 LSB
Eqn. 17
The Integral Non-Linearity (INL) is defined as the sum of all DNLs:
n
INL ( n ) =
Vn – V0
-–n
∑ DNL ( i ) = -----------------1 LSB
Eqn. 18
i=1
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
26
Preliminary
Freescale Semiconductor
Electrical Characteristics
10-bit Absolute Error Boundary
0x3FF
8-bit Absolute Error Boundary
0x3FE
DNL
0x3FD
0xFF
0x3FC
LSB
0x3FB
VI–1
0x3FA
VI
0x3F9
0xFE
0x3F8
0x3F6
0x3F5
0xFD
0x3F4
0x3F3
8-bit Resolution
10-bit Resolution
0x3F7
9
2
8
7
Ideal Transfer Curve
6
5
10-bit Transfer Curve
1
4
3
2
8-bit Transfer Curve
1
VIN
0
0
10
5
20
15
30
25
40 50
35
5055 5065 5075 5085 5095 5105 5115
5060 5070 5080 5090 5100 5110 5120
mV
Figure 9. ATD Accuracy Definitions
NOTE
Figure 9 shows only definitions, for specification values refer to Table 29.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
27
Electrical Characteristics
3.10.3 ATD Timing Specifications
Table 31. ATD External Trigger Timing Specifications
Num C
Parameter
Symbol
T1
D ETRIG Period (Level-Sensitive Trigger Mode)
T2
D ETRIG Minimum Pulse Width
Edge-Sensitive Trigger Mode
Level-Sensitive Trigger Mode
tPW
T3
D ETRIG Level Recovery 2
T4
D Conversion Start Delay
Min
TPERIOD 1 + NCONVn
1
Max
Unit
—
fATDCLK Cycles
fATDCLK Cycles
1
2
—
—
tLR
1
—
fATDCLK Cycles
tDLY
—
2
fATDCLK Cycles
NOTES:
1. NCONVn denotes 8- or 10-bit conversion time (refer to specifications N4, N5, P4 and P5). In order to achieve the
minimum period between conversions when using level-sensitive triggering, ETRIG must remain asserted this long.
2. Time prior to the end of a conversion that ETRIG must be negated in order to prevent the start of another conversion.
T2
Edge Sensitive
Falling Edge Active
ETRIG
Conversion Activity
ANn_x
T4
T4
T2
Level Sensitive
Low Active
ETRIG
Sequence
Complete Flag
ASCIF
Conversion Activity
ANn_x
T4
T4
T1
Level Sensitive
Low Active
ETRIG
T3
Sequence
Complete Flag
ASCIF
Conversion Activity
ANn_x
T4
Figure 10. ATD External Trigger Timing Diagram
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
28
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.11 Serial Peripheral Interface
3.11.1 Master Mode
Master mode timing values are shown in Table 32 and illustrated in Figure 11 and Figure 12.
Table 32. SPI Master Mode Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs
Num C
Rating
Symbol
U1a P Operating Frequency (baud rate)
U1b
U2
U3
U4
U5
U6
U9
U10
U11
U12
P
D
D
D
D
D
D
D
D
D
fOP
SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS)
Enable Lead Time
Enable Lag Time
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Data Valid (after Enable Edge)
Data Hold Time (Outputs)
Rise Time Inputs and Outputs
Fall Time Inputs and Outputs
1
tSCK 1
tlead
tlag
twsck
tsu
thi
tv
tho
tr
tf
Min
1
----------------------------7 × 32, 678
22
½
½
tIPS − 30
25
0
—
0
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
Max
Unit
2
fIPS
½
7 × 32,768
—
—
1024 tIPS
—
—
25
—
25
25
tIPS
tSCK
tSCK
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. Refer to MAC7100 Microcontroller Family Reference Manual (MAC7100RM) Chapter 22 for all available baud rates.
2. On mask set L49P and L47W devices, U1a maximum = ¼ and U1b minimum = 4.
3.11.2 Slave Mode
Slave mode timing values are shown in Table 33 and illustrated in Figure 13 and Figure 14.
Table 33. SPI Slave Mode Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted, CLOAD = 200 pF on all outputs
Num C
Rating
Symbol
V1a P Operating Frequency
V1b
V2
V3
V4
V5
V6
V7
V8
V9
V10
P
D
D
D
D
D
D
D
D
D
Typ
Max
Unit
—
½1
fIPS
tSCK
tlead
tlag
twsck
tsu
thi
ta
tdis
tv
tho
Min
1
----------------------------7 × 32, 678
21
1
1
tIPS − 30
25
25
—
—
—
0
—
—
—
—
—
—
—
—
—
—
7 × 32,768
—
—
—
—
—
1
1
25
—
tIPS
tIPS
tIPS
ns
ns
ns
tIPS
tIPS
ns
ns
tr
tf
—
—
—
—
25
25
ns
ns
fOP
SCK Period (tSCK = 1 ÷ fOP, tIPS = 1 ÷ fIPS)
Enable Lead Time
Enable Lag Time
Clock (SCK) High or Low Time
Data Setup Time (Inputs)
Data Hold Time (Inputs)
Slave Access Time
Slave SIN Disable Time
Data Valid (after SCK Edge)
Data Hold Time (Outputs)
V11 D Rise Time Inputs and Outputs
V12 D Fall Time Inputs and Outputs
NOTES:
1. On mask set L49P and L47W devices, V1a maximum = ¼ and V1b minimum = 4.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
29
Electrical Characteristics
PCSx
(OUTPUT)
U11
U2
U1b
U3
SCK
(CPOL = 0)
(OUTPUT)
U4
U12
U4
SCK
(CPOL = 1)
(OUTPUT)
U5
U6
SIN
(INPUT)
MSB In(2)
Bit 6 ... 1
LSB In
U9
U9
SOUT
(OUTPUT)
MSB Out(2)
U10
Bit 6 ... 1
LSB Out
1. If configured as output.
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 11. SPI Master Timing (CPHA = 0)
PCSx
(OUTPUT)
U2
U11
U1b
U3
U12
SCK
(CPOL = 0)
(OUTPUT)
U4
U11
U12
U4
SCK
(CPOL = 1)
(OUTPUT)
U5
U6
SIN
(INPUT)
MSB In(2)
Bit 6 ... 1
LSB In
U9
U10
SOUT
(OUTPUT)
Port Data
MSB Out(2)
Bit 6 ... 1
Master LSB Out
Port Data
1. If configured as output.
2. LSBFE = 0. For LSBFE = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 12. SPI Master Timing (CPHA = 1)
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
30
Preliminary
Freescale Semiconductor
Electrical Characteristics
SS
(INPUT)
V2
V11
V1b
V12
V3
SCK
(CPOL = 0)
(INPUT)
V4
V11
V4
V12
SCK
(CPOL = 1)
(INPUT)
V7
SOUT
(OUTPUT)
V8
V10
V9
Slave MSB Out
V10
Bit 6 ... 1
Slave LSB Out
V5
V6
SIN
(INPUT)
Bit 6 ... 1
MSB In
LSB In
Figure 13. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
V2
V11
V1b
V12
V3
SCK
(CPOL = 0)
(INPUT)
V4
V11
V12
V4
SCK
(CPOL = 1)
(INPUT)
V9
V8
V10
V7
SOUT
(OUTPUT)
Slave MSB Out
Bit 6 ... 1
Slave LSB Out
V5
V6
SIN
(INPUT)
MSB In
Bit 6 ... 1
LSB In
Figure 14. SPI Slave Timing (CPHA = 1)
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
31
Electrical Characteristics
3.12 FlexCAN Interface
Table 34. FlexCAN Wake-up Pulse Characteristics
Conditions are shown in Table 7 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
W1
P FlexCAN Wake-up dominant pulse filtered
tWUP
—
—
2
μs
W2
P FlexCAN Wake-up dominant pulse passed
tWUP
5
—
—
μs
3.13 Common Flash Module
NOTE
Unless otherwise noted the abbreviation NVM (Non-Volatile Memory) is
used for both program Flash and data Flash.
The time base for all program and data Flash operations, fNVMOP, is derived from the IPS bus clock, fIPS,
using the CFMCLKD register to control the divider ratio. Throughout this section, tIPS refers to 1 ÷ fIPS,
and tNVMOP refers to 1 ÷ fNVMOP. An fNVMOP frequency range limit is imposed for performing program
or erase operations. The CFM does not monitor the frequency and will not prevent program or erase
operation at frequencies above or below the following limits:
150 KHz < f NVMOP ≤ 200 KHz
Eqn. 19
fNVMOP = 200 KHz gives the fastest program and erase performance. Setting CFMCLKD to a value such
that fNVMOP < 150 KHz should be avoided, as this can damage the Flash memory due to overstress. Setting
CFMCLKD to a value such that fNVMOP > 200 KHz can result in incomplete programming or erasure of
the Flash memory array cells.
3.13.1 Mass Erase Timing
The time required to erase the entire NVM array (both program and data) is calculated using the formula:
t mass ≈ 20000 ⋅ t NVMOP
Eqn. 20
The setup time can be ignored for this operation.
3.13.2 Blank Check Timing
The time it takes to perform a blank check on the program or data Flash is dependant on the location of the
first non-blank word, starting from relative address zero. One fIPS cycle is required per word to be verified,
and the time required for the operation is calculated using the formula:
t check = ( locations + 15 ) ⋅ t IPS
Eqn. 21
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
32
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.13.3 Page Erase Timing
The time required to erase a 4 Kbyte program or 1 Kbyte data Flash logical page is calculated using the
formulas:
t erap = 4096 ⋅ t NVMOP + 15 ⋅ t IPS
Eqn. 22
t erad = 1024 ⋅ t NVMOP + 15 ⋅ t IPS
Eqn. 23
3.13.4 Page Erase Verify Timing
The time required to verify that a program Flash page is erased depends on the location of the first
non-blank word. The time required for the operation is calculated using the formula:
4 × 1024
t pevp = ⎛ ----------------------⎞ + 15 × t IPS
⎝
⎠
4
Eqn. 24
The time required to verify that a data Flash page is erased is calculated using the formula:
1 × 1024
t pevd = ⎛ ----------------------⎞ + 15 × t IPS
⎝
⎠
4
Eqn. 25
3.13.5 Programming Timing
Programming time is dependant on the fIPS and fNVMOP frequencies, and is calculated for a single word
using the formula:
t swpgm = 9 ⋅ t NVMOP + 25 ⋅ t IPS
Eqn. 26
Burst programming can be utilized with the program Flash, where up to 32 words in a row can be
programmed consecutively by keeping the command pipeline filled. The time to program a consecutive
word is calculated using the formula:
t bwpgm = 4 ⋅ t NVMOP + 9 ⋅ t IPS
Eqn. 27
Therefore, the time to program a 32-word row is calculated using the formula:
t brpgm = t swpgm + 31 ⋅ t bwpgm
Eqn. 28
Note that burst programming is more than 2 times faster than single word programming.
3.13.6 Data Signature Timing1
The time required to perform a data signature command is dependant on the number of words or
half-words compressed during the operation, and is calculated using the formula:
t dsig = ( Words or Half-Words + 15 ) ⋅ t IPS
Eqn. 29
1. This feature is not available on mask set L49P and L47W devices.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
33
Electrical Characteristics
3.13.7 CFM Timing Specifications
Table 35 lists the time required to execute various operations described in the Section 3.13.1 through
Section 3.13.6. For operating conditions other than those assumed below, Equation 19 through
Equation 29 must be used to calculate the timing for specific commands under those conditions.
Table 35. CFM Timing Characteristics
Conditions are shown in Table 7 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
X1
D System Clock
fNVMfsys
0.5
—
50 1
MHz
X2
D Bus frequency for Programming or Erase Operations
fNVMfips
1
—
—
MHz
X3
D Program/Erase Operating Frequency
fNVMOP
150
—
200
kHz
X4
Time, 2
fSYS = 50 MHz tswpgm
47.1
—
71.0
μs
fSYS = 40 MHz
48.1
—
71.0
fSYS = 50 MHz tbwpgm
20.8
—
30.5
fSYS = 40 MHz
21.3
—
30.5
693.1
—
1,016.5
706.8
—
1,016.5
21.0
—
26.6
21.3
—
26.6
5.2
—
6.7
5.3
—
6.7
100
—
130
ms
16
—
131,087
tIPS
16
—
65,551
tbcheckd
16
—
8,207
tIPS
Program Flash
tpevp
16
—
1,039
tIPS
Data Flash
tpevd
16
—
271
MAC71x6, Program
tdsig
17
—
262,159
MAC71x1, Program
17
—
131,087
MAC71x2, Program
17
—
65,551
MAC71xx, Data
17
—
16,399
X5
X6
P Programming
Single Word
2
D Programming Time,
Consecutive Word Burst
D Programming Time,
32-word Row Burst
2
fSYS = 50 MHz
fSYS = 40 MHz
X7a P Page Erase Time, 2
Program Flash
fSYS = 50 MHz
2
fSYS = 50 MHz
X7b P Page Erase Time,
Data Flash
X8
terap
fSYS = 40 MHz
terad
fSYS = 40 MHz
P Mass Erase Time 2
tmass
X9a D Blank Check Time, 3
Program Flash per Block
MAC71x1, MAC71x6 tbcheckp
MAC71x2
3
X9b D Blank Check Time,
Data Flash per Block
X9c D Page Erase Verify Time 3
X10 D Data Signature
tbrpgm
Time 4
μs
μs
ms
ms
tIPS
NOTES:
1. Subject to restrictions in Table 19 and Table 20 for operating characteristics of the oscillator and PLL.
2. Minimum erase and programming times are achieved with the indicated maximum fSYS (which is fIPS × 2, and subject to the
limits of Table 19 and Table 20) and corresponding maximum fNVMOP. Maximum erase and programming times are
dependent on the combination of fNVMOP and fIPS; values shown are calculated for fIPS = 2 MHz and fNVMOP = 154 KHz.
3. Minimum blank check or page erase verify time assumes the first word in the array is blank and the second is not. Maximum
blank check or page erase verify time assumes the entire block or page is blank.
4. Data signature timing is dependant on the number of words or half-words compressed for the program and data arrays,
respectively. Minimum time is for two words or half-words; maximum time is for the entire array.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
34
Preliminary
Freescale Semiconductor
Electrical Characteristics
3.13.8 NVM Reliability
The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process
monitors and burn-in to screen early life failures. The failure rates for data retention and program/erase
cycling are specified at the operating conditions noted. The program/erase cycle count on the sector is
incremented every time a sector or mass erase event is executed.
Table 36. NVM Reliability Characteristics
Conditions shown in Table 7 unless otherwise noted.
Num
C
Rating
X11
C Program/Data Flash Program/Erase endurance (–40C to +125C)
X12
C Program/Data Flash Data Retention Lifetime
Min
Unit
10,000
Cycles
15
Years
NOTE
All values shown in Table 36 are target values and subject to
characterization. For Flash cycling performance, each program operation
must be preceded by an erase.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
35
Device Pin Assignments
4
Device Pin Assignments
The MAC7100 Family is available in 208-pin ball grid array (MAP BGA), 144-pin low profile quad flat
(LQFP), 112-pin LQFP, and 100-pin LQFP package options. The family of devices offer pin-compatible
packaged devices to assist with system development and accommodate a direct application enhancement
path. Refer to Table 2 for a comparison of the peripheral sets and package options for each device.
Most pins perform two or more functions, which are described in more detail in the MAC7100
Microcontroller Family Reference Manual (MAC7100RM). Table 37, Table 38 and Figure 15 through
Figure 22 show the pin assignments for various devices and packages.
Table 37. Signal Pin Assignments
Primary /
GPIO
Function
EXTAL
XTAL
XFC
RESET
TDI
TDO
TCK
TMS
—
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
Peripheral
Function 1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SDA
SCL
SIN_A
SOUT_A
SCK_A
PCS0_A /
SS_A
PCS1_A
PCS2_A
External
Bus
Function 1
Debug
Function 1
—
—
—
—
—
—
—
—
TA / AS 2
DATA0 3
DATA1 3
DATA2 3
DATA3 3
DATA4 3
DATA5 3
DATA6 3
DATA7 3
DATA8 3
DATA9 3
DATA10 3
DATA11 3
DATA12 3
DATA13 3
DATA14 3
DATA15 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCKO 4
EVTO
EVTI
MDO0
MDO1
MSEO
RDY
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Read on
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PS 3
AA 3
—
—
—
—
—
—
Pin Number (by Device)
7101 7111
7121
7112
7122 7131
7106 7116
7126
60
60
60
48
48 T10
61
61
61
49
49 T11
58
58
58
46
46 T9
48
48
48
36
36 T7
128
128
128
102
102 A8
129
129
129
103
103 B8
130
130
130
104
104 A7
131
131
131
105
105 B7
—
79 —
—
—
M14
138
138
138
106
106 B5
137
137
137 —
—
C5
136
136
136 —
—
A5
135
135
135 —
—
C6
134
134
134 —
—
B6
133
133
133 —
—
A6
132
132
132 —
—
C7
—
98
98
74
74 H15
—
97
97
73
73 H13
—
96
96
72
72 H14
—
95
95
71
71 H16
—
94
94
70
70 J15
—
93
93
69
69 J14
67
67
67
53
53 R12
66
66
66
52
52 T12
65
65
65
51
51 P11
15
15
15
11
11 G1
16
16
16
12
12 H3
17
17
17
13
13 H2
18
18
18
14
14 H1
19
19
19
15
15 J3
20
20
20
16
16 J1
—
—
21
22
21
22
21
22
17
18
17
18
J2
K1
7136
T10
T11
T9
T7
A8
B8
A7
B7
M14
B5
C5
A5
C6
B6
A6
C7
H15
H13
H14
H16
J15
J14
R12
T12
P11
G1
H3
H2
H1
J3
J1
J2
K1
7141
7142
45
46
43
33
93
94
95
96
—
—
—
—
—
—
—
—
65
64
63
—
—
—
—
—
48
8
9
10
11
12
13
14
15
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
36
Preliminary
Freescale Semiconductor
Device Pin Assignments
Table 37. Signal Pin Assignments (continued)
Primary /
GPIO
Function
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PD0
PD1
PD2 6
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
PE1
Peripheral
Function 1
PCS5_A /
PCSS_A
PCS0_B /
SS_B
PCS5_B /
PCSS_B
PCS2_B
PCS1_B
SCK_B
SOUT_B
SIN_B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XIRQ
IRQ
—
—
—
—
—
—
—
—
—
—
—
AN0_A
AN1_A
Pin Number (by Device)
7101 7111
7121
7112
7122 7131
7106 7116
7126
23
23
23
19
19 K2
External
Bus
Function 1
Debug
Function 1
Read on
Reset
—
—
—
—
—
—
72
72
72
56
—
—
—
73
73
73
57 5
—
—
—
—
—
ADDR0 3
ADDR1 3
ADDR2 3
ADDR3 3
ADDR4 3
ADDR5 3
ADDR6 3
ADDR7 3
ADDR8 3
ADDR9 3
ADDR10 3
ADDR11 3
ADDR12 3
ADDR13 3
ADDR14 3
ADDR15 3
BS0 3
BS1 3
CLKOUT
—
—
ADDR16 3
ADDR17 3
ADDR18 3
ADDR19 3
ADDR20 3
ADDR21 3
OE 3
CS2 3
CS1 3
CS0 3
R/W 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MCKO'
EVTO'
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MODB
MODA
XCLKS
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
74
75
76
77
78
9
10
11
12
28
29
30
31
44
45
46
47
—
—
—
—
70
71
80
81
82
—
—
—
—
—
—
68
69
83
84
85
89
91
74
75
76
77
78
9
10
11
12
28
29
30
31
44
45
46
47
88
89
90
91
70
71
80
81
82
92
119
120
121
122
123
68
69
83
84
85
99
100
74
75
76
77
78
9
10
11
12
28
29
30
31
44
45
46
47
88
89
90
91
70
71
80
81
82
92
119
120
121
122
123
68
69
83
84
85
99
100
—5
58
59
60
61
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
67
54
55
62
63
64
68
95
96
97
98
99
—
—
—
—
—
75
76
K2
7141
7142
16
56 T14
T14
51
57 R14
R14
52
N14
P15
P16
N15
N16
F1
F3
G2
G3
L3
M2
M3
N3
P5
R6
P6
T6
K14
K13
K15
J16
T13
R13
M16
M15
L16
J13
C10
D10
D9
B9
D8
P12
P13
L13
L14
L15
G16
G15
53
54
55
56
57
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
49
50
58
59
60
—
86
87
88
89
90
—
—
—
—
—
66
67
—
58
59
60
61
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
67
54
55
62
63
64
68
95
96
97
98
99
—
—
—
—
—
75
76
N14
P15
P16
N15
N16
F1
F3
G2
G3
L3
M2
M3
N3
P5
R6
P6
T6
K14
K13
K15
J16
T13
R13
M16
M15
L16
J13
C10
D10
D9
B9
D8
P12
P13
L13
L14
L15
G16
G15
7136
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
37
Device Pin Assignments
Table 37. Signal Pin Assignments (continued)
Primary /
GPIO
Function
Peripheral
Function 1
External
Bus
Function 1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
AN2_A
AN3_A
AN4_A
AN5_A
AN6_A
AN7_A
AN8_A
AN9_A
AN10_A
AN11_A
AN12_A
AN13_A
AN14_A
AN15_A
eMIOS0
eMIOS1
eMIOS2
eMIOS3
eMIOS4
eMIOS5
eMIOS6
eMIOS7
eMIOS8
eMIOS9
eMIOS10
eMIOS11
eMIOS12
eMIOS13
eMIOS14
eMIOS15
RXD_B
TXD_B
RXD_A
TXD_A
CNTX_A
CNRX_A
CNTX_B
CNRX_B
CNTX_C 8
CNRX_C 8
CNTX_D 8
CNRX_D 8
RXD_D 8
TXD_D 8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Debug
Function 1
Read on
Reset
EVTI'
MDO0'
MDO1'
MSEO'
RDY'
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
NEXPS
NEXPR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
Debug Status 7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin Number (by Device)
7101 7111
7121
7112
7122 7131
7106 7116
7126
93
101
101
77
77 F13
95
102
102
78
78 F14
97
103
103
79
79 E13
99
104
104
80
80 E14
101
105
105
81
81 D15
103
106
106
82
82 C15
105
107
107
83
83 C14
107
108
108
84
84 D14
113
113
113
89
89 B13
115
114
114
90
90 C12
117
115
115
91
91 A12
119
116
116
92
92 B11
121
117
117
93
93 A10
123
118
118
94
94 A9
43
43
43
35
35 T5
42
42
42
34
34 R5
41
41
41
33
33 T4
40
40
40
32
32 R4
39
39
39
31
31 T3
38
38
38
30
30 P4
37
37
37
29
29 R3
36
36
36
28
28 R1
35
35
35
27
27 P2
34
34
34
26
26 P1
33
33
33
25
25 N2
32
32
32
24
24 N1
27
27
27
23
23 M1
26
26
26
22
22 L2
25
25
25
21
21 L1
24
24
24
20
20 K3
141
141
141
109
109 A3
142
142
142
110
110 C4
143
143
143
111
111 B3
144
144
144
112
112 C2
1
1
1
1
1 D3
2
2
2
2
2 C1
7
7
7
7
7 E1
8
8
8
8
8 F2
3
3
3
3
3 D2
4
4
4
4
4 D1
5
5
5
5
5 E3
6
6
6
6
6 E2
51
51
51
39
39 R7
52
52
52
40
40 R8
7136
F13
F14
E13
E14
D15
C15
C14
D14
B13
C12
A12
B11
A10
A9
T5
R5
T4
R4
T3
P4
R3
R1
P2
P1
N2
N1
M1
L2
L1
K3
A3
C4
B3
C2
D3
C1
E1
F2
D2
D1
E3
E2
R7
R8
7141
7142
68
69
70
71
72
73
74
75
80
81
82
83
84
85
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
97
98
99
100
1
2
3
4
—
—
—
—
36
37
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
38
Preliminary
Freescale Semiconductor
Device Pin Assignments
Table 37. Signal Pin Assignments (continued)
Primary /
GPIO
Function
PG14
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PH14
PH15
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
PI9
PI10
PI11
PI12
PI13
PI14
PI15
NOTES:
Peripheral
Function 1
External
Bus
Function 1
Debug
Function 1
Read on
Reset
RXD_C
TXD_C
AN0_B
AN1_B
AN2_B
AN3_B
AN4_B
AN5_B
AN6_B
AN7_B
AN8_B
AN9_B
AN10_B
AN11_B
AN12_B
AN13_B
AN14_B
AN15_B
PCS3_A
PCS4_A
PCS6_A
PCS7_A
PCS3_B
PCS4_B
PCS6_B
PCS7_B
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Pin Number (by Device)
7101 7111
7121
7112
7122 7131
7106 7116
7126
139
139
139
107
107 A4
140
140
140
108
108 B4
88 —
—
—
—
G13
90 —
—
—
—
G14
92 —
—
—
—
F16
94 —
—
—
—
F15
96 —
—
—
—
E16
98 —
—
—
—
E15
100 —
—
—
—
D16
102 —
—
—
—
C16
104 —
—
—
—
B16
106 —
—
—
—
B14
108 —
—
—
—
D13
114 —
—
—
—
A13
116 —
—
—
—
B12
118 —
—
—
—
C11
120 —
—
—
—
A11
122 —
—
—
—
B10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
7136
A4
B4
G13
G14
F16
F15
E16
E15
D16
C16
B16
B14
D13
A13
B12
C11
A11
B10
C3
D5
D4
E4
G4
J4
K4
L4
N4
P3
R2
R15
N11
N12
N13
P14
7141
7142
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1. The MAC7100 family maximum peripheral configurations are listed in these columns. Some family members do not implement the full
complement of ATD, CAN, DSPI and eSCI peripherals. Refer to Table 2 on page 3 for availability of peripheral functions on various devices.
2. AS function not available on mask set L49P devices.
3. MAC7111, MAC7116, MAC7131 and MAC7136 only.
4. The MCKO function cannot be used on MAC7121 devices (the alternate Nexus port must be used).
5. On MAC7121 mask set L49P devices, PB11 / PCS2_B is bonded out on pin 57.
6. PD2 function not available on mask set L49P devices.
7. Optional debug status port not available on mask set L49P devices.
8. CAN C, CAN D and eSCI D not available on MAC7112, MAC7122 and MAC7142 devices.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
39
Device Pin Assignments
Table 38. Power Supply, Voltage Regulator and Reference Pin Assignments
Pin Number (by Device)
Pin Name
7101 / 7106 /
7111 / 7112 / 7116
7121 / 7122 / 7126
7131 / 7136
7141 / 7142
VDDX
14, 50, 64, 87, 124
10, 38, 66
C9, H4, K16, P7, P10
6, 35, 62
VSSX
13, 49, 63, 86, 125
9, 37, 65
A1, A2, B1, B2, F4, G7,
G8, G9, G10, H7, H8, H9,
H10, J7, J8, J9, J10, K7,
K8, K9, K10, M4, M13,
R9, R10, R16, T1, T2,
T15, T16
5, 34, 61
7101 / 7106 / 7112 only:
79
7131 only:
C3, D4, D5, E4, G4, J4,
K4, L4, N4, N11, N12,
N13, P3, P14, R9, R10
VDDR
56
44
P9
41
VSSR
55
43
N5, N6
40
VDD2.5
53, 127
41, 101
C8, P8
38, 92
VSS2.5
54, 126
42, 100
D6, D7, N7, N8
39, 91
VDDPLL
57
45
T8
42
VSSPLL
59
47
N9, N10
44
VDDA
109
85
A16, B15, C13
76
VSSA
112
88
D11, D12
79
VRH
110
86
A15
77
111
87
A14
78
62
50
R11
47
—
—
—
7
VRL
TEST
N/C
1
NOTES:
1. This pin is reserved for Freescale factory testing, and must be tied to system ground in all applications.
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
40
Preliminary
Freescale Semiconductor
Device Pin Assignments
MAC7141 Pin Diagram
SDA
SCL
SIN_A
SOUT_A
SCK_A
SS_A
/ PCS0_A
PCS1_A
PCS2_A
PCSS_A / PCS5_A
eMIOS15
eMIOS14
eMIOS13
eMIOS12
eMIOS11
eMIOS10
eMIOS9
eMIOS8
eMIOS7
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
PG4
PG5
PG6
PG7
VSSX
VDDX
N/C
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PF15
PF14
PF13
PF12
PF11
PF10
PF9
PF8
PF7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MAC7141
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
/
/
/
/
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
PA8
PA9
VDDX
VSSX
PD4 / IRQ
PD3 / XIRQ
PD2(1) / CLKOUT/ XCLKS
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
PB9 / PCS0_B / SS_B
eMIOS6 / PF6
eMIOS5 / PF5
eMIOS4 / PF4
eMIOS3 / PF3
eMIOS2 / PF2
NEXPR / eMIOS1 / PF1
NEXPS / eMIOS0 / PF0
RESET
VSSX
VDDX
RXD_D / PG12
TXD_D / PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PA15
MODB / PD0
MODA / PD1
CNTX_A
CNRX_A
CNTX_B
CNRX_B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
PD10
PD9
PD8
PD7
PD6
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.1
1. PD2 function not available on L49P mask set devices.
Figure 15. Pin Assignments for MAC7141 in 100-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
41
Device Pin Assignments
MAC7142 Pin Diagram
SDA
SCL
SIN_A
SOUT_A
SCK_A
SS_A
/ PCS0_A
PCS1_A
PCS2_A
PCSS_A / PCS5_A
eMIOS15
eMIOS14
eMIOS13
eMIOS12
eMIOS11
eMIOS10
eMIOS9
eMIOS8
eMIOS7
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
PG4
PG5
PG6
PG7
VSSX
VDDX
N/C
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PF15
PF14
PF13
PF12
PF11
PF10
PF9
PF8
PF7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MAC7142
100 LQFP
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
/
/
/
/
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PA7
PA8
PA9
VDDX
VSSX
PD4
PD3
PD2
PB15
PB14
PB13
PB12
PB11
PB10
PB9
/ AN9_A
/ AN8_A
/ AN7_A
/ AN6_A
/ AN5_A
/ AN4_A
/ AN3_A
/ AN2_A
/ AN1_A
/ AN0_A
/ RDY'
/ MSEO'
/ MDO1'
/ MDO0'
/ EVTI'
/ EVTO'
/ MCKO'
/ IRQ
/ XIRQ
/ CLKOUT/ XCLKS
/ SIN_B
/ SOUT_B
/ SCK_B
/ PCS1_B
/ PCS2_B
/ PCS5_B / PCSS_B
/ PCS0_B / SS_B
eMIOS6 / PF6
eMIOS5 / PF5
eMIOS4 / PF4
eMIOS3 / PF3
eMIOS2 / PF2
NEXPR / eMIOS1 / PF1
NEXPS / eMIOS0 / PF0
RESET
VSSX
VDDX
PG12
PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PA15
MODB / PD0
MODA / PD1
CNTX_A
CNRX_A
CNTX_B
CNRX_B
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
PD10
PD9
PD8
PD7
PD6
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.2
Figure 16. Pin Assignments for MAC7142 in 100-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
42
Preliminary
Freescale Semiconductor
Device Pin Assignments
MAC7121 / MAC7126 Pin Diagram
PG4
PG5
PG8
PG9
PG10
PG11
PG6
PG7
VSSX
VDDX
/ PB0
/ PB1
/ PB2
/ PB3
/ PB4
/ PB5
/ PB6
/ PB7
/ PB8
/ PF15
/ PF14
/ PF13
/ PF12
/ PF11
/ PF10
/ PF9
/ PF8
/ PF7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MAC7121 / MAC7126
112 LQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
PA8
PA9
PA10
PA11
PA12
PD5
PC15
VDDX
VSSX
PD4 / IRQ
PD3 / XIRQ
PD2(1)/ CLKOUT/ XCLKS
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB10 / PCS5_B / PCSS_B(2)
eMIOS6 / PF6
eMIOS5 / PF5
eMIOS4 / PF4
eMIOS3 / PF3
eMIOS2 / PF2
NEXPR / eMIOS1 / PF1
NEXPS / eMIOS0 / PF0
RESET
VSSX
VDDX
RXD_D / PG12
TXD_D / PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PA15
PA14
PA13
MODB / PD0
MODA / PD1
SS_B / PCS0_B / PB9
SDA
SCL
SIN_A
SOUT_A
SCK_A
SS_A
/ PCS0
PCS1_A
PCS2_A
PCSS_A / PCS5_A
eMIOS15
eMIOS14
eMIOS13
eMIOS12
eMIOS11
eMIOS10
eMIOS9
eMIOS8
eMIOS7
/
/
/
/
/
/
/
/
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
CNTX_A
CNRX_A
CNTX_C
CNRX_C
CNTX_D
CNRX_D
CNTX_B
CNRX_B
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
PG15 / TXD_C
PG14 / RXD_C
PA0
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
PD10
PD9
PD8
PD7
PD6
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.3
1. PD2 function not available on L49P mask set devices.
2 On L49P mask set devices, PB11 / PCS2_B is bonded out on pin 57.
Figure 17. Pin Assignments for MAC7121 / MAC7126 in 112-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
43
Device Pin Assignments
MAC7122 Pin Diagram
MAC7122
112 LQFP
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PE9
PE8
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PA7
PA8
PA9
PA10
PA11
PA12
PD5
PC15
VDDX
VSSX
PD4
PD3
PD2
PB15
PB14
PB13
PB12
PB10
/ AN9_A
/ AN8_A
/ AN7_A
/ AN6_A
/ AN5_A
/ AN4_A
/ AN3_A
/ AN2_A
/ AN1_A
/ AN0_A
/ RDY'
/ MSEO'
/ MDO1'
/ MDO0'
/ EVTI'
/ EVTO'
/ MCKO'
/ IRQ
/ XIRQ
/ CLKOUT/ XCLKS
/ SIN_B
/ SOUT_B
/ SCK_B
/ PCS1_B
/ PCS5_B / PCSS_B
eMIOS6 / PF6
eMIOS5 / PF5
eMIOS4 / PF4
eMIOS3 / PF3
eMIOS2 / PF2
NEXPR / eMIOS1 / PF1
NEXPS / eMIOS0 / PF0
RESET
VSSX
VDDX
PG12
PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
PA15
PA14
PA13
MODB / PD0
MODA / PD1
SS_B / PCS0_B / PB9
CNTX_A / PG4
CNRX_A / PG5
PG8
PG9
PG10
PG11
CNTX_B / PG6
CNRX_B / PG7
VSSX
VDDX
SDA
/ PB0
SCL
/ PB1
SIN_A
/ PB2
SOUT_A / PB3
SCK_A / PB4
SS_A
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
PCSS_A / PCS5_A / PB8
eMIOS15 / PF15
eMIOS14 / PF14
eMIOS13 / PF13
eMIOS12 / PF12
eMIOS11 / PF11
eMIOS10 / PF10
eMIOS9 / PF9
eMIOS8 / PF8
eMIOS7 / PF7
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
PG15 / TXD_C
PG14 / RXD_C
PA0
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
PD10
PD9
PD8
PD7
PD6
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.4
Figure 18. Pin Assignments for MAC7122 in 112-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
44
Preliminary
Freescale Semiconductor
Device Pin Assignments
MAC7101 / MAC7106 Pin Diagram
SDA
SCL
SIN_A
SOUT_A
SCK_A
SS_A / PCS0_A
PCS1_A
PCS2_A
PCSS_A / PCS5_A
eMIOS15
eMIOS14
eMIOS13
eMIOS12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MAC7101 / MAC7106
144 LQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
PH10 / AN10_B
PE9 / AN9_A
PH9 / AN9_B
PE8 / AN8_A
PH8 / AN8_B
PE7 / AN7_A
PH7 / AN7_B
PE6 / AN6_A / RDY'
PH6 / AN6_B
PE5 / AN5_A / MSEO'
PH5 / AN5_B
PE4 / AN4_A / MDO1'
PH4 / AN4_B
PE3 / AN3_A / MDO0'
PH3 / AN3_B
PE2 / AN2_A / EVTI'
PH2 / AN2_B
PE1 / AN1_A / EVTO'
PH1 / AN1_B
PE0 / AN0_A / MCKO'
PH0 / AN0_B
VDDX
VSSX
PD15
PD14
PD13
PD4 / IRQ
PD3 / XIRQ
PD2(1)/ CLKOUT / XCLKS
VSSX
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
eMIOS6
eMIOS5
eMIOS4
eMIOS3
eMIOS2
NEXPR / eMIOS1
NEXPS / eMIOS0
/ PF6
/ PF5
/ PF4
/ PF3
/ PF2
/ PF1
/ PF0
PC8
PC9
PC10
PC11
RESET
VSSX
VDDX
RXD_D / PG12
TXD_D / PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
VSSX
VDDX
PA15
PA14
PA13
PD11
PD12
MODB / PD0
MODA / PD1
SS_B / PCS0_B / PB9
eMIOS11
eMIOS10
eMIOS9
eMIOS8
eMIOS7
/ PG4
/ PG5
/ PG8
/ PG9
/ PG10
/ PG11
/ PG6
/ PG7
PC0
PC1
PC2
PC3
VSSX
VDDX
/ PB0
/ PB1
/ PB2
/ PB3
/ PB4
/ PB5
/ PB6
/ PB7
/ PB8
/ PF15
/ PF14
/ PF13
/ PF12
PC4
PC5
PC6
PC7
/ PF11
/ PF10
/ PF9
/ PF8
/ PF7
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
CNTX_A
CNRX_A
CNTX_C
CNRX_C
CNTX_D
CNRX_D
CNTX_B
CNRX_B
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
PG15 / TXD_C
PG14 / RXD_C
PA0 / MCKO
PA1 / EVTO
PA2 / EVTI
PA3 / MDO0
PA4 / MDO1
PA5 / MSEO
PA6 / RDY
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
VSSX
VDDX
PE15 / AN15_A
PH15 / AN15_B
PE14 / AN14_A
PH14 / AN14_B
PE13 / AN13_A
PH13 / AN13_B
PE12 / AN12_A
PH12 / AN12_B
PE11 / AN11_A
PH11 / AN11_B
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.5
1. PD2 function not available on L49P mask set devices.
Figure 19. Pin Assignments for MAC7101 / MAC7106 in 144-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
45
Device Pin Assignments
MAC7111 / MAC7116 Pin Diagram
MAC7111 / MAC7116
144 LQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7 / DATA7
PA8 / DATA8
PA9 / DATA9
PA10 / DATA10
PA11 / DATA11
PA12 / DATA12
PD5 / ADDR16
PC15 / ADDR15
PC14 / ADDR14
PC13 / ADDR13
PC12 / ADDR12
VDDX
VSSX
PD15 / R/W
PD14 / CS0
PD13 / CS1
PD4 / IRQ
PD3 / XIRQ
PD2(1)/ CLKOUT/ XCLKS
TA / AS
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
eMIOS6 / PF6
eMIOS5 / PF5
eMIOS4 / PF4
eMIOS3 / PF3
eMIOS2 / PF2
NEXPR / eMIOS1 / PF1
NEXPS / eMIOS0 / PF0
ADDR8 / PC8
ADDR9 / PC9
ADDR10 / PC10
ADDR11 / PC11
RESET
VSSX
VDDX
RXD_D / PG12
TXD_D / PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
VSSX
VDDX
DATA15 / PA15
DATA14 / PA14
DATA13 / PA13
OE
/ PD11
/ PD12
CS2
/ PD0
MODB BS0
/ PD1
MODA BS1
SS_B / PCS0_B / PB9
CNTX_A / PG4
CNRX_A / PG5
CNTX_C / PG8
CNRX_C / PG9
CNTX_D / PG10
CNRX_D / PG11
CNTX_B / PG6
CNRX_B / PG7
ADDR0 / PC0
ADDR1 / PC1
ADDR2 / PC2
ADDR3 / PC3
VSSX
VDDX
SDA
/ PB0
SCL
/ PB1
SIN_A / PB2
SOUT_A / PB3
SCK_A / PB4
SS_A
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
PCSS_A / PCS5_A / PB8
eMIOS15 / PF15
eMIOS14 / PF14
eMIOS13 / PF13
eMIOS12 / PF12
ADDR4 / PC4
ADDR5 / PC5
ADDR6 / PC6
ADDR7 / PC7
eMIOS11 / PF11
eMIOS10 / PF10
eMIOS9 / PF9
eMIOS8 / PF8
eMIOS7 / PF7
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
PG15 / TXD_C
PG14 / RXD_C
PA0 / DATA0 / MCKO
PA1 / DATA1 / EVTO
PA2 / DATA2 / EVTI
PA3 / DATA3 / MDO0
PA4 / DATA4 / MDO1
PA5 / DATA5 / MSEO
PA6 / DATA6 / RDY
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
VSSX
VDDX
PD10 / ADDR21
PD9 / ADDR20
PD8 / ADDR19
PD7 / ADDR18
PD6 / ADDR17
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.6
1. PD2 function not available on L49P mask set devices.
Figure 20. Pin Assignments for MAC7111 / MAC7116 in 144-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
46
Preliminary
Freescale Semiconductor
Device Pin Assignments
MAC7112 Pin Diagram
MAC7112
144 LQFP
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PE9 / AN9_A
PE8 / AN8_A
PE7 / AN7_A
PE6 / AN6_A / RDY'
PE5 / AN5_A / MSEO'
PE4 / AN4_A / MDO1'
PE3 / AN3_A / MDO0'
PE2 / AN2_A / EVTI'
PE1 / AN1_A / EVTO'
PE0 / AN0_A / MCKO'
PA7
PA8
PA9
PA10
PA11
PA12
PD5
PC15
PC14
PC13
PC12
VDDX
VSSX
PD15
PD14
PD13
PD4 / IRQ
PD3 / XIRQ
PD2 / CLKOUT/ XCLKS
VSSX
PB15 / SIN_B
PB14 / SOUT_B
PB13 / SCK_B
PB12 / PCS1_B
PB11 / PCS2_B
PB10 / PCS5_B / PCSS_B
eMIOS6
eMIOS5
eMIOS4
eMIOS3
eMIOS2
NEXPR / eMIOS1
NEXPS / eMIOS0
/ PF6
/ PF5
/ PF4
/ PF3
/ PF2
/ PF1
/ PF0
PC8
PC9
PC10
PC11
RESET
VSSX
VDDX
PG12
PG13
VDD2.5
VSS2.5
VSSR
VDDR
VDDPLL
XFC
VSSPLL
EXTAL
XTAL
TEST
VSSX
VDDX
PA15
PA14
PA13
PD11
PD12
MODB / PD0
MODA / PD1
SS_B / PCS0_B / PB9
CNTX_A / PG4
CNRX_A / PG5
PG8
PG9
PG10
PG11
CNTX_B / PG6
CNRX_B / PG7
PC0
PC1
PC2
PC3
VSSX
VDDX
SDA
/ PB0
SCL
/ PB1
SIN_A / PB2
SOUT_A / PB3
SCK_A / PB4
SS_A
/ PCS0_A / PB5
PCS1_A / PB6
PCS2_A / PB7
PCSS_A / PCS5_A / PB8
eMIOS15 / PF15
eMIOS14 / PF14
eMIOS13 / PF13
eMIOS12 / PF12
PC4
PC5
PC6
PC7
eMIOS11 / PF11
eMIOS10 / PF10
eMIOS9 / PF9
eMIOS8 / PF8
eMIOS7 / PF7
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
PG3 / TXD_A
PG2 / RXD_A
PG1 / TXD_B
PG0 / RXD_B
PG15 / TXD_C
PG14 / RXD_C
PA0 / MCKO
PA1 / EVTO
PA2 / EVTI
PA3 / MDO0
PA4 / MDO1
PA5 / MSEO
PA6 / RDY
TMS
TCK
TDO
TDI
VDD2.5
VSS2.5
VSSX
VDDX
PD10
PD9
PD8
PD7
PD6
PE15 / AN15_A
PE14 / AN14_A
PE13 / AN13_A
PE12 / AN12_A
PE11 / AN11_A
PE10 / AN10_A
VSSA
VRL
VRH
VDDA
4.7
Figure 21. Pin Assignments for MAC7112 in 144-pin LQFP
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
47
Device Pin Assignments
4.8
MAC7131 Pin Diagram
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSSX
VSSX
PG0
PG14
PA2
PA5
TCK
TDI
PE15
PE14
PH14
PE12
PH11
VRL
VRH
VDDA
VSSX
VSSX
PG2
PG15
PA0
PA4
TMS
TDO
PD9
PH15
PE13
PH12
PE10
PH9
VDDA
PH8
PG5
PG3
VSSX
PG1
PA1
PA3
PA6
VDD2.5 VDDX
PD6
PH13
PE11
VDDA
PE8
PE7
PH7
PG9
PG8
PG4
VSSX
VSSX VSS2.5 VSS2.5 PD10
PD7
VSSA
VSSA
PH10
PE9
PE6
PH6
PG6
PG11
PG10
VSSX
PE4
PE5
PH5
PH4
PC0
PG7
PC1
VSSX
PE2
PE3
PH3
PH2
PB0
PC2
PC3
VSSX
VSSX
VSSX
VSSX
VSSX
PH0
PH1
PE1
PE0
PB3
PB2
PB1
VDDX
VSSX
VSSX
VSSX
VSSX
PA8
PA9
PA7
PA10
PB5
PB6
PB4
VSSX
VSSX
VSSX
VSSX
VSSX
PD5
PA12
PA11
PC15
PB7
PB8
PF15
VSSX
VSSX
VSSX
VSSX
VSSX
PC13
PC12
PC14
VDDX
PF14
PF13
PC4
VSSX
PD13
PD14
PD15
PD4
PF12
PC5
PC6
VSSX
VSSX TA/AS(1) PD3
PD2(1)
PF11
PF10
PC7
VSSX
VSSR
VSSR VSS2.5 VSS2.5 VSSPLL VSSPLL VSSX
VSSX
VSSX
PB11
PB14
PB15
PF9
PF8
VSSX
PF5
PC8
PC10
VDDX VDD2.5 VDDR
VDDX
PA15
PD11
PD12
VSSX
PB12
PB13
PF7
VSSX
PF6
PF3
PF1
PC9
PG12
VSSX
TEST
PA13
PD1
PB10
VSSX
VSSX
VSSX
VSSX
PF4
PF2
PF0
PC11 RESET VDDPLL XFC
EXTAL XTAL
PA14
PD0
PB9
VSSX
VSSX
PG13
PD8
VSSX
1. AS and PD2 functions not available on L49P mask set devices.
Figure 22. Pin Assignments for MAC7131 in 208-pin MAP BGA
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
48
Preliminary
Freescale Semiconductor
Device Pin Assignments
4.9
MAC7136 Pin Diagram
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSSX
VSSX
PG0
PG14
PA2
PA5
TCK
TDI
PE15
PE14
PH14
PE12
PH11
VRL
VRH
VDDA
VSSX
VSSX
PG2
PG15
PA0
PA4
TMS
TDO
PD9
PH15
PE13
PH12
PE10
PH9
VDDA
PH8
PG5
PG3
PI0
PG1
PA1
PA3
PA6
VDD2.5 VDDX
PD6
PH13
PE11
VDDA
PE8
PE7
PH7
PG9
PG8
PG4
PI2
PI1
PD7
VSSA
VSSA
PH10
PE9
PE6
PH6
PG6
PG11
PG10
PI3
PE4
PE5
PH5
PH4
PC0
PG7
PC1
VSSX
PE2
PE3
PH3
PH2
PB0
PC2
PC3
PI4
VSSX
VSSX
VSSX
VSSX
PH0
PH1
PE1
PE0
PB3
PB2
PB1
VDDX
VSSX
VSSX
VSSX
VSSX
PA8
PA9
PA7
PA10
PB5
PB6
PB4
PI5
VSSX
VSSX
VSSX
VSSX
PD5
PA12
PA11
PC15
PB7
PB8
PF15
PI6
VSSX
VSSX
VSSX
VSSX
PC13
PC12
PC14
VDDX
PF14
PF13
PC4
PI7
PD13
PD14
PD15
PD4
PF12
PC5
PC6
VSSX
VSSX TA / AS PD3
PD2
PF11
PF10
PC7
PI8
VSSR
VSSR VSS2.5 VSS2.5 VSSPLL VSSPLL PI12
PI13
PI14
PB11
PB14
PB15
PF9
PF8
PI9
PF5
PC8
PC10
VDDX VDD2.5 VDDR
VDDX
PA15
PD11
PD12
PI15
PB12
PB13
PF7
PI10
PF6
PF3
PF1
PC9
PG12
VSSX
TEST
PA13
PD1
PB10
PI11
VSSX
VSSX
VSSX
PF4
PF2
PF0
PC11 RESET VDDPLL XFC
EXTAL XTAL
PA14
PD0
PB9
VSSX
VSSX
VSS2.5 VSS2.5 PD10
PG13
PD8
VSSX
Figure 23. Pin Assignments for MAC7136 in 208-pin MAP BGA
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
49
Mechanical Information
5
Mechanical Information
As indicated in Table 2, MAC7100 Family devices are available in several packages. Please refer to the
freescale.com web site for the most up-to-date package availability and mechanical information. The table
below lists available package identifiers and Freescale document numbers for reference.
Table 39. Package Identifiers and Mechanical Specifications
Package Type
Case Identifier
Mechanical Specification
Document
100-lead LQFP
983-02
98ASS23308W
112-lead LQFP
987-02
98ASS23330W
144-lead LQFP
918-03
98ASS23177W
208-lead MAP BGA
1159A-01
98ARS23882W
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
50
Preliminary
Freescale Semiconductor
Mechanical Information
Revision History
Revision History
Version No.
Release Date
Page
Numbers
Description of Changes
v0.1
29-Oct-03
First public customer release (preliminary).
v1.0
14-Sep-04
General
• Converted to Freescale identity, with blue cross-reference highlights for enhanced PDF
navigation, and miscellaneous updates for presentation consistency.
• The order of Section 3.5 and Section 3.6 were reversed for better content flow. This has
caused specification numbering to change as detailed below.
7, 8
Note: Content consolidation and reorganization has resulted in the following table and
specification number changes (the first spec number of each table is shown):
Table Title
Rev. 1.0
5.0 V I/O Characteristics
3.3 V I/O Characteristics
Section 3.6, “Power Dissipation and Thermal Characteristics”
MAC71x1/6 Device Supply Current Characteristics – 40 MHz
MAC71x1/6 Device Supply Current Characteristics – 50 MHz
VREG Operating Conditions
VREG Recommended Load Capacitances
Oscillator Characteristics
PLL Characteristics
Crystal Monitor Time-Outs
CRG Maximum Clock Quality Check Timings
CRG Startup Characteristics
External Bus Input Timing Specifications
External Bus Output Timing Specifications
ATD Operating Characteristics in 5.0 V Range
ATD Operating Characteristics in 3.3 V Range
ATD Electrical Characteristics
ATD Conversion Performance in 5.0 V Range
ATD Conversion Performance in 3.3 V Range
ATD Electrical Characteristics (Operating)
ATD Performance Specifications
ATD Timing Specifications
ATD External Trigger Timing Specifications
SPI Master Mode Timing Characteristics
SPI Slave Mode Timing Characteristics
FlexCAN Wake-up Pulse Characteristics
CFM Timing Characteristics
NVM Reliability Characteristics
Table 8
D1a
Table 9
E1a
Table 10 to
Table 14
Table 15 F1
Table 16 G1
Table 17 H1
Table 18
Table 19 J1a
Table 20 K1
Table 21
Table 22
Table 23 L1
Table 24 M1
Table 25 M6a
Table 26 N1
Table 27 P1
Table 28 Q1
Table 29 R1
Table 30 S1
N/A
N/A
N/A
Table 31 T1
Table 32 U1a
Table 33 V1a
Table 34 W1
Table 35 X1
Table 36 X9b
Rev. 0.1
Table 15
Table 16
Table 7 to
Table 11
Table 12
N/A
Table 13
Table 14
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
F1
G1
D1a
E1
H1a
J1
K1
L1
L6a
M1
N1
P1
Q1
R1
S1
T1
U1
V1
W1a
X1a
Y1
Z1
Z10
Section 2, “Ordering Information”
• Added Table 1, mask set information
• Updated Table 2 with expanded port pin counts, MAC71x2 and MAC71x6 family members
• Pin assignment changes for mask set L47W devices:
— In Table 37, PB10 / PCS5_B / PCSS_B changed to pin 57, footnote for L49P
2
3
36
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
51
Mechanical Information
Revision History (continued)
Version No.
Release Date
v1.0
14-Sep-04
(continued)
Page
Numbers
Description of Changes
Section 3, “Electrical Characteristics”
• Section 3.2, “Absolute Maximum Ratings”
— A1a renamed to VDDX
— A4 “rating” changed to Analog (from ATD)
— A9 minimum changed to –0.3
— A12 maximum value removed, footnote reference added
— Table 8, Table 9 footnotes added regarding VDD5/VSS5
• Section 3.4, “Operating Conditions”
— C1 renamed to VDDX
— C4 added (C5 to C11b renumbered)
— C8 maximum changed from 40 MHz to 50 MHz
• Section 3.5, “Input/Output Characteristics”
— Table 8 spec D4 updated (from TBD)
— Table 9 spec E4 changed to 1 μA to match D4
• Section 3.6, “Power Dissipation and Thermal Characteristics”
— Reworked Equation 1 through Equation 4 and supporting text
— Section 3.6.1 and Table 10 name changed from “Power Dissipation...”
• Section 3.7, “Power Supply”
— Added MAC71x1 designation and footnotes to Table 15 / Table 16
— Table 15 designated for 40 MHz, and
– Numerous TBD entries replaced with values
– Run Supply Current collapsed from fifteen spec items to one
– Removed separate Core/Regulator/Pins specs for Run/Pseudo Stop/Stop modes
– F1 and F3 descriptions changed
– F1, F2, F3 and F4 values updated
— Table 16 added for 50 MHz specifications
— Table 17, deleted IREG spec (Regulator Current in Reduced Power, Shutdown Modes)
— Table 18, VDD2.5 load capacitance typical changed, with clarification footnote
• Section 3.8, “Clock and Reset Generator”
— Table 19 updates
– Changed specs J1b and J6 maximum from 40 MHz to 50 MHz
– Reversed polarity of XCLKS reference in footnote (3)
– J1b maximum changed to 40 MHz
– VDCBIAS removed
– Added footnote to define tfsys as 1 ÷ fSYS for use elsewhere in the document
— Updated Section 3.8.2, “PLL Filter Characteristics”
— Table 20 updates
– Changed spec K3 maximum from 40 MHz to 50 MHz
– Added footnote to define tfsys as 1 ÷ fSYS for use elsewhere in the document
— Table 23 updates
– Removed VPORR and VPORA, as they duplicated H6
– Removed tWRS
• Section 3.9, “External Bus Timing”
— Table 24 updates
– M1 minimum changed from 25 ns to 20 ns (Figure 6 also updated)
– Reworded footnote (1)
– Added footnote (2) to define tCYC as 1 ÷ CLKOUT
— Table 25 updates
– Added footnote (1)
– Consolidated previous NOTES into footnote (2), (Figure 7, Figure 8 also updated)
4
4
5
5
7, 8
6
6
6
7
8
9
10
12
12
13
14
15
16
18
19
20
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MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
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Freescale Semiconductor
Mechanical Information
Revision History (continued)
Version No.
Release Date
v1.0
14-Sep-04
(continued)
Description of Changes
Section 3, “Electrical Characteristics” (continued)
• Section 3.10, “Analog-to-Digital Converter”
— Rev. 0.1 redundant and superfluous content deleted
– Section 3.10.3, “ATD Electrical Specifications,” (included Table 29 and Table 30)
– Table 31, “ATD Performance Specifications” (redundant with v0.1 Table 27 and
Table 28, now Table 29 and Table 30)
— Table 26 updates
– Deleted previous spec M6
– Changed spec N7 and N8 values
— Table 27 updates
– Deleted previous spec N6
– Changed spec P7 and P8 values
– Changed spec P2 and footnote (1) to specify 3.15 V
— Table 28 updates
– Changed spec Q2 parameter classification from T to C and 10 pF and 22 pF values
moved from maximum to typical
— Table 29 updates
– Operating conditions VDDA minimum changed to 4.5 V
– VREF description moved from “conditions” header to new footnote (1)
— Table 30 updates
– Operating conditions VDDA minimum changed to 3.15 V
– VREF description moved from “conditions” header to new footnote (1)
— Table 31 updates
– Spec T1 description clarified, max removed, min added with footnote
– Spec T2 modified to show both edge- and level-sensitive modes
— Figure 10 modified to remove “Max Frequency” label and clearly separate edge- and
level-sensitive mode timing examples
• Section 3.11, “Serial Peripheral Interface”
— Table 32 updates
– Changed specs U1a, U1b and U4 to use fIPS and tIPS for clarity and consistency with
MAC7100RM
– Changed U1a max to ½ and U1b min to 2 to account for the DBR bit
— Table 33 updates
– Changed specs V1a, V1b, V2, V3, V4, V7, V8 to use fIPS and tIPS for clarity and
consistency with MAC7100RM
– Changed V1a max to ½ and V1b min to 2 to account for the DBR bit
• Section 3.13, “Common Flash Module”
— Significant rework to match MAC7100RM clock naming, references and timing
calculations for clarity and consistency
— Changed X1 maximum from 40 MHz to 50 MHz (Table 35)
Page
Numbers
24
24
24
25
26
26
28
28
29
29
32 to 35
34
MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
Freescale Semiconductor
Preliminary
53
Mechanical Information
Revision History (continued)
Version No.
Release Date
v1.0
14-Sep-04
(continued)
v1.1
1-Dec-04
v1.1.1
3-Dec-04
v1.2
10-Feb--06
Page
Numbers
Description of Changes
Section 4, “Device Pin Assignments”
• Table 37 and Table 38 added
• Added PD2 label / footnote to Figure 15, Figure 17, Figure 19, Figure 20 and Figure 22
• Section 4.2, “MAC7142 Pin Diagram” / Figure 16 added
• Section 4.3, “MAC7121 / MAC7126 Pin Diagram” / Figure 17 updated
— PB10 / PCS5_B / PCSS_B bonded out on pin 57, footnote for L49P
— Added MAC71x6 device information
• Section 4.4, “MAC7122 Pin Diagram” / Figure 18 added
• Section 4.5, “MAC7101 / MAC7106 Pin Diagram” / Figure 19 updated
— Added MAC71x6 device information
• Section 4.6, “MAC7111 / MAC7116 Pin Diagram” / Figure 20 updated
— Added AS to TA pin
— Added MAC71x6 device information
• Section 4.7, “MAC7112 Pin Diagram” / Figure 21 added
• Section 4.8, “MAC7131 Pin Diagram” / Figure 22 corrected, updated
— Changed pins C8 & P8 from VSS2.5 to VDD2.5
— Changed pin T8 from VSSPLL to VDDPLL
— Added AS to TA pin
• Section 4.9, “MAC7136 Pin Diagram” / Figure 23 added
Section 3, “Electrical Characteristics”
• Section 3.7, “Power Supply”
— Table 15 spec F4 –40° C and 25° C max value changed
— Table 16 spec G4 –40° C and 25° C max value changed
• Section 3.8, “Clock and Reset Generator”
— Table 19 spec J3 typical TBD entry replaced with value
— Table 20 specs K15 and K16 maximum TBD entries replaced with values
36, 40
41, 43, 45, 46, 48
42
43
44
45
46
47
48
49
12
12
15
18
Section 3, “Electrical Characteristics”
• Section 3.7, “Power Supply”
— Table 15 spec F3 –40° C, 25° C and 125° C typ and max values and unit changed
— Table 16 spec G3 –40° C, 25° C and 125° C typ and max value and unit changed
12
12
Section 1, “Overview”
• Moved 71x6 device numbers from footnote to “covered” list
1
Section 2, “Ordering Information”
• Added AF, AG and VM package identifiers to Figure 1
• Added 1L38Y to Table 1
2
2
Section 3, “Electrical Characteristics”
• Replaced TBD values in Table 15 and Table 16 with final qualification data, changed table
titles and footnotes to reflect 71x6 inclusion.
Section 5, “Mechanical Information”
• Removed obsolete package diagrams, replaced with document IDs available on web site.
12
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MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2
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Freescale Semiconductor
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Rev. 1.2, 02/2006
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