MDTIC MDT10P41A1 8-bit micro-controller Datasheet

MDT10P41A1
1. General Description
transmitters/receivers,
pointing
devices,
and
telecommunications processors, such as Remote
This EPROM-Based 8-bit Micro-controller uses a
controller,
small
instruments,
chargers,
fully static CMOS technology to achieve high
automobile and PC peripheral … etc.
toy,
speed, small size, low power and high noise
immunity. Internal RC oscillator
On chip memory includes 1K words of EPROM,
4. Pin Assignment
and 31 bytes of static RAM.
2. Features
u
Fully CMOS static design
u
8-bit data bus
u
On chip ROM size :1 K words
u
Internal RAM size : 31 bytes
MDT10P41A1P / MDT10P41A1S
PB4
PB5
PB6
PB7
Vdd
NC
NC
PA0
(25 general purpose registers, 6 special
registers)
u
34 single word instructions
u
14-bit instructions
u
2-level stacks
u
Operating voltage : 2.3V ~ 5.5 V
u
Addressing modes include direct, indirect
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PB3
PB2
PB1
PB0
Vss
PA3
PA2
PA1
and relative addressing modes
u
Power-on Reset
u
Internal RC oscillator : 6.5MHz ~ 7.5MHz
u
12 I/O pins with their own independent
direction control
3. Applications
The application areas of this MDT10P41A1 range
from appliance motor control and high speed
automotive
to
low
power
remote
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
1 of 11
2005/6 Ver.1.6
MDT10P41A1
5. Block Diagram
Stack Two
Levels
RAM
25×8
EPROM
1024×14
Port A
10 bits
Program Counters
10 bits
Port
PA0~PA3
4 bits
14
bits
Instruction
Register
Special Register
Port PB0
D0~D7
Port PB1
Port B
Instruction
Decoder
Control Circuit
Internal RC
Data
8bit
Power on Reset
Power Down Reset
Working Register
ALU
Status Register
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
2 of 11
2005/6 Ver.1.6
Port
PB2 ~PB3
Port
PB4 ~PB7
MDT10P41A1
6. Pin Function Description
Pin Name
I/O
Function Description
PA0
I/O
Open drain ouput pin with 130K ohm pull-high resistor for input.
PA1~PA3
I/O
Port A, TTL input level.
PA1-PA3 are I/O pins with 50K ohm pull-high resistor for input.
PB0
I/O
I/O pin with 10K ohm pull-high resistor for input.
PB1
I/O
Open drain output with 10K ohm pull-high resistor for input.
PB2~PB3
I/O
Port B, TTL input level.
PB2-PB3 are I/O pins with 35K ohm pull-low resistors for input.
PB4~PB7
I/O
Port B, TTL input level
Vdd
Power supply
Vss
Ground
7. Memory Map
(A) Register Map
Address
Description
00
Indirect Addressing Register
01
Unimplemented
02
PC
03
STATUS
04
MSR
05
Port A
06
Port B
07~1F
Internal RAM, General Purpose Register
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
3 of 11
2005/6 Ver.1.6
MDT10P41A1
(1) IAR ( Indirect Address Register) : R0
(2) PC (Program Counter) : R2
Write PC, CALL --- always 0
LJUMP, JUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 (ROM 1K)
LJUMP, LCALL --- from instruction word
RTWI, RET --- from STACK
Write PC --- from ALU
LJUMP, JUMP, LCALL, CALL --- from instruction word
RTWI, RET --- from STACK
(3) STATUS (Status register) : R3
Bit
Symbol
Function
0
C
Carry bit
1
HC
Half Carry bit
2
Z
Zero bit
3
PF
Power loss Flag bit
4
——
Always read as high
5
page 0
Page select bit :
0 : 000H --- 1FFH
1 : 200H --- 3FFH
6—7
——
General purpose bit
(4) MSR (Memory Select Register) : R4
(5) PORT A : R5
Bit 3-0 : PA0~PA3, I/O Register
6-4 : Always read as high.
7
: Always read as zero.
(6) PORT B : R6
PB7~PB0, I/O Register
(7) CPIO A, CPIO B (Control Port I/O Mode Register)
The CPIO register is “write-only”
=“0”, I/O pin in output mode;
=“1”, I/O pin in input mode.
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
4 of 11
2005/6 Ver.1.6
MDT10P41A1
(8) EPROM Option by writer programming :
Security bit
Weak Disable
Disable
Enable
The default EPROM security is weak disable.
8. Reset Condition for all Registers
Register
Address
Power-On Reset
CPIO A
--
1111 1111
CPIO B
--
1111 1111
IAR
00h
-
PC
02h
1111 1111
STATUS
03h
0001 1xxx
MSR
04h
111x xxxx
PORT A
05h
- 111 xxxx
PORT B
06h
xxxx xxxx
Note : “ x “=unknown, “ – “=unimplemented, read as “0”
9. Instruction Set
Instruction Code
Mnemonic
Operands
Function
Operating
010000 00000000
NOP
No operation
None
010000 00000010
SLEEP
Sleep mode
0→WT,
Status
TF, PF
stop OSC
010000 00000100
RET
Return
Stack→PC
None
010000 00000rrr
CPIO R
Control I/O port register
W→CPIO r
None
010001 1rrrrrrr
STWR R
Store W to register
W→R
None
011000 trrrrrrr
LDR R, t
Load register
R→t
Z
111010 iiiiiiii
LDWI I
Load immediate to W
I→W
None
010111 trrrrrrr
SWAPR R, t
Swap halves register
[R(0~3) ↔
R(4~7)]→t
None
011001 trrrrrrr
INCR R, t
Increment register
R + 1→t
Z
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
5 of 11
2005/6 Ver.1.6
MDT10P41A1
Instruction Code
Mnemonic
Operands
Function
Operating
Status
011010 trrrrrrr
INCRSZ R, t
Increment register, skip if zero
R + 1→t
None
011011 trrrrrrr
ADDWR R, t
Add W and register
W + R→t
C, HC, Z
011100 trrrrrrr
SUBWR R, t
Subtract W from register
R ﹣W→t
(R+/W+1→t)
C, HC, Z
011101 trrrrrrr
DECR R, t
Decrement register
R ﹣1→t
Z
011110 trrrrrrr
DECRSZ R, t
Decrement register, skip if zero
R ﹣1→t
None
010010 trrrrrrr
ANDWR R, t
AND W and register
R ∩ W→t
Z
110100 iiiiiiii
ANDWI i
AND W and immediate
i ∩ W→W
Z
010011 trrrrrrr
IORWR R, t
Inclu. OR W and register
R ∪ W→t
Z
110101 iiiiiiii
IORWI i
Inclu. OR W and immediate
i ∪ W→W
Z
010100 trrrrrrr
XORWR R, t
Exclu. OR W and register
R ⊕ W→t
Z
110110 iiiiiiii
XORWI i
Exclu. OR W and immediate
i ⊕ W→W
Z
011111 trrrrrrr
COMR R, t
Complement register
/R→t
Z
010110 trrrrrrr
RRR
R, t
Rotate right register
R(n) →R(n-1), C
→R(7), R(0)→C
C
010101 trrrrrrr
RLR
R, t
Rotate left register
R(n)→r(n+1),
C
C→R(0),
R(7)→C
010000 1xxxxxxx
CLRW
Clear working register
0→W
Z
010001 0rrrrrrr
CLRR
Clear register
0→R
Z
0000bb brrrrrrr
BCR
R, b
Bit clear
0→R(b)
None
0010bb brrrrrrr
BSR
R, b
Bit set
1→R(b)
None
0001bb brrrrrrr
BTSC R, b
Bit Test, skip if clear
Skip if R(b)=0
None
0011bb brrrrrrr
BTSS R, b
Bit Test, skip if set
Skip if R(b)=1
None
1000nn nnnnnnnn
LCALL n
Long CALL subroutine
n→PC,
None
R
PC+1→Stack
1010nn nnnnnnnn
LJUMP n
Long JUMP to address
n→PC
None
110000 nnnnnnnn
CALL
Call subroutine
n→PC,
None
n
PC+1→Stack
110001 iiiiiiii
RTWI
i
Return, place immediate to W
Stack→PC,
None
i→W
11001n nnnnnnnn
JUMP
n
JUMP to address
n→PC
None
Note :
W
CPIO
HC
Z
C
PF
PC
OSC
:
:
:
:
:
:
:
:
Working register
Control I/O port register
Half carry
Zero flag
Carry flag
Power loss flag
Program Counter
Oscillator
b :
t :
R
i
n
Bit position
Target
0 : Working register
1 : General register
:
:
:
General register address
Immediate data ( 8 bits )
Immediate address
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
6 of 11
2005/6 Ver.1.6
MDT10P41A1
Inclu.
Exclu.
AND
:
:
:
Inclusive ‘∪’
Exclusive ‘⊕’
Logic AND ‘∩’
/
x
:
:
Complement
Don’t care
10. Electrical Characteristics
(Operating temperature at 25℃).
Sym
Description
Condition
Min
Vdd Operating voltage
2.3
Fosc Internal RC oscillator frequency Vdd=5V
6.5
VIL
Typ
7
Max
Unit
5.5
V
7.5
MHz
Input Low Voltage
PA, PB
Vdd=5V
-0.6
1.0
V
PA, PB
Vdd=5V
2.0
Vdd
V
IIL
Input leakage current
Vdd=5V
+/-1
µA
VOL
Output Low Voltage
VIH
Input high Voltage
PA, PB
Vdd=5V, IOL=20mA
0.5
V
Vdd=5V, IOL=5mA
0.2
V
Vdd=5V, IOH= -20mA
4.0
V
Vdd=5V, IOH= -5mA
4.7
V
VOH Output High Voltage
PA, PB
Vpr
Power Edge-detector Reset
1.2
1.5
V
Voltage
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
7 of 11
2005/6 Ver.1.6
MDT10P41A1
11. (A)PA0 Equivalent Circuit
D
PA0:
Pull_Hi130K
Q
I/O
Control
Latch
I/O Control
QB
CK
Port I/O Pin
D
Data O/P
Latch
Write
Q
B
G
Data Bus
D
QB
Input Resistor
Data I/P
Latch
Read
TTL Input Level
G
(B)PA1~PA3 Equivalent Circuit
D
PA1~3:
Pull_Hi 50K
Q
I/O
Control
Latch
I/O Control
QB
CK
Port I/O Pin
D
Data O/P
Latch
Write
G
QB
Data Bus
D
QB
Read
Input Resistor
Data I/P
Latch
TTL Input Level
G
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
8 of 11
2005/6 Ver.1.6
MDT10P41A1
12. (A) PB0 Equivalent Circuit
D
Q
Pull_Hi 10K
I/O
Control
Latch
I/O Control
QB
CK
Port I/O Pin
D
Data O/P
Latch
Write
G
QB
Data Bus
D
QB
Input Resistor
Data I/P
Latch
Read
TTL Input Level
G
(B) PB1 Equivalent Circuit
D
Q
Pull_Hi 10K
I/O
Control
Latch
I/O Control
CK
QB
Port I/O Pin
D
Data O/P
Latch
Write
G
QB
Data Bus
D
QB
Read
Data I/P
Latch
Input Resistor
TTL Input Level
G
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
9 of 11
2005/6 Ver.1.6
MDT10P41A1
(C) PB2 ~ PB3 Equivalent Circuit
D
Q
I/O
Control
Latch
I/O Control
CK
QB
Port I/O Pin
D
Data O/P
Latch
Write
G
PULL- LOW
35 K
QB
Data Bus
D
QB
Read
Data I/P
Latch
Input Resistor
TTL Input Level
G
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
10 of 11
2005/6 Ver.1.6
MDT10P41A1
(D) PB4 ~ PB7 Equivalent Circuit
D
Q
I/O
Control
Latch
I/O Control
QB
CK
Port I/O Pin
D
Data O/P
Latch
Write
G
QB
Data Bus
D
QB
Read
Data I/P
Latch
Input Resistor
TTL Input Level
G
This specification is subject to be changed without notice. Please visit our web site for the most updated information.
http://www.mdtic.com.tw
11 of 11
2005/6 Ver.1.6
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