A1245 Chopper-Stabilized, Two Wire Hall-Effect Latch FEATURES AND BENEFITS DESCRIPTION • High speed, 4-phase chopper stabilization □□ Low switchpoint drift throughout temperature range □□ Low sensitivity to thermal and mechanical stresses • On-chip protection □□ Supply transient protection □□ Reverse battery protection • On-board voltage regulator □□ 3.0 to 24 V operation • Solid-state reliability • Industry leading ISO 7637-2 performance through use of proprietary, 40 V clamping structures The A1245 is a two-wire Hall-effect latch. The device is produced on the Allegro™ advanced BiCMOS wafer fabrication process, which implements a patented high frequency, 4-phase, chopper-stabilization technique. This technique achieves magnetic stability over the full operating temperature range, and eliminates offsets inherent in devices with a single Hall element that are exposed to harsh application environments. Two-wire latches are particularly advantageous in cost-sensitive applications because they require one less wire for operation versus the more traditional open-collector output switches. Additionally, the system designer inherently gains diagnostics because there is always output current flowing, which should be in either of two narrow ranges. Any current level not within these ranges indicates a fault condition. PACKAGES: The Hall-effect latch will be in the high output current state in the presence of a magnetic south polarity field of sufficient magnitude and will remain in this state until a sufficient north polarity field is present. Not to scale Approximate footprints The device is offered in two package styles. The LH is a SOT-23W style, miniature low profile package for surfacemount applications. The UA is a 3-pin ultra-mini single inline packages (SIP) for through-hole mounting. Both packages are lead (Pb) free, with 100% matte tin leadframe plating. 3-pin SOT23-W 2 × 3 × 1 mm (suffix LH) 3-pin ultramini SIP 1.5 × 4 × 3 mm (suffix UA) VCC V+ Regulator To all subcircuits Amp Sample and Hold Dynamic Offset Cancellation Clock/Logic Low-Pass Filter Schmitt Trigger Polarity GND UA package only Functional Block Diagram A1245-DS, Rev. 1 GND Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 Selection Guide Part Number Packing* Package Operating Ambient Temperature, TA (°C) Supply Current at ICC(L) (mA) –40 to 150 5 to 6.9 A1245LLHLX-I1-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A1245LLHLX-I2-T 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount –40 to 150 2 to 5 A1245LUA-I1-T Bulk, 500 pieces/bag 3-pin SIP through hole –40 to 150 5 to 6.9 A1245LUA-I2-T Bulk, 500 pieces/bag 3-pin SIP through hole –40 to 150 2 to 5 *Contact Allegro for additional packing options SPECIFICATIONS Absolute Maximum Ratings Characteristic Symbol Notes Rating Unit 28 V Forward Supply Voltage VCC Reverse Supply Voltage VRCC –18 V B Unlimited G Magnetic Flux Density Operating Ambient Temperature TA –40 to 150 ºC Maximum Junction Temperature TJ(max) 165 ºC Tstg –65 to 170 ºC Storage Temperature Range L Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 2 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 Pin-out Diagrams and Terminal List Table 3 NC 2 1 2 1 LH Package, 3-pin SOT23W Pin-out 3 UA Package, 3-pin SIP Pin-out Terminal List Table Name Number Function LH UA VCC 1 1 Connects power supply to chip NC 2 N/A No connection (tie to GND; improved thermal characteristics) or float GND 3 2, 3 Ground (Tie both to GND for improved thermal characteristics, or float unused GND pin) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 3 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 ELECTRICAL CHARACTERISTICS: valid at TA = –40°C to 150°C; TJ < TJ(max); for LH and UA: CBYP = 0.01 µF; through operating supply voltage range; unless otherwise noted Characteristics Supply Voltage1,2 Supply Current Symbol VCC ICC(L) Test Conditions Operating -I1 B < BRP -I2 B < BRP Min. Typ. Max. Unit 3.0 – 24 V 5 – 6.9 mA 2 – 5 mA ICC(H) B > BOP 12 – 17 mA Supply Zener Clamp Voltage VZ(sup) ICC(L)(max) + 3 mA, TA = 25°C 28 – – V Supply Zener Clamp Current IZ(sup) VZ(sup) = 28 V – – ICC(L)(max) + 3 mA mA Reverse Supply Current IRCC VRCC = –18 V – – –1.6 mA dI/dt No external bypass capacitor, capacitance of probe CS = 20 pF – 90 – mA / µs – 700 – kHz Output Slew Rate3 Chopping Frequency5 Power-Up Time2,4,5 Power-Up State4,6,7 fc ton POS VCC ≥ VCC(min) – – 25 µs ton < ton(max) , VCC slew rate > 25 mV / µs – ICC(H) – – 1V CC 2 The represents the generated voltage between the VCC pin and the GND pin. VCC slew rate must exceed 600 mV/ms from 0 to VCC(min). A slower slew rate through this range can affect device performance. 3 Measured without bypass capacitor between VCC and GND. Use of a bypass capacitor results in slower current change. 4 Power-Up Time is measured with and without an external bypass capacitor of 0.01 µF, B < B RP – 10 G. Adding a larger bypass capacitor would cause longer Power-Up Time. 5 Guaranteed by characterization and design. 6 Power-Up State as defined is true only with a V CC slew rate of 25 mV / µs or greater. 7 Power-Up State is defined during the power-on phase (t < t ON) until the device has fully powered-on (tON), after which the output will correspond to the magnetic field level seen by the sensor. For t > ton and BRP < B < BOP , Power-Up State is not defined. MAGNETIC CHARACTERISTICS1: valid at TA = –40°C to 150°C; TJ < TJ(max); for LH and UA: CBYP = 0.01 µF; through operating supply voltage range; unless otherwise noted Characteristics Magnetic Operating Point Symbol Test Conditions BOP Magnetic Release Point BRP Hysteresis BHYS BOP – BRP Min. Typ. Max. Unit2 5 – 40 G –40 – –5 G 15 40 65 G 1Relative values of B use the algebraic convention, where positive values indicate south magnetic polarity, and negative values indicate north magnetic polarity; therefore greater B values indicate a stronger south polarity field (or a weaker north polarity field, if present). 2 1 G (gauss) = 0.1 mT (millitesla). Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 4 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information Characteristic Symbol Test Conditions* Package LH, 1-layer PCB with copper limited to solder pads Package Thermal Resistance RθJA Package LH, 2-layer PCB with 0.463 thermal vias in.2 of copper area each side connected by Package UA, 1-layer PCB with copper limited to solder pads Value Units 228 ºC/W 110 ºC/W 165 ºC/W *Additional thermal information available on Allegro Web site. Maximum Allowable VCC (V) Power Derating Curve Power Derating Curve 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 VCC(max) LH, 2-layer PCB (RqJA = 110 ºC/W) UA, 1-layer PCB (RqJA = 165 ºC/W) LH, 1-layer PCB (RqJA = 228 ºC/W) 20 40 60 80 100 120 VCC(min) 140 160 180 Temperature (ºC) Power Dissipation, P D (mW) Maximum Power Dissipation versus Ambient Temperature 1900 1800 1700 1600 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 2l (R aye rP θJ C A = 11 B, P 0º a 1-la C/ cka y W (R er PC ) ge L θJA = B, P H 165 ack ºC/ a W) ge U A 1-lay er P (R CB, θJA = 228 Packag ºC/W e LH ) 20 40 60 80 100 120 Temperature (°C) 140 160 180 Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 5 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 CHARACTERISTIC PERFORMANCE Average Supply Current (Low) vs. Supply Voltage 7.0 6.8 6.8 6.6 6.6 6.4 Supply Current, I CC (mA) Supply Current, I CC (mA) Average Supply Current (Low) vs. Temperature 7.0 6.2 6.0 5.8 3V 5.6 6.4 6.2 6.0 5.8 -40°C 5.6 25°C 5.4 5.4 150°C 5.2 5.2 24 V 5.0 -50 0 50 100 150 5.0 200 0 5 Ambient Temperature, TA (°C) 15 20 25 30 Supply Voltage, VCC (V) Average Supply Current (High) vs. Supply Voltage Average Supply Current (High) vs. Temperature 17.0 17.0 16.5 16.5 16.0 16.0 Supply Current, I CC (mA) Supply Current, I CC (mA) 10 15.5 15.0 14.5 14.0 3V 13.5 15.5 15.0 14.5 14.0 -40°C 13.5 25°C 13.0 13.0 150°C 12.5 12.5 24 V 12.0 -50 0 50 100 Ambient Temperature, TA (°C) 150 200 12.0 0 5 10 15 20 25 30 Supply Voltage, VCC (V) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 6 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 Average BOP vs. Supply Voltage 40.0 35.0 35.0 30.0 30.0 Flux Density (G) Flux Density (G) Average BOP vs. Temperature 40.0 25.0 20.0 3V 15.0 24 V 25.0 20.0 -40°C 15.0 10.0 25°C 150°C 10.0 5.0 -50 0 50 100 150 5.0 200 0 5 Ambient Temperature, TA (°C) 20 25 30 Average BRP vs. Supply Voltage -5.0 -5.0 -10.0 -10.0 -15.0 -15.0 Flux Density (G) Flux Density (G) 15 Supply Voltage, VCC (V) Average BRP vs. Temperature -20.0 -25.0 3V -30.0 -20.0 -25.0 -40°C -30.0 24 V 25°C 150°C -35.0 -35.0 -40.0 -40.0 -50 0 50 100 150 200 0 5 Ambient Temperature, TA (°C) 10 15 20 25 30 Supply Voltage, VCC (V) Average BHYS vs. Supply Voltage Average BHYS vs. Temperature 65.0 65.0 60.0 60.0 55.0 55.0 50.0 50.0 Flux Density (G) Flux Density (G) 10 45.0 40.0 35.0 3V 45.0 40.0 35.0 -40°C 30.0 25°C 25.0 25.0 150°C 20.0 20.0 30.0 24 V 15.0 15.0 -50 0 50 100 Ambient Temperature, TA (°C) 150 200 0 5 10 15 20 25 30 Supply Voltage, VCC (V) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 7 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 FUNCTIONAL DESCRIPTION The A1245 output, ICC, switches high after the magnetic field at the Hall sensor IC exceeds the operate point threshold, BOP . When the magnetic field is reduced to below the release point threshold, BRP , the device output goes low. This is shown in Figure 1. The difference between the magnetic operate and release points is called the hysteresis of the device, BHYS . This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise. I+ ICC Switch to Low Switch to High ICC(H) ICC(L) BRP B– BOP 0 B+ BHYS Figure 1: Hysteresis for the A1245 On the horizontal axis, the B+ direction indicates increasing south polarity magnetic field strength, and the B– direction indicates decreasing south polarity field strength (including the case of increasing north polarity). Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 8 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 RSENSE V+ V+ VCC VCC A1245 A1245 CBYP CBYP 0.01 µF 0.01 µF GND GND RSENSE (A) Low Side Sensing (B) High Side Sensing LH and UA Packages Figure 2: Typical Application Circuits Chopper Stabilization Technique When using Hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the Hall element. This voltage is disproportionally small relative to the offset that can be produced at the output of the Hall sensor IC. This makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. Chopper stabilization is a unique approach used to minimize Hall offset on the chip. The patented Allegro technique, namely Dynamic Quadrature Offset Cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. This offset reduction technique is based on a signal modulation-demodulation process. The undesired offset signal is separated from the magnetic fieldinduced signal in the frequency domain, through modulation. The subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the DC offset becomes a high-frequency signal. The magnetic-sourced signal then can pass through a low-pass filter, while the modulated DC offset is suppressed. The chopper stabilization technique uses a 350 kHz high frequency clock. For demodulation process, a sample and hold technique is used, where the sampling is performed at twice the chopper frequency. This high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. This approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent Hall output voltages and precise recoverability after temperature cycling. This technique is made possible through the use of a BiCMOS process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sampleand-hold circuits. Regulator Hall Element Amp Sample and Hold Clock/Logic Low-Pass Filter Figure 3: Chopper Stabilization Circuit (Dynamic Quadrature Offset Cancellation) Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 9 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 Power Derating The device must be operated below the maximum junction temperature of the device, TJ(max). Under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the application. This section presents a procedure for correlating factors affecting operating TJ. (Thermal data is also available on the Allegro MicroSystems Web site.) The Package Thermal Resistance, RθJA, is a figure of merit summarizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. Its primary component is the Effective Thermal Conductivity, K, of the printed circuit board, including adjacent devices and traces. Radiation from the die through the device case, RθJC, is relatively small component of RθJA. Ambient air temperature, TA, and air motion are significant external factors, damped by overmolding. The effect of varying power levels (Power Dissipation, PD), can be estimated. The following formulas represent the fundamental relationships used to estimate TJ, at PD. PD = VIN × IIN (1) ΔT = PD × RθJA (2) TJ = TA + ΔT (3) For example, given common conditions such as: TA= 25°C, VCC = 12 V, ICC = 9 mA, and RθJA = 110 °C/W, then: A worst-case estimate, PD(max), represents the maximum allowable power level (VCC(max), ICC(max)), without exceeding TJ(max), at a selected RθJA and TA. Example: Reliability for VCC at TA = 150°C, package LH, using a low-K PCB. Observe the worst-case ratings for the device, specifically: RθJA = 110 °C/W, TJ(max) = 165°C, VCC(max) = 24 V, and ICC(max) = 17 mA. Calculate the maximum allowable power level, PD(max). First, invert equation 3: ΔTmax = TJ(max) – TA = 165 °C – 150 °C = 15 °C This provides the allowable increase to TJ resulting from internal power dissipation. Then, invert equation 2: PD(max) = ΔTmax ÷ RθJA = 15°C ÷ 110 °C/W = 136 mW Finally, invert equation 1 with respect to voltage: VCC(est) = PD(max) ÷ ICC(max) = 136 mW ÷ 17 mA = 8 V The result indicates that, at TA, the application and device can dissipate adequate amounts of heat at voltages ≤VCC(est). Compare VCC(est) to VCC(max). If VCC(est) ≤ VCC(max), then reliable operation between VCC(est) and VCC(max) requires enhanced RθJA. If VCC(est) ≥ VCC(max), then operation between VCC(est) and VCC(max) is reliable under these conditions. PD = VCC × ICC = 12 V × 9 mA = 108 mW ΔT = PD × RθJA = 48 mW × 110 °C/W = 11.9°C TJ = TA + ΔT = 25°C + 11.9°C = 36.9°C Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 10 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 Package Outline Drawings For Reference Only – Not for Tooling Use (Reference DWG-2840) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown +0.12 2.98 –0.08 D 1.49 4° ±4° A 3 +0.020 0.180 –0.053 0.96 D +0.19 1.91 –0.06 +0.10 2.90 –0.20 2.40 0.70 D 0.25 MIN 1.00 2 1 0.55 REF 0.25 BSC 0.95 Seating Plane Branded Face Gauge Plane B PCB Layout Reference View 8X 10° REF 1.00 ±0.13 NNN +0.10 0.05 –0.05 0.95 BSC 0.40 ±0.10 C Standard Branding Reference View N = Last three digits of device part number A Active Area Depth, 0.28 mm B Reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances C Branding scale and appearance at supplier discretion D Hall elements, not to scale Figure 4: Package LH, 3-Pin SOT23W Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 11 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 For Reference Only – Not for Tooling Use (Reference DWG-9013) Dimensions in millimeters – NOT TO SCALE Dimensions exclusive of mold flash, gate burrs, and dambar protrusions Exact case and lead configuration at supplier discretion within limits shown 45° B 4.09 +0.08 –0.05 1.52 ±0.05 E 2.04 C 2 X 10° 1.44 E 3.02 E Mold Ejector Pin Indent +0.08 –0.05 45° Branded Face A 1.02 MAX 0.79 REF 1 2 3 0.43 +0.05 –0.07 0.41 +0.03 –0.06 1.27 NOM NNN 14.99 ±0.25 1 D Standard Branding Reference View = Supplier emblem N = Last three digits of device part number A Dambar removal protrusion (6X) B Gate and tie bar burr area C Active Area Depth, 0.50 mm REF D Branding scale and appearance at supplier discretion E Hall element, not to scale Figure 5: Package UA, 3-Pin SIP Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 12 Chopper-Stabilized, Two Wire Hall-Effect Latch A1245 Revision History Revision Date – December 17, 2014 1 July 13, 2015 Change Initial Release Corrected LH package Active Area Depth value Copyright ©2013-15, Allegro MicroSystems, LLC Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of Allegro’s product can reasonably be expected to cause bodily harm. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com Allegro MicroSystems, LLC 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com 13