IMP C3015 Cmos 3um digital Datasheet

®
ISO 9001 Registered
Process C3015
CMOS 3µm
Digital
Electrical Characteristics
T=25oC Unless otherwise noted
N-Channel Transistor
Threshold Voltage
Body Factor
Conduction Factor
Effective Channel Length
Width Encroachment
Punch Through Voltage
Poly Field Threshold Voltage
Symbol
VTN
γN
βN
LeffN
∆WN
BVDSSN
VTFP(N)
Minimum
0.6
P-Channel Transistor
Threshold Voltage
Body Factor
Conduction Factor
Effective Channel Length
Width Encroachment
Punch Through Voltage
Poly Field Threshold Voltage
Symbol
VTP
γP
βP
LeffP
∆WP
BVDSSP
VTFP(P)
Minimum
–0.6
Diffusion & Thin Films
Well (field) Sheet Resistance
N+ Sheet Resistance
N+ Junction Depth
P+ Sheet Resistance
P+ Junction Depth
Gate Oxide Thickness
Gate Poly Sheet Resistance
Metal-1 Sheet Resistance
Passivation Thickness
Symbol
ρP-well(f)
ρN+
xjN+
ρP+
xjP+
TGOX
ρPOLY1
ρM1
TPASS
Minimum
3.2
16
Capacitance
Gate Oxide
Metal-1 to Poly-1
Metal-1 to Silicon
Symbol
COX
CM1P
CM1S
Minimum
0.66
© IMP, Inc.
42
2.85
Typical
0.8
0.6
47
3.2
0.7
Maximum
1.0
Typical
–0.8
0.55
15
3.2
0.9
Maximum
–1.0
Typical
4.8
21
0.8
80
0.7
40.0
22
30
200+900
Maximum
6.5
27
Typical
0.72
0.0523
0.030
Maximum
0.78
52
3.55
12
12
13
2.85
19
3.55
–12
–12
50
37.5
15
0.026
100
42.5
30
60
0.034
Unit
V
V1/2
µA/V2
µm
µm
V
V
Comments
100x3µm
100x3µm
100x100µm
100x3µm
Per side
Unit
V
V1/2
µA/V2
µm
µm
V
V
Comments
100x3µm
100x3µm
100x100µm
100x3µm
Per side
Unit
KΩ/o
Ω/o
µm
Ω/o
µm
nm
Ω/o
mΩ/o
nm
Comments
P-well
Unit
fF/µm2
fF/µm2
fF/µm2
oxide+nit.
Comments
89
Process C3015
Physical Characteristics
Starting Material
Starting Mat. Resistivity
Typ. Operating Voltage
Well Type
Metal Layers
Poly Layers
Contact Size
Metal-1 Width/Space
Gate Poly Width/Space
N <100>
15 - 25 Ω-cm
5V
P-well
1
1
2.0x2.0µm
3.5 / 2.5µm
3.0 / 2.5µm
N+/P+ Width/Space
N+ To P+ Space
Contact To Poly Space
Contact Overlap Of Diffusion
Contact Overlap Of Poly
Metal-1 Overlap Of Contact
Minimum Pad Opening
Minimum Pad-to-Pad Spacing
Minimum Pad Pitch
3.0 / 3.0µm
12µm
2.5µm
1.5µm
1.0µm
1.0 µm
100x100µm
5.0µm
80.0µm
Special Feature of C3015 Process: 3 µm P-well digital process.
Second metal
Poly gate
SIO2
A1
LTO
substrate
Cross-sectional view of the C3015 process
ID vs VD, W/L = 20/4.0
ID vs VD, W/L = 20/4.0
5
–3
VGS = 10V
VGS = 8.0V
3
VGS = 7.0V
VGS = 6.0V
2
VGS = 5.0V
VGS = 4.0V
1
VGS = 3.0V
Drain Current (mA) IDS
Drain Current (mA) IDS
–2.5
VGS = 9.0V
4
–2
VGS = –10V
VGS = –9.0V
–1.5
VGS = –8.0V
VGS = –7.0V
–1
VGS = –6.0V
VGS = –5.0V
–.5
VGS = 2.0V
0
5 6
7 8
9 10
3 4
Drain Voltage (v), VDS
n-ch Transistor IV Characteristics of a 20/4.0 device
90
0
1
2
C3015-4-98
0
0
1
2
7 8
5 6
3 4
Drain Voltage (v) VDS
9
VGS = –4.0V
VGS = –3.0V
VGS = –2.0V
10
p-ch Transistor Characteristics of a 20/4.0 device
Poly gate
Contact
Bottom poly
p
Sidewall spacer
n-epi
N+
n+
Source
p+
Field Oxide
N– substrate contact
p-well
p+
p
Drain
n+
source
n+
Drain
p-well contact
p+
p
SIO2
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