Allegro A6259KLW 8-bit addressable dmos power driver Datasheet

8-BIT ADDRESSABLE
DMOS POWER DRIVER
ADVANCE INFORMATION
(Subject to change without notice)
January 24, 2000
20
POWER
GROUND
2
19
CLEAR
S 0 (LSB)
3
18
DATA
OUT 0
4
17
OUT 7
OUT 1
5
16
OUT 6
OUT 2
6
15
OUT 5
OUT 3
7
14
OUT 4
S1
8
13
ENABLE
LOGIC
GROUND
9
12
S 2 (MSB)
POWER
GROUND
10
11
POWER
GROUND
VDD
LATCHES
LOGIC
SUPPLY
LATCHES
1
DECODER LOGIC
POWER
GROUND
EN
Dwg. PP-050-2
Note that the A6259KA (DIP) and the A6259KLW
(SOIC) are electrically identical and share a
common terminal number assignment.
ABSOLUTE MAXIMUM RATINGS
at TA = 25°C
Output Voltage, VO ............................ 50 V
Output Drain Current,
Continuous, IO ...................... 250 mA*
Peak, IOM ............................. 750 mA*†
Peak, IOM ................................... 2.0 A†
Single-Pulse Avalanche Energy,
EAS ............................................. 75 mJ
Logic Supply Voltage, VDD .............. 7.0 V
Input Voltage Range,
VI ............................... -0.3 V to +7.0 V
Package Power Dissipation,
PD ....................................... See Graph
Operating Temperature Range,
TA ............................. -40°C to +125°C
Storage Temperature Range,
TS ............................. -55°C to +150°C
*Each output, all outputs on.
† Pulse duration ≤ 100 µs, duty cycle ≤ 2%.
Caution: These CMOS devices have input static
protection (Class 3) but are still susceptible to
damage if exposed to extremely high static
electrical charges.
Data Sheet
26186.120
6259
The A6259KA and A6259KLW combine a 3-to-8 line CMOS
decoder and accompanying data latches, control circuitry, and DMOS
outputs in a multi-functional power driver capable of storing single-line
data in the addressable latches or use as a decoder or demuliplexer.
Driver applications include relays, solenoids, and other medium-current
or high-voltage peripheral power loads.
The CMOS inputs and latches allow direct interfacing with microprocessor-based systems. Use with TTL may require appropriate pullup resistors to ensure an input logic high. Four modes of operation are
selectable with the CLEAR and ENABLE inputs.
The addressed DMOS output inverts the DATA input with all
unaddressed outputs remaining in their previous states. All of the output
drivers are disabled (the DMOS sink drivers turned off) with the
CLEAR input low and the ENABLE input high. The A6259KA/KLW
DMOS open-drain outputs are capable of sinking up to 750 mA. Similar
devices with reduced rDS(on) are available as the A6A259.
The A6259KA is furnished in a 20-pin dual in-line plastic package.
The A6259KLW is furnished in a 20-lead wide-body, small-outline
plastic package (SOIC) with gull-wing leads for surface-mount applications. Copper lead frames, reduced supply current requirements, and
low on-state resistance allow both devices to sink 150 mA from all
outputs continuously, to ambient temperatures over 85°C.
FEATURES
■ 50 V Minimum Output Clamp Voltage
■ 250 mA Output Current (all outputs simultaneously)
■ 1.3 Ω Typical rDS(on)
■ Low Power Consumption
■ Replacements for TPIC6259N and TPIC6259DW
Always order by complete part number:
Part Number
Package
A6259KA
20-pin DIP
A6259KLW
20-lead SOIC
RθJA
55°C/W
70°C/W
RθJC
25°C/W
17°C/W
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
LOGIC SYMBOL
2.5
3
8
12
13
18
19
2.0
SU
FF
IX
1.5
SU
FF
IX
'A
', R
θJ
A =
'LW
', R
θJ
1.0
A
55
°C
/W
=7
0°
C/
W
0.5
0
50
75
100
125
AMBIENT TEMPERATURE IN °C
25
150
0
8M 0/7
2
G8
Z9
Z10
9,0D
10,0R
4
9,1D
10,1R
5
9,2D
10,2R
6
9,3D
10,3R
7
9,4D
10,4R
14
9,5D
10,5R
15
9,6D
10,6R
16
9,7D
10,7R
17
Dwg. FP-046
Dwg. GS-004A
VDD
OUT
IN
Dwg. EP-063
Dwg. EP-010-15
LOGIC INPUTS
DMOS POWER DRIVER OUTPUT
FUNCTION TABLE
Inputs
CLEAR ENABLE DATA
H
H
H
L
L
L
L
L
H
L
L
H
L = Low Logic Level
H
L
X
H
L
X
LATCH SELECTION TABLE
Addressed
OUTPUT
Other
OUTPUTs
L
H
R
L
H
H
R
R
R
H
H
H
H = High Logic Level
X = Irrelevant
Function
Addressable
Latch
Memory
8-Line
Demultiplexer
Clear
R = Previous State
Select Inputs
Addressed
S2 (MSB) S1 S0 (LSB) OUTPUT
L
L
L
L
H
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
0
1
2
3
4
5
6
H
H
H
7
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2000, Allegro MicroSystems, Inc.
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
FUNCTIONAL BLOCK DIAGRAM
D
S0
(LSB)
OUT 0
C1
CLR
D
OUT 1
C1
CLR
S1
D
OUT 2
C1
CLR
D
OUT 3
C1
CLR
S2
(MSB)
D
OUT 4
C1
CLR
D
LOGIC
SUPPLY
V DD
OUT 5
C1
CLR
LOGIC
GROUND
D
OUT 6
C1
CLR
DATA
D
OUT 7
C1
ENABLE
(ACTIVE LOW)
CLR
CLEAR
POWER
GROUND
(ACTIVE LOW)
Dwg. FP-047-1
Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.
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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
RECOMMENDED OPERATING CONDITIONS
over operating temperature range
Logic Supply Voltage Range, VDD ............... 4.5 V to 5.5 V
High-Level Input Voltage, VIH ............................ ≥ 0.85VDD
Low-level input voltage, VIL ................................. ≤0.15VDD
ELECTRICAL CHARACTERISTICS at TA = +25°C, VDD = 5 V, tir = tif ≤ 10 ns (unless otherwise
specified).
Limits
Characteristic
Logic Supply Voltage
Symbol
Test Conditions
Min.
Typ.
Max.
Units
VDD
Operating
4.5
5.0
5.5
V
V(BR)DSX
IO = 1 mA
50
—
—
V
IDSX
VO = 40 V
—
0.05
1.0
µA
VO = 40 V, TA = 125°C
—
0.15
5.0
µA
IO = 250 mA, VDD = 4.5 V
—
1.3
2.0
Ω
IO = 250 mA, VDD = 4.5 V, TA = 125°C
—
2.0
3.2
Ω
IO = 500 mA, VDD = 4.5 V (see note)
—
1.3
2.0
Ω
VDS(on) = 0.5 V, TA = 85°C
—
250
—
mA
IIH
VI = VDD = 5.5 V
—
—
1.0
µA
IIL
VI = 0, VDD = 5.5 V
—
—
-1.0
µA
tPLH
IO = 250 mA, CL = 30 pF
—
625
—
ns
tPHL
IO = 250 mA, CL = 30 pF
—
140
—
ns
Output Rise Time
tr
IO = 250 mA, CL = 30 pF
—
650
—
ns
Output Fall Time
tf
IO = 250 mA, CL = 30 pF
—
400
—
ns
IDD(off)
VDD = 5.5 V, Outputs OFF
—
15
100
µA
IDD(on)
VDD = 5.5 V, Outputs ON
—
150
300
µA
Output Breakdown
Voltage
Off-State Output
Current
Static Drain-Source
On-State Resistance
Nominal Output
Current
Logic Input Current
Prop. Delay Time
Supply Current
rDS(on)
IO(nom)
Typical Data is at VDD = 5 V and is for design information only.
NOTE — Pulse test, duration ≤ 100 µs, duty cycle ≤ 2%.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
FUNCTIONAL DESCRIPTION and INPUT REQUIREMENTS
Four modes of operation are selectable by controlling
the CLEAR and ENABLE inputs as shown above.
ENABLE
DATA
In the addressable-latch mode, data at the DATA input
is written into the addressed transparent latch. The
addressed output inverts the data input with all other
outputs remaining in their previous states.
50%
t PLH
t PHL
90%
ADDRESSED
OUTPUT
10%
tr
tf
Dwg. WP-036
OUTPUT SWITCHING TIME
ENABLE
DATA
In the demultiplexing/decoding mode, the addressed
output inverts the data input and all other outputs are OFF.
50%
t h(D)
t su(D)
In the memory mode, all outputs remain in their
previous states and are unaffected by the DATA or
address (Sn) inputs. To prevent entering erroneus data in
the latches, ENABLE should be held HIGH while the
address lines are changing.
In the clear mode, all outputs are OFF and are unaffected by the DATA or address (SN) inputs.
50%
t w(D)
Dwg. WP-037
DATA INPUT REQUIREMENTS
Data Active Time Before Enable
(Data Set-Up Time), tsu(D) .............................................. 20 ns
Data Active Time After Enable
(Data Hold Time), th(D) ................................................... 20 ns
Data Pulse Width, tw(D) ....................................................... 40 ns
Input Logic High, VIH ................................................ ≥ 0.85VDD
Input Logic Low, VIL ................................................. ≤ 0.15VDD
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Given the appropriate inputs, when DATA is LOW
for a given address, the output is OFF; when DATA is
HIGH, the output is ON and can sink current.
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
TEST CIRCUITS
+15 V
0.11 Ω
INPUT
100 mH
tav
IAS = 1.0 A
IO
DUT
OUT
VO
V(BR)DSX
VO(ON)
Dwg. EP-066-1
EAS = IAS x V(BR)DSX x tAV/2
Single-Pulse Avalanche Energy Test Circuit
and Waveforms
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
TERMINAL DESCRIPTIONS
Terminal No.
Terminal Name
Function
1
POWER GROUND
2
LOGIC SUPPLY
3
S0
4
OUT0
Current-sinking, open-drain DMOS output, address 000.
5
OUT1
Current-sinking, open-drain DMOS output, address 001.
6
OUT2
Current-sinking, open-drain DMOS output, address 010.
7
OUT3
Current-sinking, open-drain DMOS output, address 011.
8
S1
9
LOGIC GROUND
Reference terminal for input voltage measurements.
10
POWER GROUND
Reference terminal for output voltage measurements (OUT0-3).
11
POWER GROUND
Reference terminal for output voltage measurements (OUT4-7).
12
S2
13
ENABLE
14
OUT4
Current-sinking, open-drain DMOS output, address 100.
15
OUT5
Current-sinking, open-drain DMOS output, address 101.
16
OUT6
Current-sinking, open-drain DMOS output, address 110.
17
OUT7
Current-sinking, open-drain DMOS output, address 111.
18
DATA
CMOS data input to the addressed output latch. When enabled, the
addressed output inverts the data input (DATA = HIGH, OUTPUT = LOW).
19
CLEAR
Mode control input; see Function Table.
20
POWER GROUND
Reference terminal for output voltage measurements (OUT0-3).
(VDD) The logic supply voltage (typically 5 V).
Binary-coded output-select input, least-significant bit.
Binary-coded output-select input.
Binary-coded output-select input, most-significant bit.
Mode control input; see Function Table.
Reference terminal for output voltage measurements (OUT4-7).
NOTE — Grounds (terminals 1, 9, 10, 11, and 20) must be connected externally to a single point.
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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
A6259KA
Dimensions in Inches
(controlling dimensions)
20
0.014
0.008
11
0.430
MAX
0.280
0.240
0.300
BSC
1
0.070
0.045
0.100
1.060
0.980
10
0.005
BSC
MIN
0.210
MAX
0.015
0.150
0.115
MIN
0.022
0.014
Dwg. MA-001-20 in
Dimensions in Millimeters
(for reference only)
20
0.355
0.204
11
10.92
MAX
7.11
6.10
7.62
BSC
1
1.77
1.15
2.54
26.92
24.89
10
0.13
BSC
MIN
5.33
MAX
0.39
3.81
2.93
MIN
0.558
0.356
Dwg. MA-001-20 mm
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
3. Lead thickness is measured at seating plane or below.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
A6259KLW
Dimensions in Inches
(for reference only)
20
11
0.0125
0.0091
0.419
0.394
0.2992
0.2914
0.050
0.016
0.020
0.013
1
2
0.050
3
0° TO 8°
BSC
0.5118
0.4961
0.0926
0.1043
0.0040 MIN.
Dwg. MA-008-20 in
Dimensions in Millimeters
(controlling dimensions)
20
11
0.32
0.23
10.65
10.00
7.60
7.40
1.27
0.40
0.51
0.33
1
2
1.27
3
13.00
12.60
BSC
0° TO 8°
2.65
2.35
0.10 MIN.
Dwg. MA-008-20 mm
NOTES:1. Exact body and lead configuration at vendor’s option within limits shown.
2. Lead spacing tolerance is non-cumulative.
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6259
8-BIT ADDRESSABLE
DMOS POWER DRIVER
The products described here are manufactured under one or more
U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to
time, such departures from the detail specifications as may be
required to permit improvements in the performance, reliability, or
manufacturability of its products. Before placing an order, the user is
cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components
in life-support devices or systems without express written approval.
The information included herein is believed to be accurate and
reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of
third parties which may result from its use.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000