CD4035BMS CMOS 4 -Stage Parallel In/Parallel Out Shift Register December 1992 Features Description • J - K Serial Inputs and True/Complement Outputs CD4035BMS is a four stage clocked signal serial register with provision for synchronous PARALLEL inputs to each stage and SERIAL inputs to the first stage via JK logic. Register stages 2, 3, and 4 are coupled in a serial D flip-flop configuration when the register is in the serial mode (PARALLEL/SERIAL control low). • High Voltage Type (20V Rating) • 4-Stage Clocked Shift Operation • Synchronous Parallel Entry on All 4 Stages • JK Inputs on First Stage • Asynchronous True/Complement Control on All Outputs • Static Flip-Flop Operation; Master-Slave Configuration Parallel entry into each register stage is permitted when the PARALLEL/SERIAL control is high. In the parallel or serial mode information is transferred on positive clock transitions. When the TRUE/COMPLEMENT control is high, the true contents of the register are available at the output terminals. When the TRUE/COMPLEMENT control is low, the outputs are the complements of the data in the register. The TRUE/ COMPLEMENT control functions asynchronously with respect to the CLOCK signal. • Buffered Inputs and Outputs • High Speed Operation 12MHz (Typ) at VDD = 10V • 100% Tested for Quiescent Current at 20V • Standardized, Symmetrical Output Characteristics • 5V, 10V and 15V Parametric Ratings • Meets All Requirements of JEDEC Tentative Standard Number 13A, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications JK input logic is provided on the first stage SERIAL input to minimize logic requirements particularly in counting and sequence-generation applications. With JK inputs connected together, the first stage becomes a D flip-flop. An asynchronous common, RESET is also provided. The CD4035BMS series type is supplied in these 16 lead outline packages • Counters, Registers - Arithmetic-Unit Registers - Shift Left/Shift Right Registers - Serial-to-Parallel/Parallel-to-Serial Conversions Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W • Sequence Generation • Control Circuits • Code Conversion Functional Diagram Pinout CD4035BMS TOP VIEW 9 Q1/Q1 1 TRUE/ COMP. 2 FIRST STAGE TRUTH TABLE PARALLEL IN 16 VDD 15 Q2/Q2 K 3 14 Q3/Q3 J 4 13 Q4/Q4 SER IN J K CLK P/S T/C RESET 5 12 PI-4 CLOCK 6 11 PI-3 P/S 7 10 PI-2 VSS 8 9 PI-1 RESET 1 10 2 11 3 12 CL 4 3 6 7 tn (OUTPUT) tn-1 (INPUT) 4 4-STAGE REGISTER 2 J K R Qn-1 Qn 0 X 0 0 0 1 X 0 0 1 X 0 0 1 0 1 0 0 Qn-1 Qn-1 Toggle Mode 5 VDD = 16 VSS = 8 1 15 14 13 X 1 0 1 1 Q1/Q1 Q2/Q2 Q3/Q3 Q4/Q4 X X 0 Qn-1 Qn-1 X X 1 X 0 T/C OUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-851 X File Number 3308 Specifications CD4035BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 10 µA - 1000 µA - 10 µA 2 VDD = 18V, VIN = VDD or GND Input Leakage Current Input Leakage Current IIL IIH VIN = VDD or GND VIN = VDD or GND VDD = 20 +125 oC -55oC 3 o 1 +25 C -100 - nA 2 +125oC -1000 - nA VDD = 18V 3 -55oC -100 - nA VDD = 20 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA - 50 mV - V VDD = 18V Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA - -1.8 mA - -1.4 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -3.5 mA -2.8 -0.7 V 0.7 2.8 V Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B P Threshold Voltage Functional VPTH F Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V 7-852 V -55oC +25oC, NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. VOH > VOL < VDD/2 VDD/2 +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V 1, 2, 3 +25oC, +125oC, -55oC - 4 V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD4035BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Q Propagation Delay Reset to Q Transition Time Maximum Clock Input Frequency SYMBOL TPHL1 TPLH1 TPHL2 TPLH2 TTHL TTLH CONDITIONS (NOTE 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND VDD = 5V, VIN = VDD or GND FCL VDD = 5V, VIN = VDD or GND LIMITS MIN MAX UNITS 9 +25oC - 500 ns 10, 11 +125oC, -55oC - 675 ns 9 +25oC - 460 ns 10, 11 +125oC, -55oC - 621 ns 9 +25oC - 200 ns 10, 11 +125oC, -55oC - 270 ns 9 +25oC 2 - MHz 10, 11 +125oC, -55oC 1.48 - MHz MIN MAX UNITS µA NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Input Voltage Low IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VIL VDD = 10V, VOUT = 0.5V 1, 2 VDD = 15V, VOUT = 1.5V 1, 2 VDD = 5V, VOUT = 4.6V 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 1, 2 VDD =15V, VOUT = 13.5V VDD = 10V, VOH > 9V, VOL < 1V 1, 2 1, 2 +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA +125oC - -2.4 mA -55oC - - mA +25oC, +125oC, - 3 V -55oC 7-853 Specifications CD4035BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Input Voltage High VIH CONDITIONS VDD = 10V, VOH > 9V, VOL < 1V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC, 7 - V -55oC 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25o C - 150 ns VDD = 10V 1, 2, 3 +25oC - 200 ns 1, 2, 3 oC - 160 ns o Propagation Delay Clock to Q TPHL1 TPLH1 VDD = 10V Propagation Delay Reset tO Q TPHL2 TPLH2 Transition Time TTHL TTLH Minimum Reset Pulse Width TW Maximum Clock Input Frequency FCL Maximum Clock Rise and Fall Time (Note 4) TRCL TFCL Minimum Data Setup Time J/K Lines TS Minimum Data Setup Time Parallel-In Lines TS Minimum Clock Pulse Width Input Capacitance VDD = 15V VDD = 10V 1, 2, 3 +25 C - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns o - 250 ns o VDD = 5V 1, 2, 3 CIN +25 C VDD = 10V 1, 2, 3 +25 C - 110 ns VDD = 15V 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25oC 6 - MHz VDD = 10V o VDD = 15V 1, 2, 3 +25 C 8 - MHz VDD = 5V 1, 2, 3 +25oC - 15 µs 1, 2, 3 +25 oC - 15 µs VDD = 15V 1, 2, 3 +25oC - 15 µs VDD = 5V 1, 2, 3 +25oC - 220 ns 1, 2, 3 +25oC - 80 ns VDD = 10V VDD = 10V TW +25 o VDD = 15V 1, 2, 3 +25 C - 60 ns VDD = 5V 1, 2, 3 +25oC - 140 ns VDD = 10V 1, 2, 3 +25oC - 50 ns VDD = 15V 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25oC - 200 ns VDD = 5V o VDD = 10V 1, 2, 3 +25 C - 90 ns VDD = 15V 1, 2, 3 +25oC - 60 ns 1, 2 +25oC - 7.5 pF Any Input NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, tRCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V N Threshold Voltage Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP 1, 4 +25oC - ±1 V VSS = 0V, IDD = 10µA 7-854 Specifications CD4035BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Functional F CONDITIONS VDD = 18V, VIN = VDD or GND NOTES TEMPERATURE MIN MAX UNITS 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL Supply Current - MSI-2 Output Current (Sink) Output Current (Source) DELTA LIMIT IDD ± 1.0µA IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D READ AND RECORD IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% parametric, 3% functional; cumulative for static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 1, 13 - 15 2 - 12 16 Static Burn-In 2 Note 1 1, 13 - 15 8 2 - 7, 9 - 12, 16 Dynamic BurnIn Note 1 1, 3, 4 2, 5, 7 - 12 16 1, 13 - 15 8 2 - 7, 9 - 12, 16 Irradiation Note 2 7-855 9V ± -0.5V 50kHz 25kHz 13 - 15 6 - Specifications CD4035BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND 9V ± -0.5V VDD 50kHz 25kHz NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram * * * * 9 10 11 12 *ALL INPUTS PROTECTED BY CMOS INPUT PROTECTION NETWORK * 4 VDD J * 3 K P D P Q D P P Q D D Q Q * 5 R R R R VSS RESET CL Q CL Q CL Q CL Q PS PS PS PS * 6 CLOCK * 7 PARALLEL/ SERIAL CONTROL T * T T T T T T T T p n p n p n p n p n p n p n p n T T T T T T T T T 2 TRUE/COMPLEMENT P/S = 0 = SERIAL MODE T/C = 1= TRUE OUTPUTS 15 14 13 Q2/Q2 Q3/Q3 Q4/Q4 PS P D 1 Q1/Q1 Q ≡ R CL Q p n P PS p n D PS CL p n p n CL CL CL CL Q Q CL p n PS PS CL CL R p n CL PS PS CL CL FIGURE 1. TYPICAL STAGE DETAIL LOGIC 7-856 CD4035BMS AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 15 5V 0 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 1 . TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 2. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS 0 -5 -10 -15 -10V -20 -25 -15V DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 -30 -5 -10V PROPAGATION DELAY TIME (tPHL, tPLH) (ns) TRANSITION TIME (tTHL, tTLH) (ns) SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 20 -15 FIGURE 4. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 200 0 0 -10 -15V AMBIENT TEMPERATURE (TA) = +25oC 50 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 3. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 150 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 30 OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 40 60 80 100 LOAD CAPACITANCE (CL) (pF) AMBIENT TEMPERATURE (TA) = +25oC CLOCKED OPERATION 300 SUPPLY VOLTAGE (VDD) = 5V 200 10V 100 15V 0 FIGURE 5. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 20 40 60 80 LOAD CAPACITANCE (CL) (pF) 100 FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A FUNCTION OF LOAD CAPACITANCE (Q OUTPUT) 7-857 CD4035BMS 106 20 POWER DISSIPATION PER GATE (PD) (µW) MAXIMUM CLOCK INPUT FREQUENCY (fCL) (MHz) Typical Performance Characteristics (Continued) AMBIENT TEMPERATURE (TA) = +25oC LOAD CAPACITANCE (CL) = 50PF 15 10 5 AMBIENT TEMPERATURE (TA) = +25oC 8 6 4 2 105 SUPPLY VOLTAGE (VDD) = 15V 8 6 4 104 2 10V 8 6 4 10V 2 103 5V 8 6 4 CL = 50pF CL = 15pF 2 102 0 2 0 5 10 15 20 SUPPLY VOLTAGE (VDD) (V) FIGURE 7. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 9 LEFT/RIGHT RIGHT SHIFT INPUT CLK T/C RESET LEFT SHIFT OUTPUT 7 4 3 6 2 5 P/S 10 PI-1 11 PI-2 PI-3 2 4 68 2 4 68 2 103 10 102 INPUT FREQUENCY (fI) (kHz) 4 68 2 4 68 104 FIGURE 8. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK INPUT FREQUENCY LEFT SHIFT INPUT 12 4 68 1 Q1 Q2 Q3 Q4 PI-4 J P/S K CL CARRY FORWARD T/C R Q1 1 Q2 15 Q3 14 Q4 13 TRUE/COMP CONTROL IN TRUE MODE VDD RIGHT SHIFT OUTPUT PI-2 PI-3 FIGURE 9. SHIFT LEFT/SHIFT RIGHT REGISTER PI-4 Using Couleur’s Technique (BIDEC)*, a binary number (most significant bit, MSB) first is shifted and processed, such that the BCD equivalent is obtained when the last binary bit is clocked into the register. The CD4035BMS, with the correct conversion logic, can also be used as a BCD-to-binary converter. *NOTE: The basic rule is: If a 4 or less is in a decade, shift with the next clock pulse; if a 5 or greater is in a decade, add 3 and then shift at the next clock pulse. For more information refer to “IRE TRANSACTIONS ON ELECTRONIC COMPUTERS”, Dec. 1958, pages 313-316. FIGURE 10. BIDEC LOGIC 7-858 CD4035BMS VDD 9 7 2 6 4 3 5 10 PI-1 P/S 11 PI-2 Control = E = 0 12 PI-3 Q1 A Q2 B Q3 C Q4 D Q1 A Q2 B Q3 C Q4 D 0 0 0 0 0 15 1 1 1 1 1 1 0 0 0 14 0 1 1 1 2 0 1 0 0 13 1 0 1 1 5 1 0 1 0 10 0 1 0 1 10 0 1 0 1 5 1 0 1 0 4 0 0 1 0 11 1 1 0 1 9 1 0 0 1 6 0 1 1 0 3 1 1 0 0 12 0 0 1 1 6 0 1 1 0 9 1 0 0 1 13 1 0 1 1 2 0 1 0 0 11 1 1 0 1 4 0 0 1 0 7 1 1 1 0 8 0 0 0 1 14 0 1 1 1 1 1 0 0 0 12 0 0 1 1 3 1 1 0 0 8 0 0 0 1 7 1 1 1 0 PI-4 T/C CL 4 STAGE REGISTER J K R Q1 Q2 1 Q3 15 Q4 14 2 3 4 5 1/2 13 2 3 4 5 CD4002 1/2 CD4012 1 “E” CONTROL 1 9,10 11,12 1/2 9,10 11,12 CD4002 1/2 CD4012 13 13 1 2 1/2 CD4030 1 3 5 1/2 4 CD4030 Using a control line (E) two different state sequences can be generated. For example, suppose the following two sequences are desired on command (control line E). 6 FIGURE 11(a). DOUBLE SEQUENCE GENERATOR 9 7 CLOCK 6 4 CARRY INPUT VDD RESET 1 3 2 5 P/S 10 PI-1 11 PI-2 FIGURE 11(b). STATE SEQUENCES 9 12 PI-3 7 PI-4 6 CL 4 J UNITS REGISTER 3 K VDD T/C R Q1 1 Q2 15 Q3 14 2 5 Q4 P/S 10 PI-1 11 PI-2 12 PI-3 CL J TENS REGISTER K T/C R Q1 1 13 Q2 15 Q3 14 BCD UNITS (BIDEC LOGIC) P/S CARRY FORWARD BCD TENS (BIDEC LOGIC) FIG 7 FIG 7 PI-2 TO UNITS REGISTER PI-3 PI-4 PI-2 TO TENS REGISTER PI-3 PI-4 FIGURE 12. BINARY-TO-BCD CONVERTER 7-859 Q4 13 BCD TENS OUT BCD UNITS OUT P/S PI-4 CARRY FORWARD TO NEXT DECADE CD4035BMS Chip Dimensions and Pad Layout Dimensions in parantheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ − 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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