TI ONET4291VARGPRG4 1 gbps to 4.25 gbps multi-rate vcsel driver Datasheet

ONET4291VA
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1 GBPS TO 4.25 GBPS MULTI-RATE VCSEL DRIVER
FEATURES
•
•
•
•
•
•
•
•
•
Multi-Rate Operation from 1 Gbps Up
To 4.25 Gbps
2-Wire Digital Interface
Digitally Selectable Modulation Current
Digitally Selectable Bias Current
Automatic Power Control (APC) Loop
Supports Transceiver Management
System (TMS)
Includes Laser Safety Features
Analog Temperature Sensor Output
Single 3.3-V Supply
•
•
Operating Temperature –40°C to 85°C
Small Footprint Surface Mount 4 mm × 4 mm,
20-Pin QFN Package
APPLICATIONS
•
•
•
Multirate SFP/SFF Modules
1.0625 Gbps, 2.125 Gbps, and 4.25 Gbps Fibre
Channel Transmitters
Gigabit Ethernet Transmitters
DESCRIPTION
The ONET4291VA is a versatile high-speed multi-rate VCSEL driver for fiber optic applications with data rates up
to 4.25 Gbps.
The device provides a 2-wire interface which allows digital control of the modulation and bias currents,
eliminating the need for of external components.
The ONET4291VA includes an integrated automatic power control loop as well as circuitry to support laser safety
and transceiver management systems.
The part is available in a small footprint 4 mm × 4 mm 20-pin QFN package and it requires a single 3.3-V supply.
This power efficient multi-rate VCSEL driver is characterized for operation from –40°C to 85°C ambient
temperature.
BLOCK DIAGRAM
A simplified block diagram of the ONET4291VA is shown in Figure 1.
This compact, low power 1-Gbps to 4.25-Gbps multi-rate VCSEL driver consists of a high-speed current
modulator, a modulation current generator, power-on reset circuitry, a 2-wire interface and control logic block, a
bias current generator and automatic power control loop, and an analog reference block.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
ONET4291VA
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3
VCC
2
GND
60 Ω
60 Ω
GND
VCC
Power-On Reset
DOUT+
RESET
DOUT−
Limiting
Gain Stage
DIN+
100 Ω
DIN−
High-Speed Current Modulator
8
IMOD
MODC
Modulation
Current
Generator
MODR
ENA
8
SCK
SCK
SDA
SDA
DIS
DIS
RESET
MODC
MODR
ENA
2-Wire Interface and Control Logic Clock
ENA
OLE
BIASC
FLT
PDP
FAULT
PDP
FAULT
FLT
8
RZTC
TS
RZTC
TS
Analog Reference
ENA
OLE
BIASC
Bias Current Generator
and Automatic Power
Control Loop (APC)
BIAS
BIAS
MONB
MONB
MONP
MONP
MD
COMP
MD
COMP
B0072-01
Figure 1. Simplified Block Diagram of the ONET4291VA
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HIGH-SPEED CURRENT MODULATOR
The data signal is applied to the high-speed current modulator by means of the input signal pins DIN+/DIN–,
which provide on-chip differential 100-Ω line-termination. The succeeding limiting gain stage ensures sufficient
drive amplitude and edge-speed for driving the current modulator differential pair.
The modulation current is sunk from the common emitter node of the differential pair by means of a modulation
current generator, which is digitally controlled by the 2-wire interface and control logic block.
The collector nodes of the differential pair are connected to the output pins DOUT+/DOUT–, which include
on-chip 2 × 60-Ω back-termination to VCC. The 60-Ω back-termination helps to sufficiently suppress signal
distortion caused by double reflections for VCSEL diodes with impedances ranging from 50 Ω through 75 Ω.
MODULATION CURRENT GENERATOR
The modulation current generator provides the current for the current modulator described above. The circuit is
digitally controlled by the 2-wire interface and control logic block.
An 8-bit wide control bus, MODC, is used to set the desired modulation current.
Furthermore, two modulation current ranges are selected by means of the MODR signal.
The ENA signal enables or disables the modulation current generator.
The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current is
also disabled in a fault condition if the fault detection enable register flag FLTEN is set.
For more information about the register functionality, see the register mapping description.
2-WIRE SERIAL INTERFACE AND CONTROL LOGIC
The ONET4291VA uses a 2-wire serial interface for digital control. A simplified block diagram of this interface is
shown in Figure 2.
The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from a
microprocessor, for example. Both inputs include 100-kΩ pullup resistors to VCC. For driving these inputs, an
open drain output is recommended.
A write cycle consists of a START command, three address bits with MSB first, eight data bits with MSB first,
and a STOP command. In idle mode, both SDA and SCK lines are at a high level.
A START command is initiated by the falling edge of SDA with SCK at a high level, transitioning to a low level.
Bits are clocked into an 11-bit wide shift register during the high level of the system clock SCK.
A STOP command is detected on the rising edge of SDA after SCK has changed from a low to a high level.
At the time of detection of a STOP command, the eight data bits from the shift register are copied to a selected
8-bit register. Register selection occurs according to the three address bits in the shift register, which are
decoded to eight independent select signals using a 3 to 8 decoder block.
In the ONET4291VA, only addresses 0 (000b) through 3 (011b) are used.
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SDA
11 Bit Shift Register
SCK
8 Bits Data
3 Bits Addr
3
8
8
START
000
001
STOP
010
8
8 Bit Register
Modulation Current (8 Bit)
011
100
101
3 to 8 Decoder
Start/Stop
Detector
Logic
8 Bit Register
Control Functions (6 Bit)
Unused (2 Bit)
110
8
111
8 Bit Register
Bias Current (8 Bit)
8
8 Bit Register
Unused (8 Bit)
B0068-02
Figure 2. Simplified 2-Wire Interface Block Diagram
The timing definition for the serial data signal SDA and the serial clock signal SCK is shown in Figure 3.
The corresponding timing requirements are listed in Table 1.
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ONET4291VA
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START
1
0
1
0
1
1
STOP
DTAF
DTAR
DTAHI
DTAWT
SDA
SCK
STRTHLD
DTASTP
CLKR
DTAHLD
CLKF
STOPSTP
CLKHI
T0077-01
Figure 3. 2-Wire Interface Timing Diagram
Table 1. 2-Wire Interface Timing
PARAMETER
DESCRIPTION
MIN
MAX
10
UNIT
STRTHLD
START hold time
Time required from data falling edge to clock falling edge at START
CLKR, DTAR
Clock and data rise time
Clock and data rise time
ns
CLKF, DTAF
Clock and data fall time
Clock and data fall time
CLKHI
Clock high time
Minimum clock high period
50
ns
DTAHI
Data high time
Minimum data high period
100
ns
DTASTP
Data setup time
Minimum time from data rising edge to clock rising edge
10
ns
DTAWT
Data wait time
Minimum time from data falling edge to data rising edge
50
ns
DTAHLD
Data hold time
Minimum time from clock falling edge to data falling edge
10
ns
STOPSTP
STOP setup time
Minimum time from clock rising edge to data rising edge at STOP
10
ns
10
ns
10
ns
REGISTER MAPPING
The register mapping for the register addresses 0 (000b) through 3 (011b) are shown in Table 2 to Table 5.
Register 3 is included for future enhancements. It is not used in the current device.
Table 6 describes the circuit functionality based on the register settings.
Table 2. Register 0 (000b) Mapping
address 0 (000b)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ENA
PDP
PDR
OLE
FLTEN
MODR
–
–
5
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Table 3. Register 1 (001b) Mapping
address 1 (001b)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
MODC7
MODC6
MODC5
MODC4
MODC3
MODC2
MODC1
MODC0
Table 4. Register 2 (010b) Mapping
address 2 (010b)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BIASC7
BIASC6
BIASC5
BIASC4
BIASC3
BIASC2
BIASC1
BIASC0
Table 5. Register 3 (011b) Mapping
address 3 (011b)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
–
–
–
–
–
–
–
–
Table 6. Register Functionality
Symbol
Register
Function
ENA
Enable
Enables chip when set to 1. Can be toggled to reset a fault condition.
PDP
Photodiode polarity
Photodiode polarity bit:
1 = common anode
0 = common cathode
PDR
Photodiode current range
Photodiode current range bit:
1 = 0 µA – 500 µA with 2-µA resolution
0 = 0 µA – 250 µA with 1-µA resolution
OLE
Open loop enable
Open loop enable bit:
1 = open loop bias current control
0 = closed loop bias current control
FLTEN
Fault detection enable
Fault detection enable bit:
1 = fault detection on
0 = fault detection off
MODR
Modulation current range
Laser modulation current range:
1 = 0 mA – 15 mA
0 = 0 mA – 12 mA
MODC7
Modulation current bit 7 (MSB)
Modulation current setting:
MODC6
Modulation current bit 6
MODC5
Modulation current bit 5
MODR = 1 (see above):
MODC4
Modulation current bit 4
Modulation current: 100 µA – 15.4 mA with 68 µA step size
MODC3
Modulation current bit 3
MODC2
Modulation current bit 2
MODR = 0 (see above):
MODC1
Modulation current bit 1
Modulation current: 100 µA – 12 mA with 51 µA step size
MODC0
Modulation current bit 0 (LSB)
BIASC7
Bias current bit 7 (MSB)
closed loop (APC):
BIASC6
Bias current bit 6
Coupling ratio CR between VCSEL bias current and photodiode current is:
BIASC5
Bias current bit 5
CR = IBIAS-VCSEL / IPD
BIASC4
Bias current bit 4
PDR = 0 (see above), BIASC = 0 .. 255, IBIAS-VCSEL≤ 12 mA:
BIASC3
Bias current bit 3
IBIAS-VCSEL = 100 µA + (1 µA × CR × BIASC)
BIASC2
Bias current bit 2
PDR = 1 (see above), BIASC = 0 .. 255, IBIAS-VCSEL≤ 12 mA:
BIASC1
Bias current bit 1
IBIAS-VCSEL = 100 µA + (2 µA × CR × BIASC)
BIASC0
Bias current bit 0 (LSB)
open loop: IBIAS-VCSEL = 100 µA + (47 µA × BIASC)
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BIAS CURRENT GENERATION AND APC LOOP
The bias current generation and APC loop are controlled by means of the 2-wire interface.
In open loop operation, selected by setting OLE = 1 (bit 4 of register 0), the bias current is set directly by the 8-bit
wide control word BIASC[0..7] (register 2).
In automatic power control mode, selected by setting OLE = 0, the bias current depends on the register settings
BIASC[0..7] and the coupling ratio (CR) between the VCSEL bias current and the photodiode current.
CR = IBIAS-VCSEL / IPD.
Two photodiode current ranges can be selected by means of the PDR register (bit 5 of register 0). The
photodiode range should be chosen to keep the laser bias control DAC close to the center of its range. This
keeps the laser bias current setpoint resolution high and the loop settling time constant within specification.
For details regarding the bias current setting in open loop as well as in closed loop mode, see Table 6.
In closed loop mode, the photodiode polarity bit, PDP, must be set for common anode or common cathode
configuration to ensure proper operation. In open loop mode if a photodiode is still present, the photodiode
polarity bit must be set to the opposite setting.
ANALOG REFERENCE
The ONET4291VA is supplied by a single 3.3-V ±10% supply voltage connected to the VCC pins. This voltage is
referenced to ground (GND).
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which
all other internally required voltages and bias currents are derived.
An external zero temperature coefficient resistor must be connected from the RZTC pin of the device to ground
(GND). This resistor is used to generate a precise zero TC current which is used as a reference current for the
on-chip DACs.
In order to minimize the module component count, the ONET4291VA VCSEL driver provides an on-chip
temperature sensor. The output voltage of the temperature sensor is available at the TS pin.
The voltage is VTS = 9.4 mV × TEMP + 1337 mV with TEMP given in °C.
Note that the voltage at TS is not buffered. As a result, TS can only drive capacitive loads.
POWER-ON RESET AND REGISTER LOADING SEQUENCE
The ONET4291VA has power on reset circuitry which ensures that all registers are reset to zero during startup.
After the power-on to initialize time (TINIT1), the internal registers are ready to be loaded. It is important that the
registers are loaded in the following order:
1. Bias current register (register 2, 010b),
2. Modulation current register (register 1, 001b),
3. Control register (register 0, 000b).
The part will be ready to transmit data after the initialize to transmit time TINIT2, assuming that the control register
enable bit ENA is 1 and the disable pin DIS is low.
The ONET4291VA can be disabled using either the ENA control register bit or the disable pin DIS. In both cases
the internal registers are not reset. After the disable pin DIS is de-asserted and/or the enable bit ENA is
re-asserted the part returns to its prior output settings.
LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE
The ONET4291VA provides built in laser safety features. The following fault conditions are detected:
1. Voltage at MONB exceeds 1.2 V,
2. Photodiode current exceeds 150% of its target value,
3. Bias control DAC drops in value by more than 33% in one step.
If one or more fault conditions occur and the fault enable bit FLTEN is set to 1, the ONET4192VA responds by:
1. Setting the VCSEL bias current to zero.
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2. Setting the modulation current to zero.
3. Asserting and latching the FLT pin.
Fault recovery is performed by the following procedure:
1. The disable pin DIS and/or the enable control bit ENA are toggled for at least the fault latch reset time
TRESET.
2. The FLT pin de-asserts while the disable pin DIS is asserted or the enable bit ENA is de-asserted.
3. If the fault condition is no longer present, the part will return to normal operation with its prior output settings
after the disable negate time TON.
4. If the fault condition is still present, FLT re-asserts once DIS is set to low level and the part will not return to
normal operation.
PACKAGE
For the ONET4291VA, a small footprint 4 mm × 4 mm 20-pin QFN package with a lead pitch of 0,5 mm is used.
The pin out is shown in Figure 4.
16
17
18
1
15
2
14
EP
3
13
PD
VCC
CAPC
MONP
MONB
VCC
DIN+
DIN−
VCC
FLT
10
11
9
5
8
12
7
4
6
DIS
RZTC
TS
SCK
SDA
19
20
GND
MOD
MOD+
GND
BIAS
RGP PACKAGE
(TOP VIEW)
P0031-01
Figure 4. Pinout of ONET4291VA in a 4 mm × 4 mm 20-Pin QFN Package
TERMINAL FUNCTIONS
TERMINAL
NO.
8
NAME
TYPE
CMOS-in
DESCRIPTION
1
DIS
2
RZTC
3
TS
4
SCK
CMOS-in
2-wire interface serial clock. Includes a 100-kΩ pullup resistor to VCC.
5
SDA
CMOS-in
2-wire interface serial data input. Includes a 100-kΩ pullup resistor to VCC.
6, 9, 14
VCC
Supply
7
DIN+
Analog-in
Non-inverted data input. On-chip differentially 100-Ω terminated to DIN–. Must be ac coupled.
8
DIN–
Analog-in
Inverted data input. On-chip differentially 100-Ω terminated to DIN+. Must be ac coupled.
10
FLT
CMOS-out
Fault detection flag
11
MONB
Analog-out
Bias current monitor. Sources an 8.3% replica of the bias current. Connect an external resistor to
ground (GND). If the voltage at this pin exceeds 1.2 V a fault is triggered.
Analog
Analog-out
Disables both bias and modulation current when set to high state. Toggle to reset a fault
condition
Connect external zero TC 30-kΩ to ground (GND). Used to generate a defined zero TC reference
current for internal DACs.
Temperature sensor output. Not buffered, capacitive load only.
3.3-V ±10% supply voltage
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TERMINAL FUNCTIONS (continued)
TERMINAL
NO.
NAME
TYPE
DESCRIPTION
12
MONP
Analog-out
Photodiode current monitor. Sources a 50% replica of the photodiode current. Connect an
external resistor to ground (GND).
13
CAPC
Analog
Compensation pin used to control the bandwidth of the APC loop. Connect a 0.01-µF capacitor to
ground.
15
PD
Analog
Monitor photodiode input. The pin can source or sink current dependent on PDP register setting.
Pin supplies >1.5-V reverse bias.
16
BIAS
Analog
VCSEL diode bias current source. Connect to laser anode through inductor. Murata
BLM15HG102SN1 is recommended.
17, 20, EP
GND
Supply
Circuit ground. The exposed die pad (EP) must be grounded.
18
MOD+
CML-out
Non-inverted modulation current output. AC coupled to anode of common cathode VCSEL.
On-chip 60-Ω back-terminated to VCC.
19
MOD–
CML-out
Inverted modulation current output. AC coupled through VCSEL matching resistor to ground
(GND). On-chip 60-Ω back-terminated to VCC.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VALUE / UNIT
VCC
Supply voltage
–0.3 V to 4 V
VDIS, VRZTC, VTS, VSCK, VSDA, VDIN+, Voltage at DIS, RZTC, TS, SCK, SDA, DIN+, DIN–, FLT, MONB, MONP,
VDIN–, VFLT, VMONB, VMONP, VCAPC,
CAPC, PD, BIAS, MOD+, MOD– (2)
VPD, VBIAS, VMOD+, VMOD–
–0.3 V to 4 V
ESD
ESD rating at all pins
TJ,max
Maximum junction temperature
TSTG
Storage temperature range
–65°C to 85°C
TA
Characterized free-air operating temperature range
–40°C to 85°C
TLEAD
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
3 kV (HBM)
125°C
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
CONDITIONS
VCC
Supply voltage
VIH
CMOS input high voltage
DIS, SCK, SDA
VIL
CMOS input low voltage
DIS, SCK, SDA
Bias output headroom voltage
VCC– VBIAS, IBIAS = 10 mA
Photodiode current range
RRZTC
Zero TC resistor value (1)
VIN
Differential input voltage swing
tR-IN
Input rise time
tF-IN
Input fall time
TA
Operating free-air temperature
(1)
MIN
TYP
MAX
2.9
3.3
3.6
2
V
V
0.8
500
V
mV
Control bit PDR = 1, step size = 2 µA
10
500
Control bit PDR = 0, step size = 1 µA
5
250
1.22-V bias across resistor
UNIT
µA
29.7
30
30.3
kΩ
200
800
2400
mVp-p
20%–80%, fBIT = 1.25 Gbps
160
20%–80%, fBIT≥ 2.125 Gbps
100
20%–80%, fBIT = 1.25 Gbps
160
20%–80%, fBIT≥ 2.125 Gbps
100
–40
85
ps
ps
°C
Changing the value alters DAC ranges.
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DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions, all values are for open loop operation, IMOD = 6 mA,
IBIAS = 5 mA, and RRZTC = 30 kΩ, unless otherwise noted
PARAMETER
VCC
TEST CONDITIONS
Supply voltage
MIN
2.9
TYP MAX
3.3
3.6
IMOD = 6 mA, IBIAS = 5 mA, including IMOD and IBIAS
40
45
Disabled, DIS = high and/or control bit ENA = low
22
UNIT
V
IVCC
Supply current
RIN
Data input/output resistance
Differential between DIN+/DIN–
85
100
115
ROUT
Data output/output resistance
Single-ended to VCC
50
60
70
Ω
CMOS input current
SCK, SDA, 100-kΩ pullup to VCC
–50
10
µA
10
µA
CMOS input current
DIS
–10
VOH
CMOS output high voltage
FLT, ISINK = 1 mA
2.5
VOL
CMOS output low voltage
FLT, ISOURCE = 1 mA
IBIAS-DIS
Bias current during disable
IBIAS-MIN
Minimum bias current
See
IBIAS-MAX
Maximum bias current
DAC set to maximum, closed loop
8.5
DAC set to maximum, open loop
11
Photodiode reverse bias voltage
APC active, IPD = max
1.5
Photodiode fault current level
Percent of target IPD (2)
Temperature sensor voltage range
–40°C to 120°C junction temperature. Capacitive load
only. After mid-scale calibration.
Temperature sensor accuracy
Mid scale calibration
Temperature sensor drive current
Source or sink (2)
Photodiode current monitor ratio
IMONP / IPD, IBIAS > 100 µA
45%
60%
80%
Bias current monitor ratio
IMONB / IBIAS (nominal 1/12 = 8.3%)
6.7%
8.3%
10%
VCC-RST
VCC reset threshold voltage
VCC voltage level which triggers power-on reset
2.4
2.6
2.85
VCCRSTHYS
VCC reset threshold voltage
hysteresis
VMONB-FLT
Fault voltage at MONB
VPD
VTS
ITS
(1)
(2)
mA
Ω
V
0.5
(1)
V
100
µA
0.2
mA
mA
2.1
V
150%
0.8
2.5
V
10
µA
±3
–10
°C
V
120
Fault occurs if voltage at MONB exceeds value
1.05
1.2
mV
1.45
V
The bias current can be set below the specified minimum according to the corresponding register setting described in the register
mapping section above, however in closed loop operation settings below the specified value may trigger a fault.
Assured by simulation over process, supply, and temperature variation.
AC ELECTRICAL CHARACTERISTICS
over recommended operating conditions with 50-Ω output load, open loop operation, IMOD = 6 mA, IBIAS = 5 mA, and
RRZTC = 30 kΩ (unless otherwise noted)
MIN TYP (1)
MAX
20%–80%, tR-IN = 160 ps, single-ended VIN > 400 mVpp
60
125
20%–80%, tR-IN = 100 ps, single-ended VIN > 400 mVpp
35
100
20%–80%, tF-IN = 160 ps, single-ended VIN > 400 mVpp
60
125
20%–80%, tF-IN = 100 ps, single-ended VIN > 400 mVpp
35
100
PARAMETER
TEST CONDITIONS
tR-OUT
Output rise time
tF-OUT
Output fall time
IMOD-MAX
Maximum modulation current
IMOD-STEP
Modulation current step size
DJ
Deterministic output jitter
fBIT = 4.25 Gbps, excluding DJ caused by duty cycle
distortion
7
DCD
Duty cycle distortion
fBIT = 4.25 Gbps
8
(1)
10
Control bit MODR = 1, 50-Ω load
11.5
Control bit MODR = 0, 50-Ω load
9
ps
ps
mA
Control bit MODR = 1, 50-Ω load
68
Control bit MODR = 0, 50-Ω load
51
Typical operating condition is at VCC = 3.3 V and TA = 25°C.
UNIT
µA
20
psp-p
psp-p
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AC ELECTRICAL CHARACTERISTICS (continued)
over recommended operating conditions with 50-Ω output load, open loop operation, IMOD = 6 mA, IBIAS = 5 mA, and
RRZTC = 30 kΩ (unless otherwise noted)
PARAMETER
MIN TYP (1)
TEST CONDITIONS
τAPC
APC time constant
CAPC 0.01 µF, IPD = 100 µA, PD coupling ratio
CR = 1/40 (2)
TOFF
Transmitter disable time
Rising edge of DIS to IBIAS≤ 0.1 x IBIAS-NOMINAL (2)
TON
Disable negate time
Falling edge of DIS to IBIAS≥ 0.9 x IBIAS-NOMINAL
TINIT1
Power-on to initialize
Power-on to registers ready to be loaded
TINIT2
Initialize to transmit
Register load STOP command to part ready to transmit
valid data (2)
TRESET
DIS pulse width
Time DIS must held high to reset part (2)
TFAULT
Fault assert time
Time from fault condition to FLT high (2)
(2)
MAX
UNIT
µs
200
2.4
5
µs
1
ms
20
250
ms
2
ms
50
µs
(2)
100
ns
Assured by simulation over process, supply, and temperature variation.
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ONET4291VA
www.ti.com
SLLS674 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
BIAS-MONITOR CURRENT IMONB
vs
BIAS CURRENT
DETERMINISTIC JITTER
vs
MODULATION CURRENT
1.0
16
14
0.8
Deterministic Jitter − psPP
IMONB − Bias-Monitor Current − mA
0.9
0.7
0.6
0.5
0.4
0.3
12
10
8
6
4
0.2
2
0.1
0.0
0
0
2
4
6
8
10
12
0
2
Bias Current − mA
8
10
Figure 5.
Figure 6.
RANDOM JITTER
vs
MODULATION CURRENT
RANDOM JITTER
vs
TEMPERATURE
3.0
3.0
2.5
2.5
2.0
1.5
1.0
0.5
12
14
16
G002
Random Jitter − psrms
Random Jitter − psrms
6
Modulation Current − mA
G001
2.0
1.5
1.0
0.5
0.0
0
2
4
6
8
10
12
14
16
Modulation Current − mA
G003
Figure 7.
12
4
0.0
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
Figure 8.
80
100
G004
ONET4291VA
www.ti.com
SLLS674 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
RISE-TIME AND FALL-TIME
vs
MODULATION CURRENT
BIAS CURRENT IN OPEN LOOP MODE
vs
BASIC REGISTER SETTING
50
14
45
12
35
Open Loop Bias Current − mA
tt − Transition Time − ps
40
Rise Time
30
25
Fall Time
20
15
10
10
8
6
4
2
5
0
0
0
2
4
6
8
10
12
14
16
0
Modulation Current − mA
2
4
6
8
10
12
14
Bias Current Register Setting − mA
G005
G006
Figure 9.
Figure 10.
MODULATION CURRENT
vs
MODC REGISTER SETTING
SUPPLY CURRENT
vs
TEMPERATURE
50
16
14
12
Supply Current − mA
Modulation Current − mA
45
10
8
6
40
35
30
4
25
2
0
0
2
4
6
8
10
12
14
16
Modulation Current Register Setting − mA
G007
Figure 11.
20
−40
−20
0
20
40
60
TA − Free-Air Temperature − °C
80
100
G008
Figure 12.
13
ONET4291VA
www.ti.com
SLLS674 – SEPTEMBER 2005
TYPICAL CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
EYE-DIAGRAM AT 4.25 GBPS
K28.5 PATTERN, IMOD = 10 mA
Single-Ended Output Voltage − 60 mV/Div
Single-Ended Output Voltage − 100 mV/Div
EYE-DIAGRAM AT 4.25 GBPS
K28.5 PATTERN, IMOD = 5 mA
t − Time − 40 ps/Div
t − Time − 40 ps/Div
G010
G009
Figure 14.
EYE-DIAGRAM AT 4.25 GBPS
K28.5 PATTERN, IMOD = 15 mA
EYE-DIAGRAM AT 1.0625 GBPS
K28.5 PATTERN, IMOD = 15 mA
Single-Ended Output Voltage − 150 mV/Div
Single-Ended Output Voltage − 150 mV/Div
Figure 13.
t − Time − 157 ps/Div
t − Time − 40 ps/Div
G012
G011
Figure 15.
14
Figure 16.
ONET4291VA
www.ti.com
SLLS674 – SEPTEMBER 2005
APPLICATION INFORMATION
Figure 17 shows a typical application circuit using the ONET4291VA with a common cathode VCSEL connected
to ground.
The VCSEL driver is controlled via the 2-wire interface SDA/SCK by a microprocessor.
In a typical application, the FLT, MONB, MONP, and TS outputs are connected to the microcontroller for
transceiver management purposes.
The component values in Figure 17 are typical examples and may be varied according to the intended
application.
DIS
SDK
TS
RZTC
SDA
C1
0.1 µF
DIS
RZTC
TS
SCK
SDA
30 kΩ
VCC
GND
DIN+
DIN+
MOD−
DIN−
DIN−
PD
BIAS
VCC
FLT
CAPC
GND
MONP
50 Ω
MOD+
VCC
MONB
C2
0.1 µF
ONET4291VA
20-Lead QFN
C3
0.1 µF
C4
0.1 µF
L1
BLM15HG102SN1
VCSEL
Laserdiode
VCC
Monitor
Photodiode
FLT
MONP
RMONB
1 kΩ
RMONP
10 kΩ
MONB
C5
0.01 µF
S0100-01
Figure 17. Basic Application Circuit With a Common Cathode VCSEL
15
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
ONET4291VARGPR
ACTIVE
QFN
RGP
20
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
ONET
4291V
ONET4291VARGPRG4
ACTIVE
QFN
RGP
20
2500
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
ONET
4291V
ONET4291VARGPT
ACTIVE
QFN
RGP
20
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
ONET
4291V
ONET4291VARGPTG4
ACTIVE
QFN
RGP
20
250
Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR
& no Sb/Br)
-40 to 85
ONET
4291V
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
ONET4291VARGPR
QFN
RGP
20
2500
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
ONET4291VARGPT
QFN
RGP
20
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ONET4291VARGPR
QFN
RGP
20
2500
367.0
367.0
35.0
ONET4291VARGPT
QFN
RGP
20
250
210.0
185.0
35.0
Pack Materials-Page 2
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