ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO Description Features The ICS722 is a low cost, low-jitter, high-performance 3.3 volt VCXO designed to replace expensive discrete VCXOs modules. The on-chip Voltage Controlled Crystal Oscillator accepts a 0 to 3.3 V input voltage to cause the output clocks to vary by over ±100 ppm. Using ICS’ patented VCXO techniques, the device uses an inexpensive external pullable crystal in the range of 16.2 to 28 MHz to produce a VCXO output clock at that same frequency. • • • • Packaged in 8-pin SOIC • • • • VCXO tuning voltage of 0 to 3.3 V The frequency of the on-chip VCXO is adjusted by an external control voltage input into pin VIN. Because VIN is a high-impedance input, it can be driven directly from an PWM RC integrator circuit. Frequency output increases with VIN voltage input. The usable range of VIN is 0 to 3.3 V. Operational frequency range of 16.2 MHz to 28 MHz Uses an inexpensive external crystal On-chip patented VCXO with pull range of 230 ppm (minimum) Operating voltage of 3.3 V 12 mA output drive capability at TTL levels Advanced, low-power, sub-micron CMOS process ICS manufactures the largest variety of Set-Top Box and multimedia clock synthesizers for all applications. Consult ICS to eliminate VCXOs, crystals, and oscillators from your board. Block Diagram VDD VIN X1 Voltage Controlled Crystal Oscillator 16.2-28MHz Pullable Crystal X2 16.2-28MHz Clock (REFOUT) GND 1 MDS 722 A I n t e gra te d C i r c u i t S y s t e m s ● 525 Race Stre et, San Jo se, CA 9 5126 Revision 121404 ● te l (40 8) 2 97-12 01 ● w w w. i c st . c o m ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO Pin Assignment X1 1 8 X2 VDD 2 7 DC VIN 3 6 DC GND 4 5 REFOUT ICS722 8-Pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 XI Input Crystal connection. Connect to the external pullable crystal. 2 VDD Power Connect to +3.3 V (0.01µf decoupling capacitor recommended). 3 VIN Input Voltage input to VCXO. Zero to 3.3 V signal which controls the VCXO frequency. 4 GND Power Connect to ground. 5 REFOUT Output VCXO CMOS level clock output matches the nominal frequency of the crystal. 6 DC — Do not connect anything to this pin. 7 DC — Do not connect anything to this pin. 8 X2 Input Crystal connection. Connect to a external pullable crystal. 2 MDS 722 A In te grated Circuit Systems Pin Description ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121404 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO External Component Selection variable load capacitors that “pull” (change) the frequency of the crystal. The crystal specified for use with the ICS722 is designed to have zero frequency error when the total of on-chip + stray capacitance is 14 pF. The ICS722 requires a minimum number of external components for proper operation. Decoupling Capacitors A decoupling capacitor of 0.01µF should be connected between VDD and GND on pins 2 and 4 as close to the ICS722 as possible. For optimum device performance, the decoupling capacitor should be mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit. Series Termination Resistor When the PCB trace between the clock output and the load is over 1 inch, series termination should be used. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. Recommended Crystal Parameters: Initial Accuracy at 25°C Temperature Stability Aging Load Capacitance Shunt Capacitance, C0 C0/C1 Ratio Equivalent Series Resistance ±20 ppm ±30 ppm ±20 ppm 14 pf 7 pF Max 250 Max 35 Ω Max The external crystal must be connected as close to the chip as possible and should be on the same side of the PCB as the ICS722. There should be no via’s between the crystal pins and the X1 and X2 device pins. There should be no signal traces underneath or close to the crystal. See application note MAN05. Crystal Tuning Load Capacitors Quartz Crystal The ICS722 VCXO function consists of the external crystal and the integrated VCXO oscillator circuit. To assure the best system performance (frequency pull range) and reliability, a crystal device with the recommended parameters (shown below) must be used, and the layout guidelines discussed in the following section shown must be followed. The crystal traces should include pads for small fixed capacitors, one between X1 and ground, and another between X2 and ground. Stuffing of these capacitors on the PCB is optional. The need for these capacitors is determined at system prototype evaluation, and is influenced by the particular crystal used (manufacture and frequency) and by PCB layout. The typical required capacitor value is 1 to 4 pF. The oscillation frequency of a quartz crystal is determined by its “cut” and by the load capacitors connected to it. The ICS722 incorporates on-chip The procedure for determining the value of these capacitors can be found in application note MAN05. 3 MDS 722 A In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121404 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS722. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Typ. Max. Units 0 – +70 °C +3.45 V Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) +3.15 Reference crystal parameters Refer to page 3 DC Electrical Characteristics VDD=3.3 V ±5% , Ambient temperature 0 to +70°C, unless stated otherwise Parameter Symbol Conditions Operating Voltage VDD Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Output High Voltage (CMOS Level) VOH IOH = -4 mA Operating Supply Current IDD No load Short Circuit Current IOS VIN, VCXO Control Voltage VIA Typ. 3.15 ● Units 3.45 V V 0.4 VDD-0.4 V V 6 mA ±50 mA 0 525 Ra ce Street, San Jose, CA 9512 6 Max. 2.4 3.3 4 MDS 722 A In te grated Circuit Systems Min. V Revision 121404 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO AC Electrical Characteristics VDD = 3.3 V ±5%, Ambient Temperature 0 to +70° C, unless stated otherwise Parameter Symbol Output Frequency FO Crystal Pullability FP VCXO Gain Conditions Min. Typ. Max. Units 16.2 0V< VIN < 3.3 V, Note 1 28 MHz + 115 VIN = VDD/2 + 1 V, Note 1 ppm 120 ppm/V Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 1.5 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 1.5 ns Output Clock Duty Cycle tD Measured at 1.4 V, CL=15 pF 60 % Maximum Output Jitter, short term tJ CL=15 pF 40 50 110 ps Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Symbol Min. Max. Units Still air 150 °C/W θJA 1 m/s air flow 140 °C/W θJA 3 m/s air flow 120 °C/W 40 °C/W θJC Marking Diagram (ICS722MLF) 8 5 5 722MLF ###### YYWW ICS722M ###### YYWW 1 Typ. θJA Marking Diagram (ICS722M) 8 Conditions 1 4 4 Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. “LF” denotes Pb (lead) free package. 4. Bottom marking: (origin) Origin = country of origin if not USA. 5 MDS 722 A In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121404 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS722 LOW COST 27 MHZ 3.3 VOLT VCXO Package Outline and Package Dimensions (8-pin SOIC) Package dimensions are kept current with JEDEC Publication No. 95 8 E Symbol Millimeters Min Max Inches Min Max A A1 B C D E e H h L a 1.35 1.75 1.10 0.25 0.33 0.51 0.19 0.25 4.80 5.00 3.80 4.00 1.27 Basic 5.80 6.20 0.25 0.50 0.40 1.27 8° 0° 0.0532 0.0688 0.0040 0.0098 0.013 0.020 0.0075 0.0098 .1890 .1968 0.1497 0.1574 0.050 Basic 0.2284 0.2440 0.010 0.020 0.016 0.050 0° 8° H INDEX AREA 1 2 D A h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number ICS722M ICS722MT ICS722MLF ICS722MLFT Marking Shipping Packaging Package Temperature see page 5 Tubes Tape and Reel Tubes Tape and Reel 8-pin SOIC 8-pin SOIC 8-pin SOIC 8-pin SOIC 0 to +70° C 0 to +70° C 0 to +70° C 0 to +70° C “LF” denotes Pb (lead) free package. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 722 A In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121404 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m