EMLSI EMC646SP16KZ-10L 4mx16 bit cellularram ad-mux Datasheet

Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Document Title
4Mx16 bit CellularRAM AD-MUX
Revision History
Revision No.
0.0
History
Initial Draft
Draft Date
Remark
July 13,2007
Preliminary
Emerging Memory & Logic Solutions Inc.
4F Korea Construction Financial Cooperative B/D, 301-1 Yeon-Dong, Jeju-Si, Jeju-Do, Rep.of Korea
Tel : +82-64-740-1700 Fax : +82-64-740-1749~1750 / Homepage : www.emlsi.com
Zip Code : 690-717
1
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to
your questions about device. If you have any questions, please contact the EMLSI office.
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
x16 Burst, Multiplexed Address/Data
FEATURES
- 16-bit multiplexed address/data bus
- Sigle device supports asynchrous and burst operation
- Vcc, VccQ voltages:
1.7V.1.95V VCC
1.7V.1.95V VCCQ
- Random access time: 70ns
- Burst mode READ and WRITE access:
4, 8, 16, or 32 words, or continuous burst
Burst wrap or sequential
Max clock rate: 104 MHz (tCLK = 9.62ns) , 133MHz(tCLK = 7.5ns)
Burst initial latency: 38.5ns (4 clocks) @ 104 MHz ,
37.5ns(5 clocks) @ 133 MHz
tACLK: 7ns @ 104 MHz , 5.5ns @ 133 MHz
- Low power consumption:
Asynchronous READ: <25mA
Initial access, burst READ:
(38.5ns [4 clocks] @ 104 MHz) <35mA
Continuous burst READ: <30mA
Initial access, burst READ:
(37.5ns [5 clocks] @ 133 MHz) <40mA
Continuous burst READ: <35mA
- Low-power features
On-chip temperature compensated self refresh (TCSR)
Partial array refresh (PAR)
- Operating temperature range:
Wireless -30°C to +85°C
OPTIONS
- Configuration: 64Mb (4 megabit x 16)
- Vcc core / VccQ I/O voltage supply: 1.8V
- Timing: 70ns access
- Frequency: 83 MHz, 104 MHz, 133 MHz
- Standby current at 85°C
Low Low Power : 140µA(max)
Low Power
: 160µA(max)
Standard
: 180µA(max)
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Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Table of Contents
Features..............................................................................................................................................................................................
Options...........................................................................................................................................................................................
General Description............................................................................................................................................................................
Functional Description........................................................................................................................................................................
Power-Up Initialization....................................................................................................................................................................
Bus Operating Modes.........................................................................................................................................................................
Asynchronous Mode.......................................................................................................................................................................
Burst Mode Operation....................................................................................................................................................................
Mixed-Mode Operation ..................................................................................................................................................................
WAIT Operation .............................................................................................................................................................................
LB# / UB# Operation......................................................................................................................................................................
Low-Power Operation......... ...............................................................................................................................................................
Standby Mode Operation ...............................................................................................................................................................
Temperature Compensated Refresh..............................................................................................................................................
Partial Array Refresh .....................................................................................................................................................................
Registers.............................................................................................................................................................................................
Access Using CRE ........................................................................................................................................................................
Software Access ............................................................................................................................................................................
Bus Configuration Register.............................................................................................................................................................
Burst Length (BCR[2:0]) Default = Continuous Burst ................................................................................................................
Burst Wrap (BCR[3]) Default = No Wrap ...................................................................................................................................
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ......................................................................................
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH..............................................................................................................
Initial Access Latency (BCR[14]) Default = Variable..................................................................................................................
Operating Mode (BCR[15]) Default = Asynchronous Operation................................................................................................
Refresh Configuration Register......................................................................................................................................................
Device Identification Register.........................................................................................................................................................
Electrical Characteristics....................................................................................................................................................................
Timing Requirements..........................................................................................................................................................................
Timing Diagrams.................................................................................................................................................................................
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Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
List of Figures
Figure 1:
Figure 2:
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Figure 11:
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Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Functional Block Diagram - 4 Meg x 16 .............................................................................................................................
Power-Up Initialization Timing ...........................................................................................................................................
READ Operation ................................................................................................................................................................
WRITE Operation ..............................................................................................................................................................
Burst Mode READ(4-word burst)........................................................................................................................................
Burst Mode WRITE (4-word burst)......................................................................................................................................
Refresh Collision During Variable-Latency READ Operation .............................................................................................
Wired-OR WAIT Configuration ...........................................................................................................................................
Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation ..........................................
Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation ............................................
Register READ, Asynchronous Mode, Followed by READ ARRAY Operation ..................................................................
Register READ, Synchronous Mode, Followed by READ ARRAY Operation ....................................................................
Load Configuration Register ..............................................................................................................................................
Read Configuration Register .............................................................................................................................................
Bus Configuration Register Definition ................................................................................................................................
WAIT Configuration During Burst Operation ......................................................................................................................
Latency Counter (Variable Initial Latency, No Refresh Collision) .......................................................................................
Latency Counter (Fixed Latency) .......................................................................................................................................
Refresh Configuration Register Mapping ...........................................................................................................................
AC Input / Output Reference Waveform ............................................................................................................................
AC Output Load Circuit ......................................................................................................................................................
Initialization Period ............................................................................................................................................................
Asynchronous READ .........................................................................................................................................................
Single-Access Burst READ Operation - Variable Latency .................................................................................................
4-Word Burst READ Operation - Variable Latency .............................................................................................................
Single-Access Burst READ Operation - Fixed Latency ......................................................................................................
4-Word Burst READ Operation - Fixed Latency .................................................................................................................
Burst READ Terminate at End-of-Row (Wrap off) ..............................................................................................................
Burst READ Row Boundary Crossing ................................................................................................................................
Asynchronous WRITE .......................................................................................................................................................
Burst WRITE Operation - Variable Latency Mode .............................................................................................................
Burst WRITE Operation - Fixed Latency Mode ..................................................................................................................
Burst WRITE Terminate at End-of-Row (Wrap off) ............................................................................................................
Burst WRITE Row Boundary Crossing ..............................................................................................................................
Burst WRITE Followed by Burst READ ..............................................................................................................................
Asynchronous WRITE Followed by Burst READ ...............................................................................................................
Burst READ Followed by Asynchronous WRITE ...............................................................................................................
Asynchronous WRITE Followed by Asynchronous READ .................................................................................................
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Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Signal Descriptions .........................................................................................................................................................
Bus Operations ...............................................................................................................................................................
Sequence and Burst Length ...........................................................................................................................................
Drive Strength .................................................................................................................................................................
Variable Latency Configuration Codes.............................................................................................................................
Fixed Latency Configuration Codes.................................................................................................................................
Address Patterns for PAR(RCR[4] =1).............................................................................................................................
Device Identification Register Mapping ...........................................................................................................................
Absolute Maximum Ratings ............................................................................................................................................
Electrical Characteristics and Operating Conditions .......................................................................................................
Capacitance ....................................................................................................................................................................
Asynchronous READ Cycle Timing Requirements .........................................................................................................
Burst READ Cycle Timing Requirements ........................................................................................................................
Asynchronous WRITE Cycle Timing Requirements ........................................................................................................
Burst WRITE Cycle Timing Requirements ......................................................................................................................
Initialization Timing Parameters ......................................................................................................................................
5
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36
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
GENERAL DESCRIPTION
64M CellularRAM products are high-speed, CMOS pseudo-static random access memory developed for low-power, portable
applications. The 64Mb CellularRAM device has a DRAM core organized as 4 Meg x 16 bits. These devices are a variation of the
industry-standard Flash control interface, with a multiplexed address/data bus. The multiplexed address and data functionality
dramatically reduce the required signal count, and increases read/write bandwidth. For seamless operation on a burst Flash bus, 64M
CellularRAM products incorporate a transparent self refresh mechanism. The hidden refresh requires no additional support from the
system memory controller and has no significant impact on device READ/WRITE performance. Two user accessible control registers
define device operation. The bus configuration register (BCR) defines how the 64M CellularRAM device interacts with the system
memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh configuration register (RCR) is used to
control how refresh is performed on the DRAM array. These registers are automatically loaded with default settings during power-up and
can be updated anytime during normal operation. Special attention has been focused on standby current consumption during self
refresh. 64M CellularRAM products include two mechanisms to minimize standby current. Partial array refresh (PAR) enables the
system to limit refresh to only that part of the DRAM array that contains essential data. Temperature compensated self refresh (TCSR)
uses an onchip sensor to adjust the refresh rate to match the device temperature-the refresh rate decreases at lower temperatures to
minimize current consumption during standby. The system configurable refresh mechanisms are accessed through the RCR. This 64M
CellularRAM specification defines the industry-standard CellularRAM1.5 x16 A/D Mux feature set established by the CellularRAM
Workgroup. It includes support for both variable and fixed latency, with three output-device drive-strength settings, a variety of wrap
options, and a device ID register (DIDR).
Figure 1: FUNTIONAL BLOCK DIAGRAM - 4 meg x 16
A[21:16]
Address Decode
Logic
4,096K x 16
DRAM
MEMORY
ARRAY
Refresh Configuration
Register (RCR)
Input
Output
MUX
and
Buffers
A/DQ[7:0]
A/DQ[15:8]
Device ID Register
(DIDR)
Bus Configuration
Register (BCR)
CLK
CE#
WE#
OE#
ADV#
CRE
LB#
UB#
WAIT
Control
Logic
Internal
External
Note: Functional block diagrams illustrate simplified device operation. See pin descriptions; Bus operations table; and timing diagrams for detailed information.
6
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Table 1: SIGNAL DESCRIPTIONS
Symbol
Type
Descriptions
A[21:16]
Input
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are internally latched
during READ and WRITE cycles. The address lines are also used to define the value to be loaded into the
BCR or the RCR.
CLK
(note1)
Input
Clock: Synchronizes the memory to the system operating frequency during synchronous operations. When
configured for synchronous operation, the address is latched on the first rising CLK edge when ADV# is
active. CLK must be static (HIGH or LOW) during asynchronous access READ and WRITE operations
when burst mode is enabled.
ADV#
(note1)
Input
Address valid: Indiates that a valid address is present on the address inputs. Addresses are latched on the
rising edge of ADV# during asynchronous READ and WRITE operations.
CRE
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR, and READ
operations access the RCR, BCR, or DIDR.
CE#
Input
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into
standby mode.
OE#
Input
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output buffers are disabled.
WE#
Input
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a WRITE to either a
configuration register or to the memory array.
LB#
Input
Lower byte enable. DQ[7:0]
UB#
Input
Upper byte enable. DQ[15:8]
Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for address, these pins
A/DQ[15:0] Input/Output behave as A[15:0]. A[0] is the LSB of the 16-bit word address within the CellularRAM device. Address,
RCR, and BCR values are loaded with ADV# LOW. Data is input or output when ADV# is HIGH.
Wait: Provides data-valid feedback during burst READ and WRITE operations. WAIT is used to arbitrate
collisions between refresh and READ/WRITE operations. WAIT is also asserted at the end of row unless
wrapping within the burst length. Wait should be ignored during asynchronous operations. WAIT is High-Z
when CE# is HIGH.
WAIT
(note1)
Output
RFU
-
VCC
Supply
Device power supply: (1.70V.1.95V) Power supply for device core operation.
VCCQ
Supply
I/O power supply: (1.70V.1.95V) Power supply for input/output buffers.
VSS
Supply
VSS must be connected to ground.
VSSQ
Supply
VSSQ must be connected to ground.
Reserved for future use.
Note:
1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous mode operations.
7
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Table 2: BUS OPERATIONS
Asynchfonous Mode
BCR[15]=1
Power
CE#
OE#
WE#
CRE
UB#/
LB#
WAIT2
DQ[15:0]
Notes
Read
Active
X
L
L
H
L
L
Low-z
Data out
4
Write
Active
X
L
X
L
L
L
High-z
Data in
4
Standby
Standby
H or L
X
H
X
X
L
X
High-z
High-z
5, 6
No operation
Idle
X
X
L
X
X
L
X
Low-z
X
4, 6
Configuration register
write
Active
X
L
H
L
H
X
Low-z
High-z
Configuration register
read
Active
X
L
L
H
H
L
Low-z
Config.
Reg.out
Burst Mode
BCR[15]=0
Power
CE#
OE#
WE#
CRE
UB#/
LB#
WAIT
DQ[15:0]
Notes
Async read
Active
H or L
L
L
H
L
L
Low-z
Data out
4, 7
Async write
Active
H or L
L
X
L
L
L
Low-z
Data in
4
Standby
Standby
H or L
X
H
X
X
L
X
High-z
High-z
5, 6
No operation
Idle
H or L
X
L
X
X
L
X
Low-z
X
4, 6
Initial burst read
Active
L
L
X
H
L
L
Low-z
Address
4, 8
Initial burst write
Active
L
L
H
L
L
X
Low-z
Address
4, 8
Burst continue
Active
H
L
X
X
X
L
Low-z
Data out
or
Data in
4, 8
Configuration register
write
Active
L
L
H
L
H
X
Low-z
High-z
8, 9
Configuration register
read
Active
L
L
L
H
H
L
Low-z
Config.
Reg.out
8, 9
CLK ADV#
CLK ADV#
Note:
1. With burst mode enabled, CLK must be static(HIGH or LOW) during asynchronous READs and asynchronous WRITEs and to achieve standby power
during standby mode.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only UB# is
in the select mode, DQ[15:8] are enabled.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VCCQ or 0V; all device pins must be static (unswitched) in order to achieve standby current.
7. When the BCR is configured for sync mode, sync READ and WRITE, and async WRITE are supported by EMLSI
8. Burst mode operation is initialized through the bus configuration register (BCR[15]).
9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as indicated
by WAIT).
8
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
FUNTIONAL DESCRIPTION
In general, 64M CellularRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in low-power,
portable applications. The 64Mb device contains a 67,108,864-bit DRAM core, organized as 4,194,304 addresses by 16 bits.The device
implement a multiplexed address/data bus. This multiplexed configuration supports greater bandwidth through the x16 data bus, yet still
reduces the required signal count. The 64M CellularRAM bus interface supports both asynchronous and burst mode transfers.
POWER-UP INITIALIZATION
64M CellularRAM products include an on-chip voltage sensor used to launch the power-up initialization process. Initialization will
configure the BCR and the RCR with their default settings. VCC and VCCQ must be applied simultaneously. When they reach a stable
level at or above 1.7V, the device will require 150µs to complete its self-initialization process. Until the end of tPU, CE# should track
VccQ and remain HIGH. When initialization is complete, the device is ready for normal operation.
Figure 2: Power-Up Initialization Timing
Vcc=1.7V
t
Vcc
VccQ
PU
Device Initialization
9
Device ready for
normal operation
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
BUS OPERATING MODES
64M CelluarRAM products incorporate a burst mode interface found on Flash products targeting low-power, wireless applications. This
bus interface supports asynchronous and burst mode read and write transfers. The specific interface supported is defined by the value
loaded into the BCR.
Asynchronous Mode
Asynchronous mode uses the industry- standard SRAM control signals (CE#, ADV#, OE#, WE#, and LB#/UB#). READ operations(Figure 3 on page 11) are initiated by bringing CE#, ADV#, and LB#/UB# LOW while keeping OE# and WE# HIGH, and driving the address
onto the A/DQ bus. ADV# is taken HIGH to capture the address, and OE# is taken LOW. Valid data will be driven out of the I/Os after the
specified access time has elapsed. WRITE operations(Figure 4 on page 11) occur when CE#, ADV#, WE#, and LB#/UB# are driven
LOW. with the address on the A/DQ bus. ADV# is taken HIGH to capture the address, then the WRITE data is driven onto the bus. During asynchronous WRITE operations, the OE# level is a “Don't Care,” and WE# will override OE#; however, OE# must be HIGH while
the address is driven onto the A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or LB# (whichever
occurs first). During asynchronous operations with burst mode enabled, the CLK input must be held static(HIGH or LOW). WAIT will be
driven during asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM.
10
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 3: READ Operation
A[21:16]
Valid
Address
CE#
OE#
WE#
A/DQ[15:0]
Valid
Address
Valid
Data
High-Z
ADV#
LB#/UB#
Don’t Care
Figure 4: WRITE Operation
A[21:16]
Valid
Address
CE#
OE#
tCEM
WE#
A/DQ[15:0]
Valid
Data
Valid
Address
ADV#
LB#/UB#
Don’t Care
11
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a multi-clock
sequence that must be performed in an ordered fashion. After CE# goes LOW, the address to access is latched on the rising edge of the
next clock that ADV# is LOW. During this first clock rising edge, WE# indicates whether the operation is going to be a READ (WE# =
HIGH, Figure 5) or WRITE (WE# = LOW, Figure 6 on page 13).
Figure 5: Burst Mode READ (4-word burst)
CLK
A[21:16]
Address
Address
ADV#
Latency Code 2(3 clocks)
CE#
OE#
WE#
LB#/UB#
A/DQ[15:0]
Address
D0
D1
D2
D3
Address
WAIT
READ Burst Identified
(WE# = HIGH)
READ Burst Identified
(WE# = HIGH)
Don’t Care
Note:
Non-default BCR settings for burst mode READ (4-word burst): Fixed or variable latency;
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Diagram in the figure above is representative of variable latency with no refresh collision or fixed-latency access.
12
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 6: Burst Mode WRITE (4-word burst, OE# HIGH)
CLK
A[21:16]
Address
Address
ADV#
Latency Code 2(3 clocks)
CE#
WE#
LB#/UB#
A/DQ[15:0]
Address
D0
D1
D3
D2
Address
WAIT
WRITE Burst Identified
(WE# = LOW)
WRITE Burst Identified
(WE# = LOW)
Don’t Care
Note: Non-default BCR settings for burst mode WRITE (4-word burst): Fixed or variable latency;
latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of four, eight, sixteen, or thirty-two
words. Continuous bursts have the ability to start at a specified address and burst to the end of the address. It goes back to the first address and
continues to burst when continuous bursts meet the end of address.
The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is transferred between the processor and
CellularRAM device. The initial latency for READ operations can be configured as fixed or variable (WRITE operations always use fixed latency). Variable
latency allows the CellularRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to detect any conflict
with refresh cycles.
Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions. The initial latency time and clock
speed determine the latency count setting. Fixed latency is used when the controller cannot monitor WAIT. Fixed latency also provides improved
performance at lower clock frequencies.
The WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be transferred into (or out of ) the memory. WAIT will again
be asserted at the boundary of the row, unless wrapping within the burst length. With wrap off, the CellularRAM device will restore the previous row’s data
and access the next row, WAIT will be de-asserted, and the burst can continue across the row boundary(See Figeure 29 on page 42 for a READ, Figure
34 on page 47 for a WRITE). If the burst is to terminate at the row boundary, CE# must go HIGH within 2 clocks of the last data(See Figure 28 on page
41). CE# must go HIGH before any clock edge following the last word of a defined-length burst WRITE(See Figure 31 and 32 on pages 44 and 45).
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst suspension will cause CE# to remain LOW
for longer than tCEM, CE# should be taken HIGH and the burst restarted with a new CE# LOW/ADV# LOW cycle.
13
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 7: Refresh Collision During Variable-Latency READ Operation
CLK
A[21:16]
ADV#
VIH
VIL
VIH
VIL
Valid
Address
VIH
VIL
VIH
CE#
VIL
VIH
OE#
WE#
LB#/UB#
A/DQ[15:0]
WAIT
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
Valid
Address
VOH
D0
D1
D2
VOL
D3
High-Z
VOL
Additional WAIT states inserted to allow refresh completion.
Don’t Care
Note: Non-default BCR settings for refresh collision during variable-latency READ operation:
Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
14
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous WRITE operations when the BCR is configured for
synchronous operation. The asynchronous WRITE operations require that the clock (CLK) remain static (HIGH or LOW) during the
entire sequence. The ADV# signal can be used to latch the target address. CE# can remain LOW when the device is transitioning
between mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode operation
facilitates a seamless interface to legacy burst mode Flash memory controllers. See Figure 36 on page 49 for the “Asynchronous WRITE
Followed by Burst READ” timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal(See Figure 8). The shared WAIT
signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus.
Figure 8: Wired or WAIT Configuration
External
Pull-Up
Pull-Down
Resistor
CellularRAM
WAIT
READY
WAIT
WAIT
Processor
Other
Device
Other
Device
When a burst READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional time before data can be transferred. For burst READ operations, WAIT will remain active until valid data is output from the device.
For burst WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When
WAIT transitions to an inactive state, the data burst will progress on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial latency may cause data
corruption.
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for burst READ operations
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has
completed(See Figure 7 on page 14). When the refresh operation has completed, the burst READ operation will continue normally.
WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The WAIT assertion allows time for the new
row to be accessed.
WAIT will be asserted after OE# goes LOW during asynchronous READ operations. WAIT will be High-Z during asynchronous WRITE
operations. WAIT should be ignored during all asynchronous operations.
By using fixed initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal. However, WAIT can still be used to determine when valid data is available at the start of the burst and at the end of the row. If WAIT is not
monitored, the controller must properly terminate all burst accesses at row boundaries on its own.
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be
transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be written
is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB# and UB# must be LOW during READ cycles. When
both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or transmitting data.
Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW.
15
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
LOW-POWER OPERATION
Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh operation. Standby
operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion of a READ or WRITE operation, or
when the address and control inputs remain static for an extended period of time. This mode will continue until a change occurs to the
address or control inputs.
Temperature Compensated Refresh
Temperature compensated self refresh (TCSR) allows for adequate refresh at different temperatures. This CellularRAM device includes
an on-chip temperature sensor that automatically adjusts the refresh rate according to the operating temperature. The device continually
monitors the temperature to select an appropriate self-refresh rate.
Partial Array Refresh
Partial array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the device to reduce
standby current by refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half
array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the
end of the address map(See Table 7 on page 29). READ and WRITE operations to address ranges receiving refresh will not be affected.
Data stored in addresses not receiving refresh will become corrupted. When re-enabling additional portions of the array, the new
portions are available immediately upon writing to the RCR.
16
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines how the CellularRAM interacts with the system memory bus and is nearly identical to its counterpart on burst mode Flash devices. The refresh
configuration register (RCR) is used to control how refresh is performed on the DRAM array. These registers are automatically loaded
with default settings during power-up, and can be updated any time the devices are operating in a standby state. A DIDR provides
information on the device manufacturer, CellularRAM generation, and the specific device configuration. The DIDR is read-only.
Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation when the control register enable (CRE) input
is HIGH(see Figure 9 through 12 on pages 17 through 20) . When CRE is LOW, a READ or WRITE operation will access the memory
array. The configuration register values are written via addresses A[21:16] and A/DQ[15:0]. In an asynchronous WRITE, the values are
latched into the configuration register on the rising edge of ADV#, CE#, or WE#, whichever occurs first; LB# and UB# are “Don’t Care”.
The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The DIDR is read when A[19:18] are 01b.
For READs, address inputs other than A[19:18] are “Don’t Care”, and register bits 15:0 are output on DQ[15:0]. Immediately after a
configuration register READ or WRITE operation is performed, reading the memory array is highly recommended.
Figure 9: Configuration Register WRITE, Asynchronous Mode, Followed by READ ARRAY Operation
A[21:16]
(except A[19:18])
OPCODE
tAVS
Address
tAVH
Select control register
A[19:18]1
CRE
Address
tAVS
tAVH
ADV#
tVP
CE#
tCPH
Initiate Control register access
tCW
OE#
tWP
Write address bus value
to control register
WE#
LB#/UB#
A/DQ[15:0]
Address
OPCODE
Valid
data
Don’t Care
Note: A[19:18] = 00b to load RCR, and 10b to load BCR.
17
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 10: Configuration Register WRITE, Synchronous Mode, Followed by READ ARRAY Operation
CLK
Latch control register value
A[21:16]
(except A[19:18])
OPCODE
tSP
Address
tHD
Latch control register address
A[19:18]2
Address
tSP
tHD
tSP
tHD
CRE
ADV#
tCBPH
tCSP
CE#
Note3
OE#
tSP
tHD
WE#
LB#/UB#
A/DQ[15:0]
Address
OPCODE
Valid
data
tKHTL
WAIT
High-Z
High-Z
Don’t Care
Note:
1. Nondefault BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation: Latency
code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored; additional WAIT cycles caused by refresh
collisions require a corresponding number of additional CE# LOW cycles.
18
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 11: Register READ, Asynchronous Mode, Followed by READ ARRAY Operation
A[21:16]
(except A[19:18])
Address
tAVS
tAVH
Select register
Address
A[19:18]1
tAA
tAVH
tAVS
CRE
tAA
ADV#
tVP
tAADV
tCPH
Initiate register access
CE#
tCPH
tHZ
tCO
OE#
tOHZ
tOE
WE#
tBA
tBHZ
tOLZ
LB#/UB#
A/DQ[15:0]
Valid CR
Address
Don’t Care
Note: A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
19
Valid
data
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 12: Register READ, Synchronous Mode, Followed by READ ARRAY Operation
CLK
Latch control register value
A[21:16]
(except A[19:18])
Address
tSP
tHD
Latch control register address
2
A[19:18]
Address
tSP
tHD
CRE
tSP
tHD
ADV#
tCBPH
tABA
tCSP
CE#
Note3
tHZ
OE#
tOHZ
WE#
tSP
tHD
tBOE
LB#/UB#
tOLZ
tACLK
tKOH
A/DQ[15:0]
Valid CR
Address
Valid
data
tKHTL
WAIT
High-Z
High-Z
Don’t Care
Note:
1. Nondefault BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
2. A[19:18] = 00b to read RCR, 10b to read BCR, and 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored; additional WAIT cycles caused by refresh collisions require
a corresponding number of additional CE# LOW cycles.
20
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Software Access
Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The contents of the
configuration registers can be modified and all registers can be read using the software sequence.
The configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations followed by two
asynchronous WRITE operations (see Figure 13 on page 22). The READ sequence is virtually identical except that an asynchronous
READ is performed during the fourth operation (see Figure 14 on page 22). The address used during all READ and WRITE operations
is the highest address of the CellularRAM device being accessed (3FFFFFh); the contents of this address are not changed by using this
sequence.
The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, or the DIDR is to be
accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the BCR; if the data is
0002h, the sequence will access the DIDR. This value must be valid at the falling edge of WE#. During the fourth operation, DQ[15:0]
transfer data in to or out of bits 15:0 of the registers.
The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of loading the
configuration registers. However, the software nature of this access mechanism eliminates the need for CRE. If the software mechanism
is used, CRE can simply be tied to VSS. The port line often used for CRE control purposes is no longer required.
21
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 13: Load Configuration Register
CE#
READ
READ
WRITE
WRITE
OE#
WE#
LB#/UB#
ADV#
A[21:16]
Address
(MAX)
A/DQ[15:0]
Address
(MAX)
Address
(MAX)
Address
(MAX)
Address
(MAX)
0ns (min); Note 1
XXXX
Address
(MAX)
Address
XXXX
(MAX)
Address
(MAX)
CR Value
in
RCR : 0000h
BCR : 0001h
Don’t Care
Note:
If the data at the falling edge of WE# is not 0000h, 0001h or 0002h, it is possible that the data stored at the highest memory location will be altered.
Figure 14: Read Configuration Register
CE#
READ
READ
READ
WRITE
OE#
WE#
LB#/UB#
ADV#
A[21:16]
Address
(MAX)
A/DQ[15:0]
Address
(MAX)
Address
(MAX)
Address
(MAX)
Address
(MAX)
0ns (min); Note 1
XXXX
Address
(MAX)
XXXX
Address
(MAX)
RCR : 0000h
BCR : 0001h
DIDR : 0002h
Address
(MAX)
CR Value
out
Don’t Care
Note:
If the data at the falling edge of WE# is not 0000h, 0001h or 0002h, it is possible that the data stored at the highest memory location will be altered.
22
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
BUS CONFIGURATION REGISTER
The BCR defines how the CellularRAM device interacts with the system memory bus. Figure 15 describes the control bits in the BCR. At
power-up, the BCR is set to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register access software
sequence with A/DQ = 0001h on the third cycle.
Figure 15: Bus Configuration Register Definition
A
[21:20]
A
[19:18]
A
[17:16]
A/DQ
15
A/DQ
14
21-20
19-18
17-16
15
14
Reserved
Register
Select
Reserved
Operating
Mode
Initial
Latency
All must be set to “0”
A/DQ
[13:11]
13
12
A/DQ
10
11
Latency
Counter
A/DQ
9
A/DQ
7
A/DQ
6
A/DQ
[5:4]
10
9
8
7
6
WAIT
Polarity
Reserved
WAIT
Configuration(WC)
Reserved
Reserved
Must be set to “0”
Must be set to “0”
BCR[14]
A/DQ
8
Initial Access Latency
Must be set to “0”
5
4
Drive
Strength
BCR[3]
0
Burst wraps within the burst length
1
Fixed
1
Burst no wrap (default)
BCR[11]
Latency Counter
BCR[5]
BCR[4]
0
0
Full
1/2 (default)
0
0
Code 8
0
1
0
0
1
Code 1 - Reserved
1
0
1/4
0
1
0
Code 2
1
1
Reserved
0
1
1
Code 3 (default)
1
0
0
Code 4
1
0
1
Code 5
BCR[8]
1
1
0
Code 6
0
Asserted during delay
1
1
1
Code 7 - Reserved
1
Asserted one data cycle before delay (default)
BCR[15]
WAIT Configuration
WAIT Polarity
0
Active LOW
1
Active HIGH (default)
Operating Mode
0
Synchronous burst access mode
1
Asynchronous access mode (default)
Register Select
BCR[2]
BCR[1]
BCR[0]
0
0
1
Burst Length (Note 1)
0
1
0
8 words
0
1
1
16 words
4 words
BCR[19]
BCR[18]
0
0
Select RCR
1
0
0
32 words
1
0
Select BCR
1
1
1
Continuous burst (default)
0
1
Select DIDR
Others
Note:
1. Burst wrap and length apply to both READ and WRITE operations.
2. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionallity. BCR[15:0] will be read back as written.
23
Reserved
1 0
Burst
Length(BL)
Drive Strength
0
BCR[10]
2
Burst Wrap (Note 1)
Variable (default)
BCR[12]
3
Burst
Wrap(BW)
A/DQ
[2:0]
Must be set to “0”
0
BCR[13]
A/DQ
3
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device supports a burst
length of 4, 8, 16, or 32 words. The device can also be set in continuous burst mode where data is output sequentially without regard to
address boundaries; the internal address wraps to 000000h if the device is read past the last address.
Burst Wrap (BCR[3]) Default = No Wrap
The burst-wrap option determines if a 4, 8, 16, or 32 word READ or WRITE burst wraps within the burst length, or steps through
sequential addresses. If the wrap option is not enabled, the device accesses data from sequential addresses without regard to address
boundaries; the internal address wrap to 000000h if the device is read past the last address.
Table 3: Sequence and Burst Length
BURST Wrap
BCR[3]
0
Wrap
Yes
Starting
Address
4 Word
Burst
Length
Decimal
Linear
Linear
Linear
Linear
Linear
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2 ... 29-30-31
0-1-2-3-4-5-6-...
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3 ... 30-31-0
1-2-3-4-5-6-7-...
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4 ... 31-0-1
2-3-4-5-6-7-8-...
3
3-0-1-2
8 Word
Burst Length
16 Word
Burst Length
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5 ... 0-1-2
3-4-5-6-7-8-9-...
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6 ... 1-2-3
4-5-6-7-8-9-10-...
5
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7 ... 2-3-4
5-6-7-8-9-10-11-...
6
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8 ... 3-4-5
6-7-8-9-10-11-12-...
7
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-...
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9 ... 4-5-6
...
...
...
...
14
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-16-...-11-12-13
14-15-16-17-18-19-20-...
15
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17...-12-13-14
15-16-17-18-19-20-21-...
...
...
...
30
30-31-0-...-27-28-29
30-31-32-33-34-...
31-0-1-... -28-29-30
31-32-33-34-35-...
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-...-29-30-31
0-1-2-3-4-5-6-...
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
1-2-3-...-30-31-32
1-2-3-4-5-6-7-...
2
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
2-3-4-...-31-32-33
2-3-4-5-6-7-8-...
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
3-4-5-...-32-33-34
3-4-5-6-7-8-9-...
4-5-6-7-8-9-10-11
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
4-5-6-...-33-34-35
4-5-6-7-8-9-10-...
4
No
Continuous
Burst
4
31
1
32 Word
Burst Length
5
5-6-7-8-9-10-11-12
5-6-7-8-9-10-11-12-13-14-15-16-17-18-19-20
5-6-7-...-34-35-36
5-6-7-8-9-10-11-...
6
6-7-8-9-10-11-12-13
6-7-8-9-10-11-12-13-14-15-16-17-18-19-20-21
6-7-8-...-35-36-37
6-7-8-9-10-11-12-...
7
7-8-9-10-11-12-13-14
7-8-9-10-11-12-13-...
7-8-9-10-11-12-13-14-15-16-17-18-19-20-21-22
7-8-9-...-36-37-38
...
...
...
...
14
14-15-16-17-18-...-23-24-25-26-27-28-29
14-15-16-...43-44-45
14-15-16-17-18-19-20-...
15
15-16-17-18-19-...-24-25-26-27-28-29-30
15-16-17-...-44-45-46
15-16-17-18-19-20-21-...
...
...
...
30
30-31-32-...-59-60-61
30-31-32-33-34-35-36-...
31
31-32-33-...-60-61-62
31-32-33-34-35-36-37-...
24
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus loading scenarios. The
reduced-strength options are intended for stacked chip (Flash + CellularRAM) environments when there is a dedicated memory bus. The
reduced-drive-strength option minimizes the noise generated on the data bus during READ operations. Full output drive strength should
be selected when using a discrete CellularRAM device in a more heavily loaded data bus environment. Outputs are configured at halfdrive strength during testing. See Table 4 for additional information.
Table 4: Drive Strength
BCR[5]
BCR[4]
Drive Strength
Impedance Typ (Ω )
0
0
Full
25~30
CL = 30pF to 50pF
0
1
1/2
(default)
50
CL = 15pF to 30pF
104 MHz at light load
1
0
1/4
100
CL = 15pF or lower
1
1
Reserved
25
Use Recommendation
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted state with respect to
valid data presented on the data bus. The memory controller will use the WAIT signal to coordinate data transfer during synchronous
READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid on the clock edge immediately after WAIT transitions to the
de-asserted or asserted state, respectively. When BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going
valid or invalid(See Figure 16).
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine whether the WAIT
signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
Figure 16: WAIT Configuration During Burst Operation
CLK
WAIT
BCR[8] = 0
Data Valid in current cycle
WAIT
BCR[8] = 1
Data Valid in next cycle
initial latency
D0
A/DQ[15:0]
D1
D3
D2
End of row
Don’t Care
Note: Non-default BCR setting: WAIT active LOW.
Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and the first data
value transferred. For allowable latency codes, see Table 5 and 6 on pages 26 and 27, respectively, and Figure 17 and 18 in page 27,
respctively.
Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must be monitored to
detect delays caused by collisions with refresh operations. Fixed initial access latency outputs the first data at a consistent time that
allows for worst-case refresh collisions. The latency counter must be configured to match the initial latency and the clock frequency. It is
not necessary to monitor WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency
counter(See Table 6 on page 27 and Figure 18 on page 27).
Table 5: Variable Latency Configuration Codes
BCR[13:11]
Latency
Configuration
Code
Latency
1
Max Input CLK Frequency (MHz)
Normal
Refresh Collision
133
104
83
2 (3 clocks)
2
4
66(15ns)
66(15ns)
52(19.2ns)
011
3 (4 clocks)-default
3
6
104(9.62ns)
104(9.62ns)
83(12ns)
100
4 (5 clocks)
4
8
133(7.5ns)
-
-
Reserved
-
-
-
-
-
010
Others
Note: 1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on the next clock cycle.
26
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 17: Latency Counter (Variable Initial Latency, No Refresh Collision)
CLK
A[21:16]
VIH
VIL
VIH
Valid
Address
VIL
VIH
ADV#
VIL
Code 2
A/DQ[15:0]
VIH
Valid
Address
VIL
D0
D1
D3
D4
D5
D6
D7
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D2
Code 3 (default)
A/DQ[15:0]
VIH
Valid
Address
VIL
D0
Code 4
A/DQ[15:0]
VIH
Valid
Address
VIL
Don’t Care
Undefined
Table 6: Fixed Latency Configuration Codes
Latency
Configuration
Code
BCR[13:11]
010
Latency Count (N)
Max Input CLK Frequency (MHz)
Normal
133
104
83
2
33(30ns)
33(30ns)
33(30ns)
2 (3 clocks)
011
3 (4 clocks)-default
3
52(19.2ns)
52(19.2ns)
52(19.2ns)
100
4 (5 clocks)
4
66(15ns)
66(15ns)
66(15ns)
101
5 (6 clocks)
5
75(13.3ns)
75(13.3ns)
75(13.3ns)
110
6 (7 clocks)
6
104(9.62ns)
104(9.62ns)
83(12ns)
000
8 (9 clocks)
8
133(7.5ns)
-
-
Reserved
--
-
-
-
Others
Figure 18: Latency Counter (Fixed Latency)
N-1
Cycles
CLK
Cycle N
VIH
VIL
tAA
VIH
A[21:16]
VIL
Valid
Address
tAADV
VIH
ADV#
CE#
VIL
tCO
VIH
VIL
tACLK
VOH
A/DQ[15:0]
(READ) VOL
Valid
Output
tSP
A/DQ[15:0] VOH
(WRITE) VOL
Valid
Address
Valid
Input
Valid
Output
Valid
Input
Valid
Input
Don’t Care
(ADV# = LOW)
27
Valid
Output
Valid
Output
tHD
Valid
Input
Burst Identified
Valid
Output
Valid
Input
Valid
Input
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Operating Mode (BCR[15]) Default = Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
REFRESH CONFIGURATION REGISTER
The refresh configuration register (RCR) defines how the CellularRAM device performs its transparent self refresh. Altering the refresh
parameters can dramatically reduce current consumption during standby mode. Figure 19 describes the control bits used in the RCR. At
power-up, the RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access software
sequence with A/DQ = 0000h on the third cycle.
Figure 19: Refresh Configuration Register Mapping
A[21:20]
A[19:18]
A[17:16]
A/DQ
[15:7]
A/DQ
6
6
21~20
19-18
17-16
15~7
Reserved
Register Select
Reserved
Reserved
All must be set to “0”
All must be set to “0”
A/DQ
5
A/DQ
4
5
4
Ignored
Setting is ignored
(Default 001b)
A/DQ
3
A/DQ
2
3
2
Reserved
A/DQ
1
A/DQ
0
1
0
PAR
Must be set to “0”
RCR[19]
RCR[18]
Register Select
RCR[2]
RCR[1]
RCR[0]
Refresh Coverage
0
0
Select RCR
0
0
0
Full array (default)
1
0
Select BCR
0
0
1
Bottom 1/2 array
0
1
Select DIDR
0
1
0
Bottom 1/4 array
0
1
1
Bottom 1/8 array
1
0
0
None of array
1
0
1
Top 1/2 array
1
1
0
Top 1/4 array
1
1
1
Top 1/8 array
Note: 1. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. RCR[15:0] will be read back as written.
28
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Partial Array Refresh (RCR[2:0] Default = Full Array Refresh)
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce standby current by
refreshing only that part of the memory array required by the host system. The refresh options are full array, one-half array, one-quarter
array, one-eighth array, or none of the array. The mapping of these partitions can start at either the beginning or the end of the address
map(See Table 7 and Table 8).
Table 7: Address Patterns for PAR (RCR[4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Address Space
0
0
0
0
0
0
Size
Density
0
Full Die
000000h-3FFFFFh
4 Meg x 16
64Mb
1
One-half die
000000h-1FFFFFh
2 Meg x 16
32Mb
1
0
One-quarter of die
000000h-0FFFFFh
1 Meg x 16
16Mb
1
1
One-eighth of die
000000h-07FFFFh
512 K x 16
8Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
200000h-3FFFFFh
2 Meg x 16
32Mb
1
1
0
One-quarter of die
300000h-3FFFFFh
1 Meg x 16
16Mb
1
1
1
One-eighth of die
380000h-3FFFFFh
512 K x 16
8Mb
Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device configuration. Table 8
describes the bit fields in the DIDR. This register is read-only. The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the
register access software sequence with A/DQ = 0002h on the third cycle.
Table 8: Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
DIDR[10:8]
DIDR[7:5]
DIDR[4:0]
Field name
Row Length
Device version
Device density
CellularRAM generation
Vendor ID
Length
Bit
Setting
256 words
1b
Version
Bit
Setting
1st
0000b
2nd
0001b
...
...
Density
Bit
Setting
64Mb
010b
Options
29
Generation
Bit
Setting
Vendor
Bit
Setting
CR 1.5
010b
EMLSI
01010b
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
ELECTRICAL CHARACTERISTICS
Table 9: Absolute Maximum Ratings
Parameter
Rating
Voltage to any pin except Vcc, VccQ relative to Vss
-0.3V to VccQ + 0.3V
Voltage on Vcc supply relative to Vss
-0.2V to +2.45V
Voltage on VccQ supply relative to Vss
-0.2V to +2.45V
Storage temperature (plastic)
-55°C to +150°C
Operating temperature (case) Wireless
-30°C to +85°C
Soldering temperature and time: 10s (solder ball only)
+260°C
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these
or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
Table 10: Electrical Characteristics and Operating Conditions
Wireless Temperature (-30°C < TC < +85°C)
Description
Conditions
Symbol
Min
Max
Unit
Notes
VCC
1.7
1.95
V
I/O supply voltage
VCCQ
1.7
1.95
V
Input high voltage
VIH
VCCQ - 0.4
VCCQ + 0.2
V
1
Input low voltage
VIL
-0.20
0.4
V
2
0.80 VCCQ
Supply voltage
Output high voltage
IOH = -0.2mA
VOH
V
3
Output low voltage
IOL = +0.2mA
VOL
0.20 VCCQ
V
3
VIN = 0 to VCCQ
ILI
1
µA
Output leakage current
OE# = VIH or chip disabled
ILO
Operating current
Conditions
Input leakage current
Asynchronous random
READ/WRITE
ICC1
Initial access,
burst READ/WRITE
ICC2
VIN = VCCQ or 0V chip enabled, IOUT = 0
ICC3R
Continuous burst READ
ICC3W
Continuous burst WRITE
Standby current
1
µA
Max
Unit
Notes
70ns
25
mA
4
133MHz
40
mA
104MHz
35
mA
83MHz
30
mA
133MHz
35
mA
104MHz
30
mA
83MHz
25
mA
133MHz
40
mA
104MHz
35
mA
83MHz
30
mA
Standard
180
µA
160
µA
140
µA
Symbol
VIN = VCCQ or 0V, CE# = VCCQ
ISB
Low Power
Typ
TBD
Low-Low Power
Note:
1. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to VSS - 1.0V for periods less than 2ns during transitions.
3. BCR[5:4] = 01b (default setting of one-half drive strength).
4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to drive output
capacitance expected in the actual system.
5. ISB (max) values measured with PAR set to FULL ARRAY and at +85°C. In order to achieve low standby current, all inputs must be driven to
either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, or when entering standby mode.
6. ISB (typ) is the average ISB at 25°C and VCC = VCCQ = 1.8V. This parameter is verified during characterization, and is not 100% tested.
30
4
4
4
5, 6
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Table 11: Capacitance
Description
Conditions
Input Capacitance
Tc = = +25°C; f = 1 MHz;
VIN = 0V
Input/Output Capacitance(A/
DQ)
Symbol
Min
Max
Unit
Notes
CIN
2.0
6
pF
1
CIO
3.0
6.5
pF
1
Note: 1. These parameters are verified in device characterization and are not 100% tested.
Figure 20: AC Input/Output Reference Waveform
VccQ
Input1
VccQ/22
VccQ/23
Test Points
VssQ
Note:
1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2. Input timing begins at VCCQ/2.
3. Output timing ends at VCCQ/2.
Figure 21: AC Output Load Circuit
Test Points
50Ω
VccQ/2
DUT
30pF
Note: All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).
31
Output
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
TIMING REQUIREMENTS
Table 12: Asynchronous READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
Address access time
ADV# access time
Symbol
Min
tAA
tAADV
Max
Unit
70
ns
70
ns
Notes
Address hold from ADV# HIGH
tAVH
2
Address setup to ADV# HIGH
tAVS
5
LB#/UB# access time
tBA
LB#/UB# disable to DQ High-Z output
tBHZ
7
ns
Chip select access time
tCO
70
ns
CE# LOW to ADV# HIGH
tCVS
Chip disable to DQ and WAIT High-Z output
tHZ
7
ns
Output enable to valid output
tOE
20
ns
7.5
ns
7
ns
1
2
ns
ns
70
7
ns
ns
OE# LOW to WAIT valid
tOEW
Output disable to DQ High-Z output
tOHZ
Output enable to Low-Z output
tOLZ
3
ns
ADV# pulse width
tVP
5
ns
1
Note:
1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
2. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.
32
1
1
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Table 13: Burst READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
133MHz
Symbol
Min
104MHz
Max
Min
83MHZ
Max
Min
Unit
tAA
70
70
70
ns
ADV# access time (fixed latency)
tAADV
70
70
70
ns
Burst to READ access time (variable latency)
tABA
35.5
35.9
45
ns
CLK to output delay
tACLK
5.5
7
9
ns
20
ns
Address access time (fixed latency)
Address hold from ADV# HIGH(fixed latency)
tAVH
Burst OE# LOW to output delay
tBOE
CE# HIGH between subsequent burst or mixed mode
operations
tCBPH
Maximum CE# pulse width
tCEM
2
2
20
5
2
20
5
4
ns
6
4
ns
1
4
µs
1
70
ns
CLK period
tCLK
Chip select access time (fixed latency)
tCO
CE# setup time to active CLK edge
tCSP
2.5
3
4
ns
Hold time from active CLK edge
tHD
1.5
2
2
ns
7.5
9.62
70
12
70
ns
tHZ
7
7
7
CLK rise or fall time
tKHKL
1.2
1.6
1.8
ns
CLK to WAIT valid
tKHTL
5.5
7
9
ns
Output HOLD from CLK
tKOH
2
2
2
ns
CLK HIGH or LOW time
tKP
3
3
4
ns
Chip disable to DQ and WAIT High-Z output
Notes
Max
ns
2
Output disable to DQ High-Z output
tOHZ
ns
2
Output enable to Low-Z output
tOLZ
3
3
3
ns
3
Setup time to active CLK edge
tSP
2
3
3
ns
7
7
7
Note:
1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
HIGH, or b) CE# HIGH for longer than 15ns.
2. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
3. The Low-Z timings measure a 100mV transition away from the High-Z (VccQ/2) level toward either VOH or VOL.
33
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Table 14: Asynchronous WRITE Cycle Timing Requirements
Parameter
Symbol
Min
Address and ADV# LOW setup time to WE# LOW
tAS
Max
Unit
0
ns
Address HOLD from ADV# going HIGH
tAVH
2
ns
Address setup to ADV# going HIGH
tAVS
5
ns
Address valid to end of WRITE
tAW
70
ns
LB#/UB# select to end of WRITE
tBW
70
ns
CE# HIGH between subsequent async operations
tCPH
5
ns
CE# LOW to ADV# HIGH
tCVS
7
ns
Chip enable to end of WRITE
tCW
70
ns
Data HOLD from WRITE time
tDH
0
ns
20
Data WRITE setup time
tDW
Chip disable to WAIT High-Z output
tHZ
ADV# pulse width
tVP
5
ns
ADV# setup to end of WRITE
tVS
70
ns
WRITE to DQ High-Z output
tWHZ
WRITE pulse width
tWP
WRITE recovery time
tWR
ns
7
7
Note:
1. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
2. WE# Low time must be limited to tCEM (4µs).
34
Notes
ns
1
ns
1
45
ns
2
0
ns
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Table 15: Burst WRITE Cycle Timing Requirements
Parameter
133MHz
Symbol
Min
Address and ADV# LOW setup time
104MHz
Max
Min
83MHZ
Max
Min
Unit
Notes
1
Max
tAS
0
0
0
ns
tAVH
2
2
2
ns
CE# HIGH between subsequent burst or mixed
mode operations
tCBPH
5
5
6
ns
2
Maximum CE# pulse width
tCEM
µs
2
to WE# LOW
Address HOLD from ADV# HIGH(fixed latency)
4
4
4
Clock period
tCLK
7.5
9.62
12
ns
CE# setup to CLK active edge
tCSP
2.5
3
4
ns
Hold time from active CLK edge
tHD
1.5
2
2
ns
Chip disable to WAIT High-Z output
tHZ
7
7
7
CLK rise or fall time
tKHKL
1.2
1.6
1.8
ns
Clock to WAIT valid
tKHTL
5.5
7
9
ns
Output HOLD from CLK
tKOH
2
2
2
ns
CLK HIGH or LOW time
tKP
3
3
4
ns
Setup time to activate CLK edge
tSP
2
3
3
ns
Note:
1. tAS required if tCSP > 20ns.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
HIGH, or b) CE# HIGH for longer than 15ns.
3. The High-Z timings measure a 100mV transition from either VOH or VOL toward VccQ/2.
35
ns
3
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
TIMING DIAGRAMS
Figure 22: Initialization Period
Vcc(MIN)
Vcc, VccQ = 1.7V
tPU
Device ready for
normal operation
Table 16: Initialization Timing Parameters
Parameter
Symbol
Initialization period (required before normal operations)
tPU
Min
Max
Unit
150
µs
Figure 23: Asynchronous READ
A[21:16]
VIH
Valid Address
VIL
tAA
tAVH
tAVS
VIH
ADV#
tAADV
VIL
tVP
tHZ
tCVS
VIH
CE# V
IL
tCO
LB#/UB#
tBHZ
tBA
VIH
VIL
OE#
VIL
VIH
WE#
VIL
tOLZ
A/DQ[15:0]
tAVS
VIH
tAVH
Valid address
VIL
tAA
VOH
VOL
tOEW
WAIT
tOHZ
tOE
VIH
VOH
Valid Output
tHZ
High-Z
High-Z
VOL
Don’t Care
36
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 24: Single-Access Burst READ Operation - Variable Latency
tCLK
tKP
tKP
VIH
CLK
VIL
tKHKL
tSP
VIH
A[21:16]
ADV#
Valid Address
VIL
tHD
tSP
VIH
tHD
VIL
tCEM
tCSP
VIH
CE#
tHD
VIL
tOHZ
tBOE
VIH
OE#
tHZ
tABA
VIL
tSP
tHD
tOLZ
VIH
WE#
VIL
LB#/UB#
VIL
tSP
VIH
A/DQ[15:0]
tHD
Valid
Address
VIL
VOH
WAIT
tHD
tSP
VIH
tACLK
tKOH
VOH
High-Z
VOL
Valid Output
High-Z
tKOH
High-Z
High-Z
VOL
tKHTL
tKHTL
READ Burst Identified
(WE# = HIGH)
Don’t Care
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
37
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 25: 4-Word Burst READ Operation - Variable Latency
tKHKL
tCLK
tKP
tKP
VIH
CLK
VIL
tSP
tHD
VIH
A[21:16]
Valid Address
VIL
tSP
VIH
ADV#
VIL
tHD
tCSP
tABA
tHD
CE#
tHZ
VIL
tBOE
VIH
OE#
tCBPH
tCEM
VIH
VIL
tSP
tHD
tOHZ
tOLZ
VIH
WE#
VIL
LB#/UB#
A/DQ[15:0]
tHD
tSP
VIH
VIL
tSP
VIH
VIL
tKOH
tACLK
tHD
Valid
address
VOH
Valid
Output
VOL
Valid
Output
Valid
Output
Note 2
High-Z
High-Z
VOL
Note 3
High-Z
tKOH
VOH
WAIT
Valid
Output
tKHTL
tKHTL
READ Burst Identified
(WE# = HIGH)
Don’t Care
Notes :
1. Non-default BCR settings: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT Will remain de-asserted even if CE# remains LOW past the end of the defined burst length.
3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length.
38
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 26: Single-Access Burst READ Operation - Fixed Latency
tCLK
tKP
tKP
VIH
CLK
VIL
tKHKL
tSP
VIH
A[21:16]
Valid Address
tAVH
VIL
tSP
VIH
ADV#
tAA
tHD
tAADV
VIL
tHD
tCEM
CE#
VIL
tCO
VIL
tSP
tOHZ
tBOE
VIH
OE#
tHZ
tCSP
VIH
tOLZ
tHD
VIH
WE#
VIL
tSP
VIH
UB#/LB#
VIL
tSP
tHD
tAVH
tACLK
VIH
A/DQ[15:0]
tKOH
VOH
Valid Address
Valid Output
VIL
VOL
High-Z
tKOH
VOH
WAIT
VOL
High-Z
High-Z
tKHTL
tKHTL
READ Burst Identified
(WE# = HIGH)
Don’t Care
1. Non-default BCR settings: Fixed latency; latency code four (five clocks); WAIT active LOW; WAIT asserted during delay.
39
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 27: 4-Word Burst READ Operation - Fixed Latency
tCLK
tKHKL
tKP
tKP
VIH
CLK
VIL
tSP
VIH
A[21:16]
ADV#
Valid Address
VIL
tAVH
tSP
VIH
VIL
tAADV
tCEM
VIL
tHZ
tCO
tBOE
VIH
OE#
tCBPH
tHD
tCSP
VIH
CE#
tAA
tHD
VIL
tSP
tHD
tOHZ
tOLZ
VIH
WE#
VIL
UB#/LB#
tHD
tSP
VIH
VIL
VIH
A/DQ[15:0]
Valid
address
VIL
tACLK
tAVH
tSP
VOH
Valid
Output
VOL
VOL
Valid
Output
Valid
Output
Valid
Output
Note 3
High-Z
tKOH
VOH
WAIT
tKOH
Note 2
High-Z
High-Z
tKHTL
tKHTL
READ Burst Identified
(WE# = HIGH)
Don’t Care
Notes :
1. Non-default BCR settings: Fixed latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT will remain de-asserted even if CE# remains LOW past the end of the defined burst length.
3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length.
40
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 28: Burst READ Terminate at End-of-Row (Wrap Off)
VIH
CLK
VIL
tCLK
VIH
A[21:16]
VIL
VIH
ADV#
VIL
VIH
UB#/LB#
VIL
tHD
tCSP
Note 2
VIH
CE#
VIL
VIH
OE#
VIL
VIH
WE#
A/DQ[15:0]
VIL
VOH
VOL
End of row
Valid
Output
Valid
Output
tKHTL
WAIT
tHZ
tHZ
VOH
VOL
High-Z
tKOH
Don’t Care
Undefined
Notes :
1. Non-default BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW; WAIT asserted during delay.
2. For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins ( befor the second CLK after WAIT asserts with BCR[8]=0, or before the third CLK
after WAIT asserts with BCR[8]=1 ).
41
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 29: Burst READ Row Boundary Crossing
CLK
VIH
VIL
A[21:16]
tCLK
VIH
VIL
ADV#
VIH
VIL
VIH
UB#/LB#
CE#
VIL
VIH
VIL
OE#
WE#
VIH
VIL
VIH
VIL
tSP
End of row
tHD
VOH
A/DQ[15:0]
Valid output
VOL
VOH
WAIT V
OL
Valid output
Valid output
Valid out
tKTHL
tKTHL
Note 2
tKOH
tKOH
Don’t Care
Note:
1. Nondefault BCR settings for burst READ at end of row : fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as
solid line)
2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency.
42
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 30: Asynchronous WRITE
VIH
A[21:16]
Valid Address
VIL
tAVS
tAVH
tVS
ADV#
tVP
VIH
VIL
tAS
tAW
tAS
tCW
VIH
CE#
tCVS
VIL
tBW
VIH
UB#/LB#
VIL
VIH
OE#
VIL
tWP
VIH
WE#
A/DQ[15:0]
VIL
VIH
VIL
WAIT
VOH
VOL
tAS
tAVS
tAVH
tDW
Valid Address
tDH
Valid Input
tAW
High-Z
Don’t Care
43
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 31: Burst WRITE Operation - Variable Latency Mode
tKHKL
tCLK
CLK
tKP
tKP
VIH
VIL
tSP
tHD
VIH
A[21:16]
Valid Address
VIL
3
tAS
tSP
VIH
ADV#
VIL
tHD
tAS3
tSP
tHD
VIH
UB#/LB#
VIL
CE#
tHD
tCSP
VIH
tCBPH
tCEM
Note4
VIL
VIH
OE#
VIL
tSP
tHD
VIH
WE#
VIL
tAS3
tSP
tHD
tHD
VIH
A/DQ[15:0]
Valid Address
VIL
WAIT
tSP
VOH
High-Z
VOL
D1
D2
D3
D0
tKHTL
tKHTL
tHZ
High-Z
Note 2
tKOH
WRITE Burst Identified
(WE# = Low)
Don’t Care
Note:
1. Nondefault BCR settings for burst WRITE operation in variable latency mode: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted
during delay, burst length 4, burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
3. tAS required if tCSP > 20ns.
4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
44
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 32: Burst WRITE Operation - Fixed Latency Mode
tKHKL
tCLK
CLK
A[21:16]
VIL
tSP
Valid Address
VIL
tAS3
tAVH
tSP
VIL
tHD
tAS3
tSP
tHD
VIH
UB#/LB#
VIL
tCSP
VIH
CE#
tKP
VIH
VIH
ADV#
tKP
VIH
tHD
tCEM
tCBPH
Note 4
VIL
VIH
OE#
VIL
tSP
VIH
WE#
VIL
VIH
A/DQ[15:0]
WAIT
tHD
tSP
VOH
High-Z
tHD
D1
Valid Address
VIL
VOL
tSP
tAVH
tAS3
D2
D3
tKHTL
tKHTL
D0
tHZ
High-Z
Note2
tKOH
Don’t Care
WRITE Burst Identified
(WE# = LOW)
Note:
1. Nondefault BCR settings for burst WRITE operation in fixed latency mode: fixed latency, latency code 2(3 clocks), WAIT active LOW,
WAIT asserted during delay, burst length 4, burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
t
3. AS required if tCSP > 20ns.
4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
45
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 33: Burst WRITE Terminate at End-of-Row (Wrap Off)
VIH
CLK
VIL
tCLK
VIH
A[21:16]
VIL
VIH
ADV#
VIL
VIH
UB#/LB#
VIL
tHD
VIH
CE#
tCSP
Note 2
VIL
VIH
OE#
VIL
VIH
WE#
VIL
VIH
A/DQ[15:0]
VIL
VOH
WAIT
VOL
tSP
tHD
Valid
Intput
Valid
Intput
End of row
tHZ
tHZ
High-Z
tKOH
tKHTL
Don’t Care
Note:
1. Nondefault BCR settings for burst WRITE at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted during delay.
(shown as solid line)
2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins(befor the second CLK after WAIT asserts with
BCR[8]=0, or before the third CLK after WAIT asserts with BCR[8]=1).
46
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 34: Burst WRITE Row Boundary Crossing
CLK
VIH
VIL
tCLK
VIH
A[21:16]
VIL
VIH
ADV#
VIL
VIH
UB#/LB#
VIL
VIH
CE#
OE#
VIL
VIH
VIL
WE#
A/DQ[15:0]
WAIT
VIH
VIL
tSP
VIL
Valid input
VOH
VOL
End of row
tHD
VIH
Valid input
Valid output
Valid input
tKTHL
Valid output
tKTHL
tKOH
tKOH
Note 2
Don’t Care
Note:
1. Nondefault BCR settings for burst WRITE at end of row : Fixed or variable latency, WAIT active LOW, WAIT asserted during delay. (shown as
solid line)
2. WAIT will be assert for LC or LC + 1 cycles for variables latency, or LC cycles for fixed latency.
47
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 35: Burst WRITE Followed by Burst READ
tCLK
CLK
A[21:16]
VIH
VIL
VIH
VIL
ADV#
VIH
tSP tHD
tSP tHD
Valid
Address
Valid
Address
tSP tHD
tSP tHD
VIL
UB#/LB#
VIL
VIH
CE#
tHD
tSP
VIH
tHD tCBPH
tCSP
VIL
Note 2
OE#
VIL
VIH
WE#
VIL
VIH
A/DQ[15:0]
WAIT
VIL
tSP tHD
tSP tHD
tSP tHD
Valid
Address
tSP tHD
D0
tSP tHD
D1
D2
D3
VOH
VOL
tOHZ
tCSP
VIH
Valid
Address
tKOH
tBOE
VOH
VOL
Valid
Output
Valid
Output
Valid
Output
Valid
Output
tACLK
High-Z
High-Z
Don’t Care
Note:
1. Nondefault BCR settings for burst WRITE followed by burst READ: fixed or variable latency, latency code 2 (3 clocks), WAIT active LOW,
WAIT asserted during delay.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE#
HIGH, or b) CE# HIGH for longer than 15ns.
48
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 36: Asynchronous WRITE Followed by Burst READ
tCLK
VIH
CLK
VIL
tSP
tHD
VIH
A[21:16]
Valid Address
VIL
VIH
ADV#
VIL
tAVS
CE#
tSP
tAS
tBW
tHD
tSP
VIL
VIH
tHD
tVP
VIH
UB#/LB#
Valid Address
tAVH
tCBPH
tCSP
tCW
Note 2
VIL
tOHZ
VIH
OE#
VIL
WE#
VIL
tSP tHD
tWP
VIH
tWC
tAS
tSP
VIH
A/DQ[15:0]
VIL
VOH
WAIT
Valid Address
tAVS
tAVH
Data
tDW
Valid Address
tDH
tKHTL
VOL
tBOE
tHD
VOH
Valid
Output
VOL
Valid
Output
Valid
Output
tACLK
tKOH
Don’t Care
Note:
1. Nondefault BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: fixed or variable latency, latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
2. When the divice is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW when the
device is transitioning to fixed-latency burst READs. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by
either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
49
Valid
Output
High-Z
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 37: Burst READ Followed by Asynchronous WRITE
tCLK
CLK
VIH
VIL
tSP
tHD
VIH
A[21:16]
tAVS
tSP
VIH
ADV#
CE#
Valid Address
Valid Address
VIL
tHD
tAS
tHD
tCSP
tBOE
VIH
VIL
WE#
UB#/LB#
tSP
tHD
Note 2
tAS
tOLZ
tWP
tWPH
VIH
VIL
tHD
tSP
VIH
tBW
tAS
VIL
tSP
tHD
tKOH
tACLK
VOH
VIH
A/DQ[15:0]
tAW
tCW
tCBPH
tHZ
tOHZ
VIL
OE#
tVS
tVP
VIL
VIH
tAVH
Valid Address
VIL
VOL
VIH
tAVS
tAVH
Valid Address
Valid Output
VIL
tKOH
tDW
tDH
Valid Input
VOH
WAIT
High-Z
VOL
High-Z
tKHTL
tKHTL
Don’t Care
READ Burst Identified
(WE# = HIGH)
Notes:
1. Nondefault BCR settings for burst READ followed by asynchronous WRITE using ADV#: fixed or variable latency, latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
2. When the device is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE# can stay LOW
when the device is transitioning from fixed-latency burst READs; asynchronous operation begins at the falling edge of ADV#. A refresh opportunity
must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH
for longer than 15ns.
50
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
Figure 38: Asynchronous WRITE Followed by Asynchronous READ
A[21:16]
VIH
tAVS
tAS
VIH
VIL
OE#
VIH
tAA
tAADV
tBHZ
tBA
tCPH
tCVS
tHZ
tCO
tCW
VIL
Note 1
tOLZ
VIH
tOHZ
tOE
tWP
VIH
VIL
A/DQ[15:0]
tCVS
VIL
tAVH
tVP
tWR
tBW
VIL
WE#
tAW
tVS
tAS
VIH
CE#
tAVS
tAVH
tVP
ADV#
UB#/LB#
Valid Address
Valid Address
VIL
tAS
tAA
tAW
VOH
VIH
Valid Address
VIL
tAVS
tAVH
Valid Address
Valid Input
tDS
tAVS
tDH
tAVH
VOL
Valid Output
tHZ
tOEZ
VOH
WAIT
High-Z
VOL
Don’t Care
Note:
1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the appropriate refresh
interval. Otherwise, tCPH is only required after CE#-controlled WRITEs.
51
Undefined
Preliminary
EMC646SP16K
4Mx16 CellularRAM AD-MUX
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X X - XX XX
1. EMLSI Memory
12. Power
2. Device Type
11. Speed
3. Density
10. PKG
9. Option
4. Function
5. Technology
8. Version
6. Operating Voltage
7. Organization
8. Version
Blank ----------------- Mother die
A ----------------------- 2’nd generation
B ----------------------- 3’rd generation
C ----------------------- 4’th generation
D ----------------------- 5’th generation
1. Memory Component
2. Device Type
6 ---------------------- Low Power SRAM
7 ---------------------- STRAM
C ---------------------- CellularRAM
9. Option
Blank ---- No optional mode
H ----------- Demultiplexed with DPD
J ------------ Demultiplexed with DPD & RBC
K ------------ Multiplexed with RBC
L ------------ Multiplexed with DPD & RBC
3. Density
4 ----------------------- 4M
8 ----------------------- 8M
16 --------------------- 16M
32 --------------------- 32M
64 --------------------- 64M
28 --------------------- 128M
4. Function
2 ----Multiplexed async.
3-----Demultiplexed async. with page mode
4-----Demultiplexed async. with direct DPD
5-----Multiplexed sync.
6-----Optional mux/demuxed sync.
5. Technology
S ----------------------- Single Transistor & Trench Cell
10. Package
Blank ---------------------- Wafer
S
---------------------- 32 sTSOP1
T
---------------------- 32 TSOP1
U
---------------------- 44 TSOP2
P
---------------------- 48 FPBGA
Z
---------------------- 52 FPBGA
Y
---------------------- 54 FPBGA
V
---------------------- 90 FPBGA
11. Speed (@async.)
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
90 ---------------------- 90ns
10 --------------------- 100ns
12 --------------------- 120ns
6. Operating Voltage
V ----------------------- 3.3V
U ----------------------- 3.0V
S ----------------------- 2.5V
R ----------------------- 2.0V
P ----------------------- 1.8V
L ----------------------- 1.5V
7. Organization
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
12. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power
(Pb-Free&Green)
L ---------------------- Low Power
52