IDT IDT72T1885 2.5 volt high-speed terasyncâ ¢ fifo Datasheet

2.5 VOLT HIGH-SPEED TeraSync™ FIFO
18-BIT/9-BIT CONFIGURATIONS
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,
16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9
*IDT72T1845,
*IDT72T1865,
*IDT72T1885,
IDT72T18105,
*IDT72T1855
*IDT72T1875
*IDT72T1895
IDT72T18115
IDT72T18125
*SPECIFIED PRODUCTS ARE EOL - LAST TIME BUY EXPIRES MAY 26, 2018
FEATURES:
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Choose among the following memory organizations:
IDT72T1845 ⎯ 2,048 x 18/4,096 x 9
IDT72T1855 ⎯ 4,096 x 18/8,192 x 9
IDT72T1865 ⎯ 8,192 x 18/16,384 x 9
IDT72T1875 ⎯ 16,384 x 18/32,768 x 9
IDT72T1885 ⎯ 32,768 x 18/65,536 x 9
IDT72T1895 ⎯ 65,536 x 18/131,072 x 9
IDT72T18105 ⎯ 131,072 x 18/262,144 x 9
IDT72T18115 ⎯ 262,144 x 18/524,288 x 9
IDT72T18125 ⎯ 524,288 x 18/1,048,576 x 9
Up to 225 MHz Operation of Clocks
User selectable HSTL/LVTTL Input and/or Output
Read Enable & Read Clock Echo outputs aid high speed operation
User selectable Asynchronous read and/or write port timing
2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
3.3V Input tolerant
Mark & Retransmit, resets read pointer to user marked position
Write Chip Select (WCS) input enables/disables Write operations
Read Chip Select (RCS) synchronous to RCLK
Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
Program programmable flags by either serial or parallel means
Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags
FUNCTIONAL BLOCK DIAGRAM
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Separate SCLK input for Serial programming of flag offsets
User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
- x18 in to x18 out
Big-Endian/Little-Endian user selectable byte representation
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Empty, Full and Half-Full flags signal FIFO status
Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
JTAG port, provided for Boundary Scan function
Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)
PlasticBall Grid Array (PBGA)
Easily expandable in depth and width
Independent Read and Write Clocks (permit reading and writing
simultaneously)
High-performance submicron CMOS technology
Industrial temperature range (–40°°C to +85°°C) is available
Green parts are available, see ordering information
For IDT72T1845/55/65/75/85/95 functional replacement device use
IDT72T18125
D0 -Dn (x18 or x9)
LD
WEN WCLK/WR
SEN SCLK
WCS
INPUT REGISTER
ASYW
WRITE CONTROL
LOGIC
WRITE POINTER
BE
IP
CONTROL
LOGIC
IW
OW
BUS
CONFIGURATION
MRS
RESET
LOGIC
PRS
TCK
TRST
TMS
TDO
OFFSET REGISTER
RAM ARRAY
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
524,288 x 18 or 1,048,576 x 9
OUTPUT REGISTER
FLAG
LOGIC
READ POINTER
RT
MARK
ASYR
READ
CONTROL
LOGIC
JTAG CONTROL
(BOUNDARY SCAN)
RCLK/RD
REN
RCS
TDI
Vref
WHSTL
RHSTL
SHSTL
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
HSTL I/0
CONTROL
EREN
OE
Q0 -Qn (x18 or x9)
5909 drw01
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
© 2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2017
DSC-5909/20
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATIONS
A1 BALL PAD CORNER
A
WCS
PRS
LD
FF/IR
OW
HF
WCLK
MRS
FWFT/SI
PAF
FSEL0
SHSTL
WEN
WHSTL
VDDQ
VDDQ
VDDQ
BE
IP
ASYR
PFM
EREN
MARK
FSEL1
DNC
RHSTL
PAE
EF/OR
RCLK
VCC
VCC
VDDQ
VDDQ
VDDQ
REN
RT
B
C
D
ASYW
SEN
VDDQ
VCC
VCC
GND
GND
VCC
VCC
VDDQ
RCS
OE
SCLK
IW
VDDQ
VCC
GND
GND
GND
GND
GND
VCC
VDDQ
Q17
VREF
D17
VCC
GND
GND
GND
GND
GND
GND
VCC
VDDQ
Q16
D15
D16
VCC
GND
GND
GND
GND
GND
GND
VCC
VDDQ
Q15
D13
D14
VDDQ
VCC
GND
GND
GND
GND
VCC
VDDQ
Q14
Q13
D11
D12
VDDQ
VCC
VCC
GND
GND
VCC
VCC
VDDQ
Q12
Q11
D9
D10
VDDQ
VDDQ
VDDQ
VCC
VCC
VDDQ
VDDQ
VDDQ
Q10
Q9
D7
D5
D3
D1
TRST
TCK
TDI
ERCLK
Q1
Q3
Q5
Q8
D8
D6
D4
D2
D0
TMS
TD0
Q0
Q2
Q4
Q6
Q7
1
2
3
4
5
6
7
8
9
10
11
12
E
F
G
H
J
K
L
M
5909 drw02
NOTE:
1. DNC - Do Not Connect.
IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 Only
PBGA: 1mm pitch, 13mm x 13mm BB144 (Order code: BB)
TOP VIEW
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PIN CONFIGURATIONS (CONTINUED)
A1 BALL PAD CORNER
A
V CC
V CC
V CC
V CC
V CC
V CC
WCLK
PRS
GND
FF
EREN
RCLK
OE
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
V CC
V CC
V CC
V CC
V CC
V CC
WEN
MRS
GND
PAF
EF
REN
RCS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
V CC
V CC
V CC
V CC
V CC
V CC
WCS
LD
GND
HF
PAE
MARK
RT
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
V CC
V CC
V CC
FWFT/SI
OW
FS0
SHSTL
FS1
GND
BE
IP
DNC
RHSTL
ASYR
PFM
VDDQ
VDDQ
VDDQ
V CC
V CC
V CC
GND
GND
VDDQ
VDDQ
VDDQ
V CC
V CC
V CC
GND
GND
VDDQ
VDDQ
VDDQ
V CC
SEN
SCLK
WHSTL
GND
VDDQ
VDDQ
VDDQ
V CC
V CC
ASYW
GND
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
V CC
V CC
V CC
VREF
GND
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
V CC
V CC
V CC
IW
GND
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
DNC
DNC
DNC
GND
GND
GND
GND
GND
GND
VDDQ
DNC
DNC
DNC
DNC
DNC
GND
GND
DNC
DNC
DNC
DNC
DNC
DNC
GND
GND
DNC
DNC
DNC
DNC
DNC
DNC
GND
GND
DNC
DNC
DNC
DNC
DNC
DNC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DNC
DNC
DNC
DNC
DNC
D13
D10
D5
D4
D1
TMS
TDO
GND
Q0
Q2
Q3
Q8
Q11
Q14
DNC
DNC
DNC
D17
D14
D11
D7
D8
D2
TRST
TDI
GND
Q1
Q6
Q5
Q9
Q12
Q15
DNC
DNC
V CC
D16
D15
D12
D9
D6
D3
D0
TCK
GND
ERCLK
Q4
Q7
Q10
Q13
Q16
Q17
VDDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
B
C
D
E
F
G
H
V CC
J
K
L
M
N
P
R
T
U
V
18
5909 drw02a
NOTE:
1. DNC - Do Not Connect.
IDT72T18105/72T18115/72T18125 Only
PBGA: 1mm pitch, 19mm x 19mm BB240, BBG240 (Order code: BB)
TOP VIEW
3
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
DESCRIPTION:
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
operation, which consists of activating REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that PAE can be set to switch at a predefined number of locations
from the empty boundary and the PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming, WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via Dn. REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Qn regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect. PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the PAE (Programmable AlmostEmpty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the PAE and
PAF flags.
If asynchronous PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK. PAE is reset to HIGH on the LOWto-HIGH transition of WCLK. Similarly, the PAF is asserted LOW on the LOWto-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during Master Reset by the state of the Programmable Flag
Mode (PFM) pin.
This device includes a Retransmit from Mark feature that utilizes two control
inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation, RT goes LOW, will reset the read pointer to
this ‘marked’ location.
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 are exceptionally deep, extremely high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write
controls and a flexible Bus-Matching x18/x9 data flow. These FIFOs offer
several key user benefits:
• Flexible x18/x9 Bus-Matching on both read and write ports
• A user selectable MARK location for retransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translation on the read or write ports
• The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
• High density offerings up to 9 Mbit
Bus-Matching TeraSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (Dn) and a data output port (Qn), both of
which can assume either a 18-bit or a 9-bit width as determined by the state of
external control pins Input Width (IW) and Output Width (OW) pin during the
Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the WEN input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, also the RCS should be
tied LOW and the OE input used to provide three-state control of the outputs, Qn.
The output port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the RHSTL input during a master reset.
An Output Enable (OE) input is provided for three-state control of the outputs.
A Read Chip Select (RCS) input is also provided, the RCS input is synchronized
to the read clock, and also provides three-state control of the Qn data outputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronous operation of the output port, RCS should be enabled, held LOW.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the FIFO that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to EREN and ERCLK, this is very useful when data is being read at
high speed. The ERCLK and EREN outputs are non-functional when the Read
port is setup for Asynchronous mode.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
4
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x18) and read
out of the FIFO in small word (x9) format. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired is
configured during master reset by the state of the Big-Endian (BE) pin.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D0-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8 during the parallel
programming of the flag offsets. If Non-Interspersed Parity mode is selected,
then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode
is selected during Master Reset by the state of the IP input pin. This mode is
relevant only when the input width is set to x18 mode.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 are fabricated using high speed submicron
CMOS technology.
5
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PARTIAL RESET (PRS)
MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR)
READ CLOCK (RCLK/RD)
WRITE ENABLE (WEN)
READ ENABLE (REN)
WRITE CHIP SELECT (WCS)
LOAD (LD)
(x18, x9) DATA IN (D0 - Dn)
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE (OE)
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
READ CHIP SELECT (RCS)
(x18, x9) DATA OUT (Q0 - Qn)
RCLK ECHO, ERCLK
REN ECHO, EREN
MARK
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
5909 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IW
OW
Write Port Width
Read Port Width
L
L
x18
x18
L
H
x18
x9
H
L
x9
x18
H
H
x9
x9
6
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION
Symbol
Name
(1)
ASYR Asynchronous
Read Port
(1)
ASYW Asynchronous
Write Port
BE(1)
Big-Endian/
Little-Endian
D0–D17 Data Inputs
EF/OR
Empty Flag/
Output Ready
ERCLK RCLK Echo
EREN
Read Enable Echo
FF/IR
Full Flag/
Input Ready
FSEL0(1) Flag Select Bit 0
FSEL1(1) Flag Select Bit 1
FWFT/
SI
First Word Fall
Through/Serial In
HF
Half-Full Flag
IP(1)
Interspersed Parity
IW(1)
Input Width
LD
Load
MARK
Mark for Retransmit
MRS
Master Reset
OE
Output Enable
OW(1)
Output Width
PAE
Programmable
Almost-Empty Flag
Programmable
Almost-Full Flag
PAF
PFM(1)
Programmable
Flag Mode
I/O TYPE
LVTTL
INPUT
LVTTL
INPUT
LVTTL
INPUT
HSTL-LVTTL
INPUT
HSTL-LVTTL
OUTPUT
Description
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
will select Asynchronous operation.
During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset
will select Little-Endian format.
Data inputs for an 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins should be tied to GND.
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is
OUTPUT full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for
writing to the FIFO memory.
LVTTL
During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the
INPUT
programmable flags PAE and PAF. There are up to eight possible settings available.
LVTTL
During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the
INPUT
programmable flags PAE and PAF. There are up to eight possible settings available.
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
INPUT
functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be setup in IDT Standard mode.
HSTL-LVTTL HF indicates whether the FIFO memory is more or less than half-full.
OUTPUT
LVTTL
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
INPUT
Parity mode.
LVTTL
This pin, along with OW, selects the bus width of the write port. See Table 1 for bus size configuration.
INPUT
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
INPUT
determines one of eight default offset values for the PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
INPUT
operation will reset the read pointer to this position.
HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
INPUT
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings,
serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode,
interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Qn. During a Master or Partial Reset the
INPUT
OE input is the only input that provide High-Impedance control of the data outputs.
LVTTL
This pin, along with IW, selects the bus width of the read port. See Table 1 for bus size configuration.
INPUT
HSTL-LVTTL PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty
OUTPUT Offset register. PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
HSTL-LVTTL PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
OUTPUT the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal
to m.
LVTTL
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
INPUT
PFM will select Synchronous Programmable flag timing mode.
7
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
Description
PRS
Partial Reset
HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
INPUT
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
HSTL-LVTTL Data outputs for an 18- or 9-bit bus. When in 9-bit mode, any unused output pins should not be connected.
Q0–Q17 Data Outputs
OUTPUT Outputs are not 5V tolerant regardless of the state of OE and RCS.
RCLK/ Read Clock/
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK
RD
Read Strobe
INPUT
reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded
into the offset registers is output on a rising edge of RCLK. If Asynchronous operation of the read port has been
selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN should be tied LOW.
RCS
Read Chip Select HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
INPUT
a Master or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance
regardless of RCS.
REN
Read Enable
HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enables RCLK for reading data from the
INPUT
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN
input should be tied LOW.
(1)
RHSTL Read Port HSTL
LVTTL
This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select
INPUT
required, this input must be tied HIGH. Otherwise it should be tied LOW.
RT
Retransmit
HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH
INPUT
in FWFT mode) and doesn’t disturb the write pointer, programming method, existing timing mode or programmable
flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the ‘mark’ location.
SCLK Serial Clock
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT
SEN is enabled.
SEN
Serial Enable
HSTL-LVTTL SEN enables serial loading of programmable flag offsets.
INPUT
SHSTL System HSTL
LVTTL
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select
INPUT
TCK(2)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
INPUT
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI(2)
JTAG Test Data
Input
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test
INPUT
data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass
Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO(2)
JTAG Test Data
Output
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test
OUTPUT data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register
and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR
controller states.
TMS(2)
JTAG Mode
Select
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST(2) JTAG Reset
WEN
WCS
WCLK/
WR
HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
INPUT
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.
Write Enable
HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into
INPUT
the FIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
Write Chip Select HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
Write Clock/
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of WCLK
Write Strobe
INPUT
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
8
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
WHSTL
Write Port HSTL
Select
+2.5V Supply
Ground Pin
Reference
Voltage
LVTTL
INPUT
I
I
I
O/P Rail Voltage
I
(1)
V CC
GND
Vref
VDDQ
Description
This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must
be tied HIGH. Otherwise it should be tied LOW.
These are VCC supply inputs and must be connected to the 2.5V supply rail.
These are Ground pins and must be connected to the GND rail.
This is a Voltage Reference input and must be connected to a voltage level determined from the table,
“Recommended DC Operating Conditions”. This provides the reference voltage when using HSTL class
inputs. If HSTL class inputs are not being used, this pin should be tied LOW.
This pin should be tied to the desired voltage rail for providing power to the output drivers.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to Figures 6-8.
9
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
ABSOLUTE MAXIMUM RATINGS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
VTERM
Rating
Terminal Voltage
with respect to GND
Commercial
–0.5 to +3.6(2)
Unit
V
Symbol
Parameter(1)
Conditions
Max.
Unit
CIN
Input
Capacitance
VIN = 0V
10
pF
TSTG
Storage Temperature
–55 to +125
°C
COUT(1,2)
VOUT = 0V
10
pF
IOUT
DC Output Current
–50 to +50
mA
Output
Capacitance
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
(2,3)
(3)
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
VCC
GND
Parameter
Supply Voltage
Supply Voltage
Min.
2.375
0
Typ.
2.5
0
Max.
2.625
0
Unit
V
V
VIH
Input High Voltage
⎯ LVTTL
⎯ eHSTL
⎯ HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
VDDQ+0.3
VDDQ+0.3
V
V
V
VIL
Input Low Voltage
⎯ LVTTL
⎯ eHSTL
⎯ HSTL
-0.3
-0.3
-0.3
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
Voltage Reference Input
⎯ eHSTL
⎯ HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
0
—
70
°C
-40
—
85
°C
VREF(1)
TA
Operating Temperature Commercial
TA
Operating Temperature Industrial
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. Outputs are not 3.3V tolerant.
10
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
Parameter
ILI
ILO
Input Leakage Current
Output Leakage Current
VOH(5)
Output Logic “1” Voltage,
VOL
Output Logic “0” Voltage,
IOH = –8 mA
IOH = –8 mA
IOH = –8 mA
IOL = 8 mA
IOL = 8 mA
IOL = 8 mA
@VDDQ = 2.5V ± 0.125V (LVTTL)
@VDDQ = 1.8V ± 0.1V (eHSTL)
@VDDQ = 1.5V ± 0.1V (HSTL)
@VDDQ = 2.5V ± 0.125V (LVTTL)
@VDDQ = 1.8V ± 0.1V (eHSTL)
@VDDQ = 1.5V ± 0.1V (HSTL)
Min.
Max.
Unit
–10
–10
10
10
μA
μA
VDDQ -0.4
VDDQ -0.4
VDDQ -0.4
—
—
—
—
—
—
0.4V
0.4V
0.4V
V
V
V
V
V
V
IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895
ICC1(1,2)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
40
60
60
mA
mA
mA
ICC2(1)
Standby VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
10
50
50
mA
mA
mA
IDT72T18105/72T18115/72T18125
ICC1(1,2)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
50
70
70
mA
mA
mA
ICC2(1)
Standby VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
20
60
60
mA
mA
mA
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. For the IDT72T18105/72T18115/72T18125, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 1.0 x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (1.0 x fs), fs = WCLK = RCLK frequency (in MHz)
For the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz).
3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)
with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000
fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,
N= Number of outputs switching.
4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).
5. Outputs are not 3.3V tolerant.
11
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) ⎯ SYNCHRONOUS TIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Symbol
fC
tA
tCLK
tCLKH
tCLKL
tDS
tDH
tENS
tENH
tLDS
tLDH
tWCSS
tWCSH
fS
tSCLK
tSCKH
tSCKL
tSDS
tSDH
tSENS
tSENH
tRS
tRSS
tHRSS
tRSR
tRSF
tWFF
tREF
tPAFS
tPAES
tERCLK
tCLKEN
tRCSLZ
tRCSHZ
tSKEW1
tSKEW2
Parameter
Clock Cycle Frequency (Synchronous)
Data Access Time
Clock Cycle Time
Clock High Time
Clock Low Time
Data Setup Time
Data Hold Time
Enable Setup Time
Enable Hold Time
Load Setup Time
Load Hold Time
WCS setup time
WCS hold time
Clock Cycle Frequency (SCLK)
Serial Clock Cycle
Serial Clock High
Serial Clock Low
Serial Data In Setup
Serial Data In Hold
Serial Enable Setup
Serial Enable Hold
Reset Pulse Width(3)
Reset Setup Time
HSTL Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to Synchronous Programmable Almost-Full Flag
Read Clock to Synchronous Programmable Almost-Empty Flag
RCLK to Echo RCLK output
RCLK to Echo REN output
RCLK to Active from High-Z(4)
RCLK to High-Z(4)
Skew time between RCLK and WCLK for EF/OR and FF/IR
Skew time between RCLK and WCLK for PAE and PAF
Commercial
Com’l & Ind’l(2)
IDT72T1845L4-4
IDT72T1855L4-4
IDT72T1865L4-4
IDT72T1875L4-4
IDT72T1885L4-4
IDT72T1895L4-4
IDT72T18105L4-4
IDT72T18115L4-4
IDT72T18125L4-4
IDT72T1845L5
IDT72T1855L5
IDT72T1865L5
IDT72T1875L5
IDT72T1885L5
IDT72T1895L5
IDT72T18105L5
IDT72T18115L5
IDT72T18125L5
Min.
—
0.6
4.44
2.0
2.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
—
100
45
45
15
5
5
5
30
15
4
10
—
—
—
—
—
—
—
—
—
3.5
4
Max.
225
3.4
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
10
3.4
3.4
3.4
3.4
3.8
3.4
3.4
3.4
—
—
Min.
—
0.6
5
2.3
2.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
—
100
45
45
15
5
5
5
30
15
4
10
—
—
—
—
—
—
—
—
—
4
5
Max.
200
3.6
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
3.6
3.6
3.6
3.6
4
3.6
3.6
3.6
—
—
Commercial
Commercial
IDT72T1845L6-7
IDT72T1855L6-7
IDT72T1865L6-7
IDT72T1875L6-7
IDT72T1885L6-7
IDT72T1895L6-7
IDT72T18105L6-7 IDT72T18105L10
IDT72T18115L6-7 IDT72T18115L10
IDT72T18125L6-7 IDT72T18125L10
Min.
—
0.6
6.7
2.8
2.8
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
—
100
45
45
15
5
5
5
30
15
4
10
—
—
—
—
—
—
—
—
—
5
6
Max.
150
3.8
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
15
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
—
—
Min.
—
0.6
10
4.5
4.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
—
100
45
45
15
5
5
5
30
15
4
10
—
—
—
—
—
—
—
—
—
7
8
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
12
Max.
100
4.5
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
15
4.5
4.5
4.5
4.5
5
4.5
4.5
4.5
—
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS ⎯ ASYNCHRONOUS TIMING
(Commercial: VCC = 2.5V ± 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 5%, TA = -40°C to +85°C)
Symbol
fA
tAA
tCYC
tCYH
tCYL
tRPE
tFFA
tEFA
tPAFA
tPAEA
tOLZ
tOE
tOHZ
tHF
Parameter
Cycle Frequency (Asynchronous)
Data Access Time
Cycle Time
Cycle HIGH Time
Cycle LOW Time
Read Pulse after EF HIGH
Clock to Asynchronous FF
Clock to Asynchronous EF
Clock to Asynchronous Programmable Almost-Full Flag
Clock to Asynchronous Programmable Almost-Empty Flag
Output Enable to Output in Low Z(3)
Output Enable to Output Valid
Output Enable to Output in High Z(3)
Clock to HF
Commercial
Com’l & Ind’l(2)
IDT72T1845L4-4
IDT72T1855L4-4
IDT72T1865L4-4
IDT72T1875L4-4
IDT72T1885L4-4
IDT72T1895L4-4
IDT72T18105L4-4
IDT72T18115L4-4
IDT72T18125L4-4
IDT72T1845L5
IDT72T1855L5
IDT72T1865L5
IDT72T1875L5
IDT72T1885L5
IDT72T1895L5
IDT72T18105L5
IDT72T18115L5
IDT72T18125L5
Min.
—
0.6
10
4.5
4.5
8
—
—
—
—
0
—
—
—
Max.
100
8
—
—
—
—
8
8
8
8
—
3.4
3.4
8
Min.
—
0.6
12
5
5
10
—
—
—
—
0
—
—
—
Max.
83
10
—
—
—
—
10
10
10
10
—
3.6
3.6
10
Commercial
Commercial
IDT72T1845L6-7
IDT72T1855L6-7
IDT72T1865L6-7
IDT72T1875L6-7
IDT72T1885L6-7
IDT72T1895L6-7
IDT72T18105L6-7 IDT72T18105L10
IDT72T18115L6-7 IDT72T18115L10
IDT72T18125L6-7 IDT72T18125L10
Min.
—
0.6
15
7
7
12
—
—
—
—
0
—
—
—
Max.
66
12
—
—
—
—
12
12
12
12
—
3.8
3.8
12
Min.
—
0.6
20
8
8
14
—
—
—
—
0
—
—
—
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Values guaranteed by design, not currently tested.
13
Max.
50
14
—
—
—
—
14
14
14
14
—
4.5
4.5
14
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
AC TEST LOADS
HSTL
1.5V AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
VDDQ/2
0.25 to 1.25V
0.4ns
0.75
VDDQ/2
50Ω
Z0 = 50Ω
I/O
5909 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDED HSTL
1.8V AC TEST CONDITIONS
5
0.4 to 1.4V
0.4ns
0.9
VDDQ/2
tCD
(Typical, ns)
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
6
4
3
2
1
NOTE:
1. VDDQ = 1.8V±.
20 30 50
200
5909 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
2.5V LVTTL
2.5V AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
80 100
Capacitance (pF)
GND to 2.5V
1ns
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
14
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE & tOLZ
Output VCC
Normally
2
LOW
tOHZ
VCC
2
100mV
100mV
VOL
VOH
100mV
Output
Normally VCC
2
HIGH
100mV
VCC
2
5909 drw04b
NOTES:
1. REN is HIGH.
2. RCS is LOW.
READ CHIP SELECT ENABLE & DISABLE TIMING
VIH
tENH
RCS
VIL
tENS
RCLK
tRCSHZ
tRCSLZ
Output VCC
Normally
2
LOW
Output
Normally VCC
2
HIGH
100mV
VCC
2
100mV
VOL
VOH
100mV
100mV
VCC
2
5909 drw04c
NOTES:
1. REN is HIGH.
2. OE is LOW.
15
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 support two different timing modes of operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selection of which mode will operate is determined during Master Reset, by the
state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to Qn after three RCLK rising
edges, REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW once
(D/2 + 1) words were written into the FIFO. If x18 Input or x18 Output bus Width
is selected, (D/2 + 1) = the 1,025th word for the IDT72T1845, 2,049th word for
IDT72T1855, 4,097th word for the IDT72T1865, 8,193rd word for the
IDT72T1875, 16,385th word for the IDT72T1885, 32,769th word for the
IDT72T1895, 65,537th word for the IDT72T18105, 131,073rd word for the
IDT72T18115 and 262,145th word for the IDT72T18125. If both x9 Input and
x9 Output bus Widths are selected, (D/2 + 1) = the 2,049th word for the
IDT72T1845, 4,097th word for IDT72T1855, 8,193rd word for the IDT72T1865,
16,385th word for the IDT72T1875, 32,769th word for the IDT72T1885,
65,537th word for the IDT72T1895, 131,073rd word for the IDT72T18105,
262,145th word for the IDT72T18115 and 524,289th word for the IDT72T18125.
Continuing to write data into the FIFO will cause the Programmable Almost-Full
flag (PAF) to go LOW. Again, if no reads are performed, the PAF will go LOW
after (D-m) writes to the FIFO. If x18 Input or x18 Output bus Width is selected,
(D-m) = (2,048-m) writes for the IDT72T1845, (4,096-m) writes for the
IDT72T1855, (8,192-m) writes for the IDT72T1865, (16,384-m) writes for the
IDT72T1875, (32,768-m) writes for the IDT72T1885, (65,536-m) writes for the
IDT72T1895, (131,072-m) writes for the IDT72T18105, (262,144-m) writes
for the IDT72T18115 and (524,288-m) writes for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, (D-m) = (4,096-m) writes for the
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845, (8,192-m) writes for the IDT72T1855, (16,384-m) writes for the
IDT72T1865, (32,768-m) writes for the IDT72T1875, (65,536-m) writes for the
IDT72T1885, (131,072-m) writes for the IDT72T1895, (262,144-m) writes for
the IDT72T18105, (524,288-m) writes for the IDT72T18115 and (1,048,576-m)
writes for the IDT72T18125. The offset “m” is the full offset value. The default
setting for these values are stated in the footnote of Table 2. This parameter is
also user programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D writes
to the FIFO. If the x18 Input or x18 Output bus Width is selected, D = 2,048 writes
for the IDT72T1845, 4,096 writes for the IDT72T1855, 8,192 writes for the
IDT72T1865, 16,384 writes for the IDT72T1875, 32,768 writes for the
IDT72T1885, 65,536 writes for the IDT72T1895, 131,072 writes for the
IDT72T18105, 262,144 writes for the IDT72T18115 and 524,288 writes for the
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, D = 4,096
writes for the IDT72T1845, 8,192 writes for the IDT72T1855, 16,384 writes for
the IDT72T1865, 32,768 writes for the IDT72T1875, 65,536 writes for the
IDT72T1885, 131,072 writes for the IDT72T1895, 262,144 writes for the
IDT72T18105, 524,288 writes for the IDT72T18115 and 1,048,576 writes for
the IDT72T18125, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the EF will go LOW inhibiting
further read operations. REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO, WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of
Table 2. This parameter is also user programmable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the (D/2 + 2)
words were written into the FIFO. If x18 Input or x18 Output bus Width is selected,
(D/2 + 2) = the 1,026th word for the IDT72T1845, 2,050th word for IDT72T1855,
4,098th word for the IDT72T1865, 8,194th word for the IDT72T1875, 16,386th
word for the IDT72T1885, 32,770th word for the IDT72T1895, 65,538th word
for the IDT72T18105, 131,074th word for the IDT72T18115 and 262,146th
word for the IDT72T18125. If both x9 Input and x9 Output bus Widths are
selected, (D/2 + 2) = the 2,050th word for the IDT72T1845, 4,098th word for
IDT72T1855, 8,194th word for the IDT72T1865, 16,386th word for the
IDT72T1875, 32,770th word for the IDT72T1885, 65,538th word for the
IDT72T1895, 131,074th word for the IDT72T18105, 262,146th word for the
IDT72T18115 and 524,290th word for the IDT72T18125. Continuing to write
data into the FIFO will cause the PAF to go LOW. Again, if no reads are
performed, the PAF will go LOW after (D-m) writes to the FIFO. If x18 Input or
x18 Output bus Width is selected, (D-m) = (2,049-m) writes for the IDT72T1845,
16
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, D = 4,097
writes for the IDT72T1845, 8,193 writes for the IDT72T1855, 16,385 writes
for the IDT72T1865, 32,769 writes for the IDT72T1875, 65,537 writes for the
IDT72T1885, 131,073 writes for the IDT72T1895, 262,145 writes for the
IDT72T18105, 524,289 writes for the IDT72T18115 and 1,048,577 writes for
the IDT72T18125, respectively. Note that the additional word in FWFT mode
is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO, OR will go
HIGH inhibiting further read operations. REN is ignored when the FIFO is
empty.
When configured in FWFT mode, the OR flag output is triple registerbuffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 14, 15,
16 and 19.
(4,097-m) writes for the IDT72T1855, (8,193-m) writes for the IDT72T1865,
(16,385-m) writes for the IDT72T1875, (32,769-m) writes for the IDT72T1885,
(65,536-m) writes for the IDT72T1895, (131,073-m) writes for the IDT72T18105,
(262,145-m) writes for the IDT72T18115 and (524,289-m) writes for the
IDT72T18125. If both x9 Input and x9 Output bus Widths are selected, (D-m)
= (4,097-m) writes for the IDT72T1845, (8,193-m) writes for the IDT72T1855,
(16,385-m) writes for the IDT72T1865, (32,769-m) writes for the IDT72T1875,
(65,537-m) writes for the IDT72T1885, (131,073-m) writes for the IDT72T1895,
(262,145-m) writes for the IDT72T18105, (524,289-m) writes for the
IDT72T18115 and (1,048,577-m) writes for the IDT72T18125. The offset m
is the full offset value. The default setting for these values are stated in the footnote
of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset, IR will go HIGH after
D writes to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 2,049
writes for the IDT72T1845, 4,097 writes for the IDT72T1855, 8,193 writes for
the IDT72T1865, 16,385 writes for the IDT72T1875, 32,769 writes for the
IDT72T1885, 65,536 writes for the IDT72T1895, 131,073 writes for the
IDT72T18105, 262,145 writes for the IDT72T18115 and 524,289 writes for the
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
the LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on LD
during Master Reset selects serial loading of offset values. A LOW on LD during
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
IDT72T1845
*LD
L
L
L
L
H
H
H
H
FSEL1
H
L
L
H
L
H
L
H
FSEL0
L
H
L
H
L
L
H
H
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Offsets n,m
All Other
x9 to x9
Modes
Mode
511
511
255
255
127
127
63
63
31
1,023
15
31
7
15
3
7
IDT72T1855, 72T1865, 72T1875, 72T1885,
72T1895, 72T18105, 72T18115, 72T18125
*LD
FSEL1
FSEL0
Offsets n,m
H
L
L
1,023
L
H
L
511
L
L
H
255
L
L
L
127
L
H
H
63
H
H
L
31
H
L
H
15
H
H
H
7
*LD
FSEL1
FSEL0
Program Mode
H
X
X
Serial(3)
L
X
X
Parallel(4)
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for PAF and PAE flags
by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly, PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE is reset toHIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 25
for asynchronous PAF timing and Figure 26 for asynchronous PAE timing.
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
IW = OW = x9
IW = x18 or
OW = x18
IDT72T1845
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
0
Number of
Words in
FIFO
(1)
(n+1) to 1,024
(1)
1 to n
0
0
0
1 to n (1)
1 to n (1)
0
1 to n
(1)
H
H
H
L
L
H
H
H
L
H
(n+1) to 8,192
(n+1) to 16,384
H
H
H
H
H
1,025 to (2048-(m+1))
2,049 to (4,096-(m+1))
4,097 to (8,192-(m+1))
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
H
H
L
H
H
(2048-m) to 2,047
(4,096-m) to 4,095
(8,192-m) to 8,191
(16,384-m) to 16,383
(32,768-m) to 32,767
H
L
L
H
H
2,048
4,096
8,192
16,384
32,768
L
L
L
H
H
(n+1) to 2,048
(n+1) to 4,096
IW = OW = x9
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IW = x18 or
OW = x18
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
0
Number of
Words in
FIFO
1 to n
FF PAF HF PAE EF
1 to n
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
1 to n
0
0
0
(1)
(1)
1 to n (1)
(n+1) to 65,536
1 to n
(n+1) to 131,072
(1)
(n+1) to 262,144
IDT72T18125
FF
0
H
H
H
L
1 to n (1)
H
H
H
L
H
(n+1) to 524,288
H
H
H
H
H
(262,144-m) to 262,143
131,072
(524,288-m) to 524,287
524,288
262,144
L
H
H
L
H
H
(1,048,576-m) to 1,048,575
H
L
L
H
H
1,048,576
L
L
L
H
H
65,537 to (131,072-(m+1)) 131,073 to (262,144-(m+1)) 262,145 to (524,288-(m+1)) 524,289 to (1,048,576-(m+1))
(131,072-m) to 131,071
PAF HF PAE EF
NOTE:
1. See table 2 for values for n, m.
TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE
IW = OW = x9
IW = x18 or
OW = x18
Number of
Words in
FIFO
IDT72T1845
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
PAF HF PAE OR
0
0
0
0
0
L
H
H
L
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
L
H
H
L
L
(n+2) to 1,025
(n+2) to 2,049
(n+2) to 4,097
(n+2) to 8,193
(n+2) to 16,385
L
H
H
H
L
1,026 to (2049-(m+1))
(2049-m)
to 2,048
2,049
4,098 to (8,193-(m+1))
8,194 to (16,385-(m+1))
16,386 to (32,769-(m+1))
L
H
L
H
L
(4,097-m) to 4,096
(8,193-m) to 8,192
(16,385-m) to 16,384
(32,769-m) to 32,768
L
L
L
H
L
4,097
8,193
16,385
32,769
H
L
L
H
L
IDT72T18125
IW = OW = x9
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
0
1 to n+1 (1)
(n+2) to 32,769
0
0
1 to n+1 (1)
1 to n+1 (1)
(n+2) to 65,537
0
(n+2) to 131,073
IR
65,537
PAF HF PAE OR
L
H
H
L
H
1 to n+1 (1)
1 to n+1 (1)
L
H
H
L
L
(n+2) to 262,145
(n+2) to 524,289
L
H
H
H
L
L
H
L
H
L
0
32,770 to (65,537-(m+1)) 65,538 to (131,073-(m+1)) 131,074 to (262,145-(m+1)) 262,146 to (524,289-(m+1)) 524,290 to (1,048,577-(m+1))
(65,537-m) to 65,536
H
2,050 to (4,097-(m+1))
IW = x18 or
OW = x18
Number of
Words in
FIFO
IR
(131,073-m) to 131,072
(262,145-m) to 262,144
(524,289-m) to 524,288
(1,048,577-m) to 1,048,576
L
L
L
H
L
131,073
262,145
524,289
1,048,577
H
L
L
H
L
5909 drw05
NOTE:
1. See table 2 for values for n, m.
2. Number of Words in FIFO = Depth + Output Register.
18
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
LD WEN REN SEN WCLK
0
0
1
RCLK
X
1
IDT72T1845,
IDT72T1865,
IDT72T1885,
IDT72T18105,
IDT72T18125
x18 input
0
1
0
1
X
x18 input
1
1
X
0
X
X
1
1
1
1
0
X
X
1
X
0
X
X
1
1
1
X
X
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
x18 input
x9 input
(72T18105/115/125)
Empty Offset Empty Offset (LSB)
Full Offset
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
0
IDT72T1855
IDT72T1875
IDT72T1895
IDT72T18115
Parallel write to registers:
x18 input
x9 input
(72T18105/115/125)
Empty Offset Empty Offset (LSB)
Empty Offset (MSB)
Full Offset
Full Offset (LSB)
Full Offset (MSB)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
x9 input
(72T1895/105/115/125)
Empty Offset (LSB)
Empty Offset
Empty Offset (MSB)
Full Offset (LSB)
Full Offset
Full Offset (MSB)
x9 input
(72T1895/105/115/125)
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
x9 to x9 Mode
Serial shift into registers:
24 bits for the IDT72T1845
26 bits for the IDT72T1855
28 bits for the IDT72T1865
30 bits for the IDT72T1875
32 bits for the IDT72T1885
34 bits for the IDT72T1895
36 bits for the IDT72T18105
38 bits for the IDT72T18115
40 bits for the IDT72T18125
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Empty Offset (LSB)
Empty Offset
Empty Offset (MSB)
Full Offset (LSB)
Full Offset
Full Offset (MSB)
All Other Modes
Serial shift into registers:
22 bits for the IDT72T1845
24 bits for the IDT72T1855
26 bits for the IDT72T1865
28 bits for the IDT72T1875
30 bits for the IDT72T1885
32 bits for the IDT72T1895
34 bits for the IDT72T18105
36 bits for the IDT72T18115
38 bits for the IDT72T18125
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
No Operation
X
Write Memory
Read Memory
X
No Operation
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
19
5909 drw06
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
1st Parallel Offset Write/Read Cycle
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q8
D/Q0
D/Q0
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
8
7
6
5
4
8
3
2
7
6
5
4
3
2
1
1
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER
2nd Parallel Offset Write/Read Cycle
16
D/Q8
15
14
13
12
11
10
9
D/Q0
EMPTY OFFSET REGISTER
16
15
14
13
12
3rd Parallel Offset Write/Read Cycle
11
10
D/Q8
9
D/Q0
EMPTY OFFSET REGISTER
20
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
6
5
17
D/Q0
FULL OFFSET REGISTER
FULL OFFSET REGISTER
7
18
4th Parallel Offset Write/Read Cycle
D/Q8
8
19
4
3
2
8
1
7
6
5
4
3
2
1
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER
4th Parallel Offset Write/Read Cycle
16
D/Q8
15
14
13
12
11
10
9
D/Q0
FULL OFFSET REGISTER
6th Parallel Offset Write/Read Cycle
16
15
14
13
12
11
10
9
D/Q8
D/Q0
FULL OFFSET REGISTER
20
IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895(1)⎯ x9 Bus Width
Data Inputs/Outputs
EMPTY OFFSET REGISTER
1st Parallel Offset Write/Read Cycle
Data Inputs/Outputs
D/Q17
D/Q16
D/Q0
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1
D/Q8
18
# of Bits Used
D/Q0
EMPTY OFFSET (LSB) REGISTER
Non-Interspersed
Parity
Interspersed
Parity
16 15 14 13 12 11 10 9 8 7 6 5
16 15 14 13 12 11 10 9
4 3 2 1
8 7 6 5 4 3 2 1
D/Q8
# of Bits Used
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
EMPTY OFFSET (MSB) REGISTER
D/Q17
D/Q16
2nd Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
FULL OFFSET REGISTER
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
8 7 6 5 4 3 2
16 15 14 13 12 11 10 9
D/Q0
3rd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
FULL OFFSET (LSB) REGISTER
D/Q17
D/Q16
IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895⎯ x18 Bus Width
x9 to x9 Mode
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
19 18 17
19 18 17
1
1
D/Q8
# of Bits Used:
12 bits for the IDT72T1845
13 bits for the IDT72T1855
14 bits for the IDT72T1865
15 bits for the IDT72T1875
16 bits for the IDT72T1885
17 bits for the IDT72T1895
18 bits for the IDT72T18105
19 bits for the IDT72T18115
20 bits for the IDT72T18125
Note: All unused bits of the
LSB & MSB are don’t care
17
IDT72T1895/72T18105/72T18115/72T18125(1)⎯ x9 Bus Width
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q16
19
D/Q0
16 15 14 13 12 11 10 9 8 7 6 5 4 3
16 15 14 13 12 11 10 9
8 7 6 5 4 3
2 1
2 1
D/Q8
All Other Modes
# of Bits Used:
11 bits for the IDT72T1845
12 bits for the IDT72T1855
13 bits for the IDT72T1865
14 bits for the IDT72T1875
15 bits for the IDT72T1885
16 bits for the IDT72T1895
17 bits for the IDT72T18105
18 bits for the IDT72T18115
19 bits for the IDT72T18125
Note: All unused bits of the
LSB & MSB are don’t care
4th Parallel Offset Write/Read Cycle
D/Q17
D/Q16
Data Inputs/Outputs
FULL OFFSET (MSB) REGISTER
4666 drw 06
D/Q0
19 18 17
19 18 17
IDT72T18105/72T18115/72T18125⎯ x18 Bus Width
5909 drw07
NOTES:
1. When programming the IDT72T1895 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72T1895 with an output
bus width of x9 and input bus width of x18, 4 read cycles will be required. A total of 6 program/read cycles will be required if both the input and output bus widths are set to x9.
2. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
20
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
For example, programming PAE and PAF on the IDT72T1895 configured
for x18 bus width proceeds as follows: when LD and WEN are set LOW, data
on the inputs Dn are written into the LSB of the Empty Offset Register on the first
LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH transition
of WCLK, data are written into the MSB of the Empty Offset Register. On the third
LOW-to-HIGH transition of WCLK, data are written into the LSB of the Full Offset
Register. On the fourth LOW-to-HIGH transition of WCLK, data are written into
the MSB of the Full Offset Register. The fifth LOW-to-HIGH transition of WCLK,
data are written, once again to the Empty Offset Register. Note that for x9 bus
width, one extra Write cycle is required for both the Empty Offset Register and
Full Offset Register. See Figure 21, Parallel Loading of Programmable Flag
Registers, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers does
not have to occur at one time. One, two or more offset registers can be written
and then by bringing LD HIGH, write operations can be redirected to the FIFO
memory. When LD is set LOW again, and WEN is LOW, the next offset register
in sequence is written to. As an alternative to holding WEN LOW and toggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling WEN.
Note that the status of a programmable flag (PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus tPAF, PAE will be valid after the next two rising
RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-Qn
pins when LD is set LOW and REN is set LOW. It is important to note that
consecutive reads of the offset registers is not permitted. The read operation must
be disabled for a minimum of one RCLK cycle in between offset register
accesses. If the FIFO is configured for an input bus width and output bus width
both set to x9, then the total number of read operations required to read the offset
registers is 4 for the IDT72T1845/72T1855/72T1865/72T1875/72T1885 or 6
for the IDT72T1895/72T18105/72T18115/72T18125. Refer to Figure 3,
Programmable Flag Offset Programming Sequence, for a detailed diagram
of the data input lines D0-Dn used during parallel programming. If the FIFO is
configured for an input to output bus width of x9 to x18, x18 to x9 or x18 to x18,
then the following number of read operations are required: for an output bus
width of x18 a total of 2 read operations will be required to read the offset registers
for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 or 4 for
the IDT72T18105/72T18115/72T18125. For an output bus width of x9 a total
of 4 read operations will be required to read the offset registers for the
IDT72T1845/72T1855/72T1865/72T1875/72T1885. A total of 6 will be required for the IDT72T1895/72T18105/72T18115/72T18125. Refer to Figure
3, Programmable Flag Offset Programming Sequence, for a detailed diagram.
See Figure 22, Parallel Read of Programmable Flag Registers, for the timing
diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting REN, LD,
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, SEN, SCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when LD and SEN are set LOW, data on the SI input are written, one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. If x9 to x9 mode is selected, a total of 24 bits for the
IDT72T1845, 26 bits for the IDT72T1855, 28 bits for the IDT72T1865, 30 bits
for the IDT72T1875, 32 bits for the IDT72T1885, 34 bits for the IDT72T1895,
36 bits for the IDT72T18105, 38 bits for the IDT72T18115 and 40 bits for the
IDT72T18125. For any other mode of operation (that includes x18 bus width
on either the Input or Output), minus 2 bits from the values above. So, a total
of 22 bits for the IDT72T1845, 24 bits for the IDT72T1855, 26 bits for the
IDT72T1865, 28 bits for the IDT72T1875, 30 bits for the IDT72T1885, 32 bits
for the IDT72T1895, 34 bits for the IDT72T18105, 36 bits for the IDT72T18115
and 38 bits for the IDT72T18125. See Figure 20, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed
selectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing LD and SEN HIGH, data can be written to FIFO memory via
Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set LD LOW
and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising SCLK edge that achieves the above criteria;
PAF will be valid after three more rising WCLK edges plus tPAF, PAE will be valid
after the next three rising RCLK edges plus tPAE.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of PAE and PAF values can be achieved by using a combination
of the LD, WCLK , WEN and Dn input pins. If the FIFO is configured for an input
bus width and output bus width both set to x9, then the total number of write
operations required to program the offset registers is 4 for the IDT72T1845/
72T1855/72T1865/72T1875/72T1885 or 6 for the IDT72T1895/72T18105/
72T18115/72T18125. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram of the data input lines D0-Dn used
during parallel programming. If the FIFO is configured for an input to output bus
width of x9 to x18, x18 to x9 or x18 to x18, then the following number of write
operations are required. For an input bus width of x18 a total of 2 write operations
will be required to program the offset registers for the IDT72T1845/72T1855/
72T1865/72T1875/72T1885/72T1895 or 4 for the IDT72T18105/72T18115/
72T18125. For an input bus width of x9 a total of 4 write operations will be
required to program the offset registers for the IDT72T1845/72T1855/72T1865/
72T1875/72T1885. A total of 6 will be required for the IDT72T1895/72T18105/
72T18115/72T18125. Refer to Figure 3, Programmable Flag Offset Programming Sequence, for a detailed diagram.
21
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
or both together. When REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
edge when the ‘MARK’ input is HIGH and OR is LOW. The rising RCLK edge
‘marks’ the data present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a rising RCLK edge occurs while
MARK is LOW.
Once a marked location has been set (and the device is still in retransmit
can be initiated by a rising RCLK edge while the retransmit input (RT) is LOW.
REN must be HIGH (reads disabled) before bringing RT LOW. The device
indicates the start of retransmit setup by setting OR HIGH.
When OR goes LOW, retransmit setup is complete and on the next rising
RCLK edge after retransmit setup is complete, (RT goes HIGH), the contents
of the first retransmit location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of REN, a
LOW on REN is not required for the first word. Reading all subsequent words
requires a LOW on REN to enable the rising RCLK edge. See Figure 19,
Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.
Note, for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/
72T1895 there must be a minimum of 32 bytes of data between the write pointer
and read pointer when the MARK is asserted, for the IDT72T18105/72T18115
there must be a minimum of 128 bytes and for the IDT72T18125 there must be
a minimum of 256 bytes. Remember, 2(x9) bytes = 1(x18) word. (32 bytes =
16 word = 8 long words). Also, once the MARK is set, the write pointer will not
increment past the “marked” location until the MARK is deasserted. This
prevents “overwriting” of retransmit data.
RETRANSMIT FROM MARK OPERATION
The Retransmit from Mark feature allows FIFO data to be read repeatedly
starting at a user-selected position. The FIFO is first put into retransmit mode that
will ‘mark’ a beginning word and also set a pointer that will prevent ongoing FIFO
write operations from over-writing retransmit data. The retransmit data can be
read repeatedly any number of times from the ‘marked’ position. The FIFO can
be taken out of retransmit mode at any time to allow normal device operation.
The ‘mark’ position can be selected any number of times, each selection overwriting the previous mark location. Retransmit operation is available in both IDT
standard and FWFT modes.
During IDT standard mode the FIFO is put into retransmit mode by a Lowto-High transition on RCLK when the ‘MARK’ input is HIGH and EF is HIGH.
The rising RCLK edge ‘marks’ the data present in the FIFO output register as
the first retransmit data. The FIFO remains in retransmit mode until a rising edge
on RCLK occurs while MARK is LOW.
Once a ‘marked’ location has been set (and the device is still in retransmit
mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK
while the retransmit input (RT) is LOW. REN must be HIGH (reads disabled)
before bringing RT LOW. The device indicates the start of retransmit setup by
setting EF LOW, also preventing reads. When EF goes HIGH, retransmit setup
is complete and read operations may begin starting with the first data at the MARK
location. Since IDT standard mode is selected, every word read including the
first ‘marked’ word following a retransmit setup requires a LOW on REN (read
enabled).
Note, write operations may continue as normal during all retransmit
functions, however write operations to the ‘marked’ location will be prevented.
See Figure 18, Retransmit from Mark (IDT standard mode), for the relevant
timing diagram.
HSTL/LVTTL I/O
Both the write port and read port are user selectable between HSTL or
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
control pins are selectable via SHSTL, see Table 5 for details of groupings.
Note, that when the write port is selected for HSTL mode, the user can reduce
the power consumption (in stand-by mode by utilizing the WCS input).
All “Static Pins” must be tied to VCC or GND. These pins are LVTTL only,
and are purely device configuration pins.
TABLE 5 — I/O CONFIGURATION
WHSTL SELECT
WHSTL: HIGH = HSTL
LOW = LVTTL
Dn (I/P)
WCLK/WR (I/P)
WEN (I/P)
WCS (I/P)
RHSTL SELECT
RHSTL: HIGH = HSTL
LOW = LVTTL
RCLK/RD (I/P)
RCS (I/P)
MARK (I/P)
REN (I/P)
OE (I/P)
RT (I/P)
Qn (O/P)
EF/OR (O/P)
PAF (O/P)
EREN (O/P)
PAE (O/P)
FF/IR (O/P)
HF (O/P)
ERCLK (O/P)
TDO (O/P)
SHSTL SELECT
STATIC PINS
SHSTL: HIGH = HSTL
LOW = LVTTL
LVTTL ONLY
SCLK (I/P)
LD (I/P)
MRS (I/P)
TCK (I/P)
TMS (I/P)
SEN (I/P)
FWFT/SI (I/P)
22
PRS (I/P)
TRST (I/P)
TDI (I/P)
IW (I/P)
BM (I/P)
ASYR (I/P)
IP (I/P)
FSEL1 (I/P)
SHSTL (I/P)
RHSTL (I/P)
OW (I/P)
ASYW (I/P)
BE (I/P)
FSEL0 (I/P)
PFM (I/P)
WHSTL (I/P)
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
SIGNAL DESCRIPTION
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ASYNCHRONOUS READ (ASYR)
The read port can be configured for either Synchronous or Asynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
Asynchronous operation of the read port will be selected. During Asynchronous operation of the read port the RCLK input becomes RD input, this is the
Asynchronous read strobe input. A rising edge on RD will read data from the
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operation of the read port).
The OE input provides three-state control of the Qn output bus, in an
asynchronous manner. (RCS, provides three-state control of the read port in
Synchronous mode).
When the read port is configured for Asynchronous operation the device
must be operating on IDT standard mode, FWFT mode is not permissible if the
read port is Asynchronous. The Empty Flag (EF) operates in an Asynchronous
manner, that is, the empty flag will be updated based on both a read operation
and a write operation. Refer to Figures 32, 33, 34 and 35 for relevant timing
and operational waveforms.
INPUTS:
DATA IN (D0 - Dn)
Data inputs for 18-bit wide data (D0 - D17) or data inputs for 9-bit wide data
(D0 - D8).
CONTROLS:
MASTER RESET ( MRS )
A Master Reset is accomplished whenever the MRS input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAM array. PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
All control settings such as OW, IW, BE, RM, PFM and IP are defined during
the Master Reset cycle.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place. MRS
is asynchronous.
See Figure 9, Master Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
The Retransmit (RT) input is used in conjunction with the MARK input,
together they provide a means by which data previously read out of the FIFO
can be reread any number of times. If retransmit operation has been selected
(i.e. the MARK input is HIGH), a rising edge on RCLK while RT is LOW will reset
the read pointer back to the memory location set by the user via the MARK input.
If IDT standard mode has been selected the EF flag will go LOW and remain
LOW for the time that RT is held LOW. RT can be held LOW for any number
of RCLK cycles, the read pointer being reset to the marked location. The next
rising edge of RCLK after RT has returned HIGH, will cause EF to go HIGH,
allowing read operations to be performed on the FIFO. The next read operation
will access data from the ‘marked’ memory location.
Subsequent retransmit operations may be performed, each time the read
pointer returning to the ‘marked’ location. See Figure 18, Retransmit from Mark
(IDT Standard mode) for the relevant timing diagram.
If FWFT mode has been selected the OR flag will go HIGH and remain HIGH
for the time that RT is held LOW. RT can be held LOW for any number of RCLK
cycles, the read pointer being reset to the ‘marked’ location. The next RCLK
rising edge after RT has returned HIGH, will cause OR to go LOW and due to
FWFT operation, the contents of the marked memory location will be loaded onto
the output register, a read operation being required for all subsequent data
reads.
Subsequent retransmit operations may be performed each time the read
pointer returning to the ‘marked’ location. See Figure 19, Retransmit from Mark
(FWFT mode) for the relevant timing diagram.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array, PAE goes LOW, PAF goes HIGH,
and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming programmable flag offset settings may not be
convenient.
See Figure 10, Partial Reset Timing, for the relevant timing diagram.
ASYNCHRONOUS WRITE (ASYW)
The write port can be configured for either Synchronous or Asynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronous operation of the write port will be selected. During Asynchronous operation of the write port the WCLK input becomes WR input, this is the
Asynchronous write strobe input. A rising edge on WR will write data present
on the Dn inputs into the FIFO. (WEN must be tied LOW when using the write
port in Asynchronous mode).
When the write port is configured for Asynchronous operation the full flag
(FF) operates in an asynchronous manner, that is, the full flag will be updated
based in both a write operation and read operation. Note, if Asynchronous
mode is selected, FWFT is not permissable. Refer to Figures 30, 31, 34 and
35 for relevant timing and operational waveforms.
MARK
The MARK input is used to select Retransmit mode of operation. An RCLK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmit mode. Note, for the IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895 there must be a minimum of 32 bytes of data between the
write pointer and read pointer when the MARK is asserted, for the IDT72T18105/
72T18115 there must be a minimum of 128 bytes and for the IDT72T18125
there must be a minimum of 256 bytes. Remember, 2(x9) bytes = 1(x18) word.
(32 bytes = 16 word = 8 long words). Also, once the MARK is set, the write
pointer will not increment past the “marked” location until the MARK is
deasserted. This prevents “overwriting” of retransmit data.
23
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
The MARK input must remain HIGH during the whole period of retransmit
mode, a falling edge of RCLK while MARK is LOW will take the device out of
retransmit mode and into normal mode. Any number of MARK locations can be
set during FIFO operation, only the last marked location taking effect. Once a
mark location has been set the write pointer cannot be incremented past this
marked location. During retransmit mode write operations to the device may
continue without hindrance.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
If Asynchronous operation of the write port has been selected, then WEN
must be held active, (tied LOW).
READ STROBE & READ CLOCK (RD/RCLK)
If Synchronous operation of the read port has been selected via ASYR, this
input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE
and HF flags will not be updated. (Note that RCLK is only capable of updating
the HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
If Asynchronous operation has been selected this input is RD (Read
Strobe) . Data is Asynchronously read from the FIFO via the output register
whenever there is a rising edge on RD. In this mode the REN and RCS inputs
must be tied LOW. The OE input is used to provide Asynchronous control of the
three-state Qn outputs.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (OR) to indicate whether or not there
is valid data at the data outputs (Qn). It also uses Input Ready (IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Qn after three RCLK
rising edges, REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and PAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
Serial programming using the FWFT/SI pin functions the same way in both IDT
Standard and FWFT modes.
WRITE CHIP SELECT (WCS)
The WCS disables all Write Port inputs (data only) if it is held HIGH. To
perform normal operations on the write port, the WCS must be enabled, held
LOW.
READ ENABLE (REN)
When Read Enable is LOW, data is loaded from the RAM array into the
output register on the rising edge of every RCLK cycle if the device is not empty.
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN provided that
RCS is LOW. When the last word has been read from the FIFO, the Empty Flag
(EF) will go LOW, inhibiting further read operations. REN is ignored when the
FIFO is empty. Once a write is performed, EF will go HIGH allowing a read to
occur. The EF flag is updated by two RCLK cycles + tSKEW after the valid WCLK
cycle. Both RCS and REN must be active, LOW for data to be read out on the
rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically goes
to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW
after the first write. REN and RCS do not need to be asserted LOW for the First
Word to fall through to the output register. In order to access all other words,
a read must be executed using REN and RCS. The RCLK LOW-to-HIGH
transition after the last word has been read from the FIFO, Output Ready (OR)
will go HIGH with a true read (RCLK with REN = LOW;RCS = LOW), inhibiting
further read operations. REN is ignored when the FIFO is empty.
If Asynchronous operation of the Read port has been selected, then REN
must be held active, (tied LOW).
WRITE STROBE & WRITE CLOCK (WR/WCLK)
If Synchronous operation of the write port has been selected via ASYW, this
input behaves as WCLK.
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
If Asynchronous operation has been selected this input is WR (write strobe).
Data is Asynchronously written into the FIFO via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be tied LOW.
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM array
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + tSKEW after the RCLK cycle.
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle, IR will go
LOW allowing a write to occur. The IR flag is updated by two WCLK cycles +
tSKEW after the valid RCLK cycle.
SERIAL ENABLE ( SEN )
The SEN input is an enable used only for serial programming of the offset
registers. The serial programming method must be selected during Master
Reset. SEN is always used in conjunction with LD. When these lines are both
LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of SCLK.
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
24
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
OUTPUT ENABLE ( OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When OE is HIGH, the output data bus (Qn) goes
into a high impedance state. During Master or a Partial Reset the OE is the only
input that can place the output bus Qn, into High-Impedance. During Reset the
RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
LOAD (LD)
This is a dual purpose pin. During Master Reset, the state of the LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the PAE and PAF flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset, LD
enables write operations to and read operations from the offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
After Master Reset, the LD pin is used to activate the programming process
of the flag offset values PAE and PAF. Pulling LD LOW will begin a serial loading
or parallel load or read of these offset values. THIS PIN MUST BE HIGH
AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO
MEMORY.
READ CHIP SELECT ( RCS )
The Read Chip Select input provides synchronous control of the Read
output port. When RCS goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the Low-Impedance state. When RCS goes HIGH, the next
RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master
or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only
input that provides High-Impedance control of the Qn outputs. If OE is LOW the
Qn data outputs will be Low-Impedance regardless of RCS until the first rising
edge of RCLK after a Reset is complete. Then if RCS is HIGH the data outputs
will go to High-Impedance.
The RCS input does not effect the operation of the flags. For example, when
the first word is written to an empty FIFO, the EF will still go from LOW to HIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of RCS. For this reason the user must take care when
a data word is written to an empty FIFO in FWFT mode. If RCS is disabled when
an empty FIFO is written into, the first word will fall through to the output register,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take RCS active LOW to access this first word, place the output bus in LOW-Z.
REN must remain disabled HIGH for at least one cycle after RCS has gone LOW.
A rising edge of RCLK with RCS and REN active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty
FIFO when RCS is HIGH. Refer to Figure 17, RCS and REN Read Operation
(FWFT Mode). The RCS pin must also be active (LOW) in order to perform
a Retransmit. See Figure 13 for Read Cycle and Read Chip Select Timing (IDT
Standard Mode). See Figure 16 for Read Cycle and Read Chip Select Timing
(First Word Fall Through Mode).
If Asynchronous operation of the Read port has been selected, then RCS
must be held active, (tied LOW). OE provides three-state control of Qn.
BUS-MATCHING (IW, OW)
The pins IW and OW are used to define the input and output bus widths.
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 5 for BusMatching Byte Arrangement.
BIG-ENDIAN/LITTLE-ENDIAN (BE)
During Master Reset, a LOW on BE will select Big-Endian operation. A
HIGH on BE during Master Reset will select Little-Endian format. This function
is useful when data is written into the FIFO in word format (x18) and read out
of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is
selected, then the most significant byte of the word written into the FIFO will be
read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable flag timing mode. If asynchronous PAF/PAE configuration is selected
(PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH
transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of
WCLK. Similarly, the PAF is asserted LOW on the LOW-to-HIGH transition of
WCLK and PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
WRITE PORT HSTL SELECT (WHSTL)
The control inputs, data inputs and flag outputs associated with the write port
can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master
Reset, then HSTL operation of the write port will be selected. If WHSTL is LOW
at Master Reset, then LVTTL will be selected.
The inputs and outputs associated with the write port are listed in Table 5.
READ PORT HSTL SELECT (RHSTL)
The control inputs, data inputs and flag outputs associated with the read port
can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master
Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW
at Master Reset, then LVTTL will be selected for the read port, then echo clock
and echo read enable will not be provided.
The inputs and outputs associated with the read port are listed in Table 5.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode. A HIGH will select Interspersed Parity mode. The IP bit function allows
the user to select the parity bit in the word loaded into the parallel port (D0-Dn)
when programming the flag offsets. If Interspersed Parity mode is selected, then
the FIFO will assume that the parity bit is located in bit position D8 and D17 during
the parallel programming of the flag offsets, and will therefore ignore D8 when
loading the offset register in parallel mode. This is also applied to the output
register when reading the value of the offset register. If Interspersed Parity is
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is
selected, then D16 and D17 are the parity bits and are ignored during parallel
SYSTEM HSTL SELECT (SHSTL)
All inputs not associated with the write and read port can be setup to be either
HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation
of all the inputs not associated with the write and read port will be selected. If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associated with SHSTL are listed in Table 5.
25
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
programming of the offsets. (D8 becomes a valid bit). Additionally, output Q8 will
become a valid bit when performing a read of the offset register. IP mode is
selected during Master Reset by the state of the IP input pin.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
again. See Figure 15, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT
mode, OR is a triple register-buffered output.
OUTPUTS:
FULL FLAG (FF/IR)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF) function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. When FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO.
If x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845,
4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the
IDT72T1875, 32,768 for the IDT72T1885, 65,536 for the IDT72T1895,
131,072 writes for the IDT72T18105, 262,144 writes for the IDT72T18115 and
524,288 writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths
are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855,
16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the
IDT72T1885, 131,072 for the IDT72T1895, 262,144 writes for the
IDT72T18105, 524,288 writes for the IDT72T18115 and 1,048,576 writes for
the IDT72T18125. See Figure 11, Write Cycle and Full Flag Timing (IDT
Standard Mode), for the relevant timing information.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
any free space left, IR goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either MRS or PRS), IR will go HIGH after D writes
to the FIFO. If x18 Input or x18 Output bus Width is selected, D = 2,049 for the
IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385
for the IDT72T1875, 32,769 for the IDT72T1885, 65,537 for the IDT72T1895,
131,073 writes for the IDT72T18105, 262,145 writes for the IDT72T18115 and
524,289 writes for the IDT72T18125. If both x9 Input and x9 Output bus Widths
are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385
for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 writes for the IDT72T18105, 524,289
writes for the IDT72T18115 and 1,048,577 writes for the IDT72T18125. See
Figure 14, Write Timing (FWFT Mode), for the relevant timing information.
The IR status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert IR is one greater than needed to
assert FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
Note, when the device is in Retransmit mode, this flag is a comparison of the
write pointer to the ‘marked’ location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (MRS), PAF will go LOW after (D-m) words are written
to the FIFO. If x18 Input or x18 Output bus Width is selected, (D-m) = (2,048-m)
writes for the IDT72T1845, (4,096-m) writes for the IDT72T1855, (8,192-m)
writes for the IDT72T1865, (16,384-m) writes for the IDT72T1875, (32,768-m)
writes for the IDT72T1885, (65,536-m) writes for the IDT72T1895, (131,072-m)
writes for the IDT72T18105, (262,144-m) writes for the IDT72T18115 and
(524,288-m) writes for the IDT72T18125. If both x9 Input and x9 Output bus
Widths are selected, (D-m) = (4,096-m) writes for the IDT72T1845, (8,192-m)
writes for the IDT72T1855, (16,384-m) writes for the IDT72T1865, (32,768-m)
writes for the IDT72T1875, (65,536-m) writes for the IDT72T1885, (131,072-m)
writes for the IDT72T1895, (262,144-m) writes for the IDT72T18105,
(524,288-m) writes for the IDT72T18115 and (1,048,576-m) writes for the
IDT72T18125. The offset “m” is the full offset value. The default setting for this
value is stated in Table 2.
In FWFT mode, if x18 Input or x18 Output bus Width is selected, the PAF
will go LOW after (2,049-m) writes for the IDT72T1845, (4,097-m) writes for the
IDT72T1855, (8,193-m) writes for the IDT72T1865, (16,385-m) writes for the
IDT72T1875, (32,769-m) writes for the IDT72T1885, (65,537-m) writes for the
IDT72T1895, (131,073-m) writes for the IDT72T18105, (262,145-m) writes
for the IDT72T18115 and (524,289-m) writes for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, the PAF will go LOW after (4,097m) writes for the IDT72T1845, (8,193-m) writes for the IDT72T1855, (16,385-m)
writes for the IDT72T1865, (32,769-m) writes for the IDT72T1875, (65,537-m)
writes for the IDT72T1885, (131,073-m) writes for the IDT72T1895, (262,145m) writes for the IDT72T18105, (524,289-m) writes for the IDT72T18115
and (1,048,577-m) writes for the IDT72T18125. The offset m is the full offset
value. The default setting for this value is stated in Table 2.
See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
If asynchronous PAF configuration is selected, the PAF is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF
configuration is selected, the PAF is updated on the rising edge of WCLK. See
Figure 25 for Asynchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode).
Note, when the device is in Retransmit mode, this flag is a comparison of the
write pointer to the ‘marked’ location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
EMPTY FLAG (EF/OR)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF)
function is selected. When the FIFO is empty, EF will go LOW, inhibiting further
read operations. When EF is HIGH, the FIFO is not empty. See Figure 12, Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
the relevant timing information.
In FWFT mode, the Output Ready (OR) function is selected. OR goes LOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs. OR stays LOW after the RCLK LOW to HIGH transition that shifts the
last word from the FIFO memory to the outputs. OR goes HIGH only with a true
read (RCLK with REN = LOW). The previous data stays at the outputs, indicating
the last word was read. Further data reads are inhibited until OR goes LOW
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go LOW
when there are n words or less in the FIFO. The offset “n” is the empty offset
value. The default setting for this value is stated in Table 2.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 24, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
26
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
If asynchronous PAE configuration is selected, the PAE is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE
configuration is selected, the PAE is updated on the rising edge of RCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via RHSTL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of REN, RCS.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data from the Qn outputs. This is especially helpful at high speeds when
variables within the device may cause changes in the data access times. These
variations in access time maybe caused by ambient temperature, supply
voltage, device characteristics. The ERCLK output also compensates for any
trace length delays between the Qn data outputs and receiving devices inputs.
Any variations effecting the data access time will also have a corresponding
effect on the ERCLK output produced by the FIFO device, therefore the ERCLK
output level transitions should always be at the same position in time relative to
the data outputs. Note, that ERCLK is guaranteed by design to be slower than
the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data
Output Relationship, Figure 28, Echo Read Clock & Read Enable Operation
and Figure 29, Echo RCLK & Echo REN Operation for timing information.
HALF-FULL FLAG (HF)
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference
between the write and read pointers becomes less than or equal to half of the
total depth of the device; the rising RCLK edge that accomplishes this condition
sets HF HIGH.
In IDT Standard mode, if no reads are performed after reset (MRS or PRS),
HF will go LOW after (D/2 + 1) writes to the FIFO. If x18 Input or x18 Output
bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855,
8,192 for the IDT72T1865, 16,384 for the IDT72T1875, 32,768 for the
IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105,
262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, D = 4,096 for the IDT72T1845,
8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the
IDT72T1875, 65,536 for the IDT72T1885, 131,072 for the IDT72T1895,
262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576
for the IDT72T18125.
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO. If x18 Input or x18 Output bus
Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855,
8,193 for the IDT72T1865, 16,385 for the IDT72T1875, 32,769 for the
IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105,
262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9
Input and x9 Output bus Widths are selected, D = 4,097 for the IDT72T1845,
8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the
IDT72T1875, 65,537 for the IDT72T1885, 131,073 for the IDT72T1895,
262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577
for the IDT72T18125.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Mode),
for the relevant timing information. Because HF is updated by both RCLK and
WCLK, it is considered asynchronous.
ECHO READ ENABLE (EREN)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via RHSTL.
The EREN output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for reading
data from the Qn output port at high speeds. The EREN output is controlled by
internal logic that behaves as follows: The EREN output is active LOW for the
RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of
RCLK will cause EREN to go active, LOW if both REN and RCS are active, LOW
and the FIFO is NOT empty.
SERIAL CLOCK (SCLK)
During serial loading of the programming flag offset registers, a rising edge
on the SCLK input is used to load serial data present on the SI input provided
that the SEN input is LOW.
DATA OUTPUTS (Q0-Qn)
(Q0 - Q17) data outputs for 18-bit wide data or (Q0 - Q8) data outputs for
9-bit wide data.
RCLK
tERCLK
tERCLK
ERCLK
tA
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tD
QSLOWEST(3)
5909 drw08
NOTES:
1. REN is LOW;RCS is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 4. Echo Read Clock and Data Output Relationship
27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
BYTE ORDER ON INPUT PORT:
BYTE ORDER ON OUTPUT PORT:
BE
IW
OW
L
L
L
BE
IW
OW
H
L
L
D17-D9
D8-D0
A
B
Q17-Q9
Q8-Q0
A
B
Write to FIFO
Read from FIFO
(a) x18 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
B
A
Read from FIFO
(b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN
Q8-Q0
Q17-Q9
BE
IW
OW
L
L
H
A
Q17-Q9
1st: Read from FIFO
Q8-Q0
B
2nd: Read from FIFO
(c) x18 INPUT to x9 OUTPUT - BIG ENDIAN
Q17-Q9
BE
IW
OW
H
L
H
Q8-Q0
B
Q17-Q9
1st: Read from FIFO
Q8-Q0
A
2nd: Read from FIFO
(d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN
BYTE ORDER ON INPUT PORT:
D17-D9
D8-D0
A
D17-Q9
D8-Q0
B
BYTE ORDER ON OUTPUT PORT:
BE
IW
OW
L
H
L
1st: Write to FIFO
Q17-Q9
Q8-Q0
A
B
2nd: Write to FIFO
Read from FIFO
(a) x9 INPUT to x18 OUTPUT - BIG ENDIAN
BE
IW
OW
H
H
L
Q17-Q9
Q8-Q0
B
A
Read from FIFO
(a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN
5909 drw09
Figure 5. Bus-Matching Byte Arrangement
28
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JTAG TIMING SPECIFICATION
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5909 drw10
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
t5
Figure 6. Standard JTAG Timing
JTAG
AC ELECTRICAL CHARACTERISTICS
SYSTEM INTERFACE PARAMETERS
(vcc = 2.5V ± 5%; Tcase = 0°C to +85°C)
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
Test Conditions
Symbol
Test
Conditions
Min.
Parameter
Symbol
Data Output
tDO(1)
-
20
ns
Data Output Hold
tDOH(1)
0
-
ns
Data Input
tDS
tDH
10
10
-
ns
trise=3ns
tfall=3ns
Min.
Parameter
Max. Units
NOTE:
1. 50pf loading on external output signals.
JTAG Clock Input Period tTCK
-
100
-
ns
JTAG Clock HIGH
tTCKHIGH
-
40
-
ns
JTAG Clock Low
tTCKLOW
-
40
-
ns
JTAG Clock Rise Time
tTCKRISE
-
-
5(1)
ns
JTAG Clock Fall Time
tTCKFALL
-
-
(1)
5
ns
JTAG Reset
tRST
-
50
-
ns
JTAG Reset Recovery
tRSR
-
50
-
ns
NOTE:
1. Guaranteed by design.
29
Max. Units
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
JTAG INTERFACE
The Standard JTAG interface consists of four basic elements:
•
Test Access Port (TAP)
•
TAP controller
•
Instruction Register (IR)
•
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T1845/72T1855/
72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/72T18125 incorporates the necessary tap controller and modified pad cells to implement the
JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture.
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
TMS
TCLK
TRST
P
TAP
Controller
clkDR, ShiftDR
UpdateDR
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5909 drw11
Figure 7. Boundary Scan Architecture
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST)
and one output port (TDO).
30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
1
Test-Logic
Reset
0
0
Run-Test/
Idle
1
SelectDR-Scan
1
SelectIR-Scan
1
0
1
0
Capture-IR
1
Capture-DR
0
0 0
Shift-DR
1
Input = TMS
EXit1-DR
Shift-IR
1
1
0
1
Exit2-DR
Exit2-IR
0
1
1
Update-DR
0
0
Pause-IR
1
1
1
Exit1-IR
0 0
Pause-DR
0
0
Update-IR
1
0
5909 drw12
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 8. TAP Controller State Diagram
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling the
normal operation of the IC. The TAP controller state machine is designed in such
a way that, no matter what the initial state of the controller is, the Test-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times. This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
31
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
THE INSTRUCTION REGISTER
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at UpdateIR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
IDT72T1845/55/65/75/85/95/105/115/125 JTAG Device Identification Register
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
•
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
•
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16 different possible instructions. Instructions are decoded as follows.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
Hex
Value
0x00
0x02
0x01
0x03
0x0F
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
Instruction
Function
EXTEST
IDCODE
SAMPLE/PRELOAD
HIGH-IMPEDANCE
BYPASS
Select Boundary Scan Register
Select Chip Identification data register
Select Boundary Scan Register
JTAG
Select Bypass Register
JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
EXTEST
The required EXTEST instruction places the IC into an external boundarytest mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is
dropped in the 11-bit Manufacturer ID field.
For the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125, the Part Number field contains the following
values:
Device
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional TRST pin or by otherwise moving to the
Test-Logic-Reset state.
Part# Field
040E
040D
040C
040B
040A
0409
0419
0418
0417
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
32
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
33
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
MRS
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
tRSS
tRSR
REN
WEN
FWFT/SI
LD
tRSS
FSEL0,
FSEL1
tRSS
OW, IW
tHRSS
WHSTL
tHRSS
RHSTL
tHRSS
SHSTL
tRSS
BE
tRSS
PFM
tRSS
IP
tRSS
RT
tRSS
SEN
If FWFT = HIGH, OR = HIGH
tRSF
EF/OR
If FWFT = LOW, EF = LOW
tRSF
If FWFT = LOW, FF = HIGH
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q0 - Qn
OE = LOW
5909 drw13
NOTE:
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 9. Master Reset Timing
34
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tRS
PRS
tRSS
tRSR
REN
tRSS
tRSR
WEN
tRSS
RT
tRSS
SEN
If FWFT = HIGH, OR = HIGH
tRSF
EF/OR
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
tRSF
FF/IR
If FWFT = HIGH, IR = LOW
tRSF
PAE
tRSF
PAF, HF
tRSF
OE = HIGH
Q0 - Qn
OE = LOW
5909 drw14
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 10. Partial Reset Timing
35
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
WCLK
NO WRITE
2
1
(1)
tSKEW1
tCLK
tCLKL
tCLKH
NO WRITE
tDS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
1
(1)
tSKEW1
tDH
2
tDH
tDS
DX+1
DX
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
tENS
RCS
tA
tA
Q0 - Qn
NEXT DATA READ
DATA READ
5909 drw15
tRCSLZ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
1
RCLK
tENS
tCLKL
2
tENH
tENS
REN
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
LAST WORD
Q0 - Qn
tOLZ
LAST WORD
tOHZ
tOE
tA
D0
D1
t OLZ
OE
(1)
tSKEW1
WCLK
tENH
tENS
tENS
tENH
WEN
tWCSS
tWCSH
WCS
tDS
D0 - Dn
D0
tDH
tDS
tDH
D1
5909 drw16
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS is LOW.
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
36
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
2
1
RCLK
tENS
REN
tENS
tENS
tENH
tENS
RCS
tREF
EF
tRCSLZ
Q0 - Qn
tRCSHZ
tA
tRCSLZ
tREF
tRCSHZ
tA
LAST DATA-1
LAST DATA
tSKEW1(1)
WCLK
tENS
tENH
WEN
tDS
Dn
tDH
Dx
5909 drw 17
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. OE is LOW.
Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)
37
38
W1
W2
(1)
1
tENS
tSKEW1
tDH
2
tRCSLZ
W3
PREVIOUS DATA IN OUTPUT REGISTER
tDS
tENS
3
tREF
tA
W4
tDS
W[n +2]
W[n+3]
1
tPAES
tSKEW2 (2)
2
W[n+4]
+1 ]
W [ D-1
2
tDS
2 +2 ]
W [ D-1
tHF
W [ D-1
2 +3 ]
W1
W[D-m-2]
tDS
W[D-m-1]
W[D-m]
1
tPAFS
W[D-m+1]
W[D-m+2]
W[D-1]
WD
5909 drw18
tWFF
tENH
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Figure 14. Write Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than tSKEW1, then OR assertion may be delayed one extra RCLK cycle.
2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
3. LD = HIGH, OE = LOW
4. n = PAE offset, m = PAF offset and D = maximum FIFO depth.
5. If x18 input or x18 output bus width is selected, D=2,049 for IDT72T1845, 4,097 for IDT72T1855, 8,193 for IDT72T1865, 16,385 for IDT72T1875, 32,769 for IDT72T1885, 65,537 for IDT72T1895, 131,073 for IDT72T18105, 262,145
for IDT72T18115, 524,288 for IDT72T18125.
If both x9 input and x9 output bus widths are selected, D=4,097 for IDT72T1845, 8,193 for IDT72T1855, 16,385 for IDT72T1865, 32,769 for IDT72T1875, 65,537 for IDT72T1885, 131,073 for IDT72T1895, 262,144 for IDT72T18105,
524,288 for IDT72T18115, 1,048,576 for IDT72T18125.
6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
IR
PAF
HF
PAE
OR
Q0 - Qn
REN
RCS
RCLK
D0 - Dn
WEN
WCLK
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
39
tDS
tENS
W1
tOHZ
WD
tENS
tWFF
tDH
tENH
W1
tOE
tA
W2
1
(1)
tSKEW1
tA
2
tWFF
W3
(2)
Wm+2
tSKEW2
W[m+3]
tA
tPAFS
W[m+4]
W[
2
D-1 + 1
]
tHF
W[
tA
2
D-1 + 2
]
W[D-n-1]
tA
W[D-n]
1
tPAES
W[D-n+1]
W[D-n+2]
W[D-1]
tA
tENS
WD
5909 drw19
tREF
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Figure 15. Read Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. If x18 input or x18 output bus width is selected, D=2,049 for IDT72T1845, 4,097 for IDT72T1855, 8,193 for IDT72T1865, 16,385 for IDT72T1875, 32,769 for IDT72T1885, 65,537 for IDT72T1895, 131,073 for IDT72T18105, 262,145
for IDT72T18115, 524,288 for IDT72T18125.
If both x9 input and x9 output bus widths are selected, D=4,097 for IDT72T1845, 8,193 for IDT72T1855, 16,385 for IDT72T1865, 32,769 for IDT72T1875, 65,537 for IDT72T1885, 131,073 for IDT72T1895, 262,144 for IDT72T18105,
524,288 for IDT72T18115, 1,048,576 for IDT72T18125.
6. RCS = LOW.
IR
PAF
HF
PAE
OR
Q0 - Qn
OE
REN
RCLK
D0 - Dn
WEN
WCLK
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
40
tDS
tENS
W1
WD
tENS
tRCSHZ
tENH
tENS
tWFF
tDH
tENH
W2
tRCSLZ
1
(1)
tSKEW1
tA
2
tWFF
W3
(2)
Wm+2
tSKEW2
W[m+3]
tA
tPAFS
W[m+4]
W[
2
D-1 + 1
]
tHF
W[
tA
2
D-1 + 2
]
W[D-n-1]
tA
W[D-n]
1
tPAES
W[D-n+1]
W[D-n+2]
W[D-1]
tA
tENS
WD
5909 drw20
tREF
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Figure 16. Read Cycle and Read Chip Select Timing (First Word Fall Through Mode)
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW1, then the IR assertion may be delayed one extra WCLK cycle.
2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than tSKEW2, then the PAF deassertion may be delayed one extra WCLK cycle.
3. LD = HIGH.
4. n = PAE Offset, m = PAF offset and D = maximum FIFO depth.
5. If x18 input or x18 output bus width is selected, D=2,049 for IDT72T1845, 4,097 for IDT72T1855, 8,193 for IDT72T1865, 16,385 for IDT72T1875, 32,769 for IDT72T1885, 65,537 for IDT72T1895, 131,073 for IDT72T18105, 262,145
for IDT72T18115, 524,288 for IDT72T18125.
If both x9 input and x9 output bus widths are selected, D=4,097 for IDT72T1845, 8,193 for IDT72T1855, 16,385 for IDT72T1865, 32,769 for IDT72T1875, 65,537 for IDT72T1885, 131,073 for IDT72T1895, 262,144 for IDT72T18105,
524,288 for IDT72T18115, 1,048,576 for IDT72T18125.
6. OE = LOW.
IR
PAF
HF
PAE
OR
Q0 - Qn
RCS
REN
RCLK
D0 - Dn
WEN
WCLK
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
HIGH-Z
tDS
tENS
W1
tDH
tSKEW
tDS
1
W2
tDH
tENH
2
tREF
3
1st Word falls through to
O/P register on this cycle
tENS
tRCSLZ
W1
tENS
tA
tENH
W2
tENS
tRCSHZ
tENH
tENS
tENS
tRCSLZ
tREF
W2
5909 drw21
41
Figure 17 . RCS and REN Read Operation (FWFT Mode)
NOTES:
1. It is very important that the REN be held HIGH for at least one cycle after RCS has gone LOW. If REN goes LOW on the same cycle as RCS or earlier, then Word, W1 will be lost, Word, W2 will be read on the output when the
bus goes to LOW-Z.
2. The 1st Word will fall through to the output register regardless of REN and RCS. However, subsequent reads require that both REN and RCS be active, LOW.
Dn
WEN
WCLK
Qn
OR
RCS
REN
RCLK
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
42
WMK-1
tENS
tA
tENS
WMK
tENH
tA
WMK+1
tA
tA
tENS
tENS
tENS
WMK+n
tHF
1
tSKEW2
tREF
tENH
2
tPAFS
1
tREF
tENS
tA
2
WMK
tA
3
5909 drw22
tPAES(6)
WMK+1
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Figure 18. Retransmit from Mark (IDT Standard Mode)
NOTES:
1. Retransmit setup is complete when EF returns HIGH.
2. OE = LOW;RCS = LOW.
3. RT must be HIGH when reading from FIFO.
4. Once Mark is set, the write pointer will not increment past the ‘marked’ location, preventing overwrites of Retransmit data.
5. Before a “MARK” can be set there must be at least 32 bytes of data between the Write Pointer and Read Pointer locations for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895, 64 bytes of data for the IDT72T18105/
72T18115 and 128 bytes of data for the IDT72T18125. (32 bytes = 16 words = 8 long words).
6. A transition in the PAE flag may occur one RCLK cycle earlier than shown, (on cycle 2).
HF
PAF
WEN
WCLK
PAE
EF
RT
MARK
Qn
REN
RCLK
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
43
WMK-1
tENS
tA
tENS
WMK
tENH
tA
WMK+1
tA
tA
tENS
tENS
tENS
WMK+n
tHF
1
tSKEW2
tREF
tENH
2
tPAFS
tA
1
tREF
WMK
tENS
tA
2
WMK+1
tA
3
5909 drw23
tPAES(6)
WMK+2
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Figure 19. Retransmit from Mark (First Word Fall Through Mode)
NOTES:
1. Retransmit setup is complete when OR returns LOW.
2. OE = LOW;RCS = LOW.
3. RT must be HIGH when reading from FIFO.
4. Once Mark is set, the write pointer will not increment past the ‘marked’ location, preventing overwrites of Retransmit data.
5. Before a “MARK” can be set there must be at least 32 bytes of data between the Write Pointer and Read Pointer locations for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895, 64 bytes of data for the IDT72T18105/
72T18115 and 128 bytes of data for the IDT72T18125. (32 bytes = 16 words = 8 long words).
6. A transition in the PAE flag may occur one RCLK cycle earlier than shown, (on cycle 2).
HF
PAF
WEN
WCLK
PAE
OR
RT
MARK
Qn
REN
RCLK
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tSCKH
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tSCLK
tSCKL
SCLK
tSENH
tSENS
tENH
SEN
tLDS
tLDS
tLDH
LD
tSDH
tSDS
(1)
BIT 1
SI
(1)
BIT 1
BIT X
BIT X
5909 drw24
FULL OFFSET
EMPTY OFFSET
NOTES:
1. x9 to x9 mode: X =12 for the IDT72T1845, X = 13 for the IDT72T1855, X = 14 for the IDT72T1865, X = 15 for the IDT72T1875, X = 16 for the IDT72T1885, X = 17 for the IDT72T1895,
X = 18 for the IDT72T18105, X = 19 for the IDT72T18115 and X = 20 for the IDT72T18125.
2. All other modes: X=11 for the IDT72T1845, X = 12 for the IDT72T1855, X = 13 for the IDT72T1865, X = 14 for the IDT72T1875, X = 15 for the IDT72T1885 and X = 16 for the IDT72T1895,
X = 17 for the IDT72T18105, X = 18 for the IDT72T18115 and X = 19 for the IDT72T18125.
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
WCLK
tLDS
tLDH
tLDH
tENS
tENH
tENH
tDS
tDH
LD
WEN
tDS
tDS
tDH
tDS
tDH
tDH
D0 - D17
PAE OFFSET
PAE(2) OFFSET
PAF OFFSET
5909 drw25
PAF(2) OFFSET
NOTES:
1. This timing diagram is based on programming with a x18 bus width.
2. Overwrites previous offset value.
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tLDH
tLDS
tLDH
tLDS
tLDH
tLDS
LD
tENH
tENH
tENS
tENH
tENS
tENS
REN
tA
Q0 - Q17
DATA IN OUTPUT REGISTER
tA
PAE OFFSET VALUE
tA
PAF OFFSET VALUE
PAE OFFSET
5909 drw26
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 18 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
44
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tCLKL
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL
WCLK
1
2
1
tENS
2
tENH
WEN
tPAFS
PAF
tPAFS
(2)
D-(m+1) words
(2)
in FIFO
D - m words in FIFO
(2)
D - (m +1) words in FIFO
(3)
tSKEW2
RCLK
tENH
tENS
REN
5909 drw27
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the IDT72T1885,
131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385 for the IDT72T1875,
32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
6. RCS is LOW.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
(2)
PAE
(2)
n words in FIFO ,
(3)
n + 1 words in FIFO
(4)
tSKEW2
RCLK
1
n words in FIFO ,
(3)
n + 1 words in FIFO
(2)
n + 1 words in FIFO ,
(3)
n + 2 words in FIFO
tPAES
2
tPAES
1
tENS
2
tENH
REN
5909 drw28
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
45
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tCLKH
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL
WCLK
tENS
tENH
WEN
tPAFA
PAF
D - m words
in FIFO
D - (m + 1) words in FIFO
D - (m + 1) words
in FIFO
tPAFA
RCLK
tENS
REN
5909 drw29
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the IDT72T1885,
131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385 for the IDT72T1875,
32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS is LOW.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAE
tPAEA
n words in FIFO(2),
n + 1 words in FIFO(3)
n + 1 words in FIFO(2),
n + 2 words in FIFO(3)
n words in FIFO(2),
n + 1 words in FIFO(3)
tPAEA
RCLK
tENS
REN
5909 drw30
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS = LOW.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
46
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tCLKH
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKL
WCLK
tENH
tENS
WEN
tHF
HF
[
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1),
D-1
(2)
2 + 1 words in FIFO
(2)
[ D-1
2 + 2] words in FIFO
]
[
D/2 words in FIFO(1),
D-1
(2)
2 + 1 words in FIFO
]
tHF
RCLK
tENS
REN
5909 drw31
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865,
16,384 for the IDT72T1875, 32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125.
If both x9 Input and x9 Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536
for the IDT72T1885, 131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865,
16,385 for the IDT72T1875, 32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125.
If both x9 Input and x9 Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537
for the IDT72T1885, 131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
3. RCS = LOW.
Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)
47
tOLZ
tENS
WD-4
tA
tENH
tCLKEN
tERCLK
WD-3
tOHZ
tCLKEN
tOLZ
tENS
WD-3
tA
tCLKEN
WD-2
tA
tENH
WD-1
tCLKEN
tENS
tA
tREF
tCLKEN
Last Word, WD
tCLKEN
Figure 28. Echo Read Clock & Read Enable Operation (IDT Standard Mode Only)
NOTES:
1. The EREN output is an “ANDed” function of RCS and REN and will follow these inputs provided that the FIFO is not empty. If the FIFO is empty, EREN will go HIGH, thus preventing any reads.
2. The EREN output is synchronous to RCLK.
Qn
EF
EREN
RCS
REN
ERCLK
RCLK
5909 drw32
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
48
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
WCLK
tENS
tENH
WEN
tDS
tDH
Wn+1
D0 - Dn
tDS
tDH
tDS
Wn+2
tDH
Wn+3
tSKEW1
1
RCLK
a
2
b
e
d
c
h
g
f
i
tERCLK
ERCLK
tENS
REN
tENH
tENS
RCS
tCLKEN
tCLKEN
tCLKEN
tCLKEN
EREN
tRCSLZ
Qn
HIGH-Z
tA
tA
Wn+1
Wn+2
Wn+3
tREF
tREF
OR
tA
tA
O/P
Reg.
Wn Last Word
Wn+1
tA
Wn+2
Wn+3
5909 drw33
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in HighImpedance state.
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
d.
EREN goes HIGH, no new word has been placed on the output register on this cycle.
e.
No Operation.
f.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
g.
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
h.
Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
i.
This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
Figure 29. Echo RCLK and Echo REN Operation (FWFT Mode Only)
49
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
RCLK
tENS
REN
tENH
tA
Qn
W0
W1
tFFA
FF
tFFA
tFFA
tCYC
WR
tDS
Dn
tCYH
tDH
WD
WD+1
5909 drw34
NOTE:
1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 30. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
1
RCLK
2
tENS
REN
tENH
tA
tA
Qn
Last Word
W1
W0
tREF
tREF
EF
tCYL
tSKEW
WR
tCYH
tCYC
tDH
tDS
Dn
W0
tDH
tDS
W1
5909 drw35
NOTE:
1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 31. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
50
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
No Write
WCLK
1
2
WEN
Dn
DF
DF+1
tWFF
tWFF
FF
tCYC
tSKEW
tCYL
tCYH
RD
tAA
tAA
Qn
Last Word
WX
WX+1
5909 drw36
NOTES:
1. OE = LOW, RCS = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 32. Synchronous Write, Asynchronous Read, Full Flag (IDT Standard Mode)
WCLK
tENS
tENH
tDS
tDH
WEN
Dn
EF
W0
tEFA
tRPE
tEFA
RD
tCYH
tAA
Qn
Last Word in Output Register
W0
5909 drw37
NOTES:
1. OE = LOW, RCS = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 33. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
51
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tCYH
tCYC
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCYL
WR
tDH
Dn
tDH
tDS
W0
W1
RD
tAA
tAA
Qn
W1
W0
Last Word in O/P Register
tRPE
tEFA
tEFA
EF
5909 drw38
NOTES:
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 34. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC
tCYH
tCYL
WR
tDH
tDS
Dn
tDH
tDS
Wy+1
Wy
tCYC
tCYH
tCYL
RD
tAA
Qn
Wx
tAA
Wx+1
Wx+2
tFFA
tFFA
FF
5909 drw39
NOTES:
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 35. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
52
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
OPTIONAL CONFIGURATIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can be
created by ORing OR of every FIFO, and separately ORing IR of every FIFO.
Figure 36 demonstrates a width expansion using two IDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125 devices. D0 - D17 from each device form a 36-bit wide input bus and
Q0-Q17 from each device form a 36-bit wide output bus. Any word width can
be attained by adding additional IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125 devices.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m+n
DATA IN
D0 - Dm
m
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
FULL FLAG/INPUT READY (FF/IR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
n
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
FIFO
#1
FIFO
#2
m
Q0 - Qm
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
n
Qm+1 - Qn
m+n
DATA OUT
5909 drw40
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of Width Expansion
For the x18 Input or x18 Output bus Width: 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 18, 32,768 x 18, 65,536 x 36, 131,072 x 36,
262,144 x 36 and 524,288 x 36
For both x9 Input and x9 Output bus Widths: 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18,
524,288 x 18 and 1,048,576 x 18
53
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
FWFT/SI
TRANSFER CLOCK
WRITE CLOCK
WRITE ENABLE
INPUT READY
DATA IN
FWFT/SI
WCLK
WEN
IR
n
Dn
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
FWFT/SI
WCLK
RCLK
OR
WEN
REN
IR
RCS
OE
Qn
GND
n
Dn
IDT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
READ CLOCK
RCLK
RCS
READ CHIP SELECT
READ ENABLE
REN
OR
OUTPUT READY
OE
OUTPUT ENABLE
n
DATA OUT
Qn
5909 drw41
Figure 37. Block Diagram of Depth Expansion
For the x18 Input or x18 Output bus Width:
4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18, 524,288 x 18 and 1,048,576 x 18
For both x9 Input and x9 Output bus Widths:
8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9, 262,144 x 9, 524,288 x 9, 1,048,576 x 9 and 2,097,152 x 9
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T1845 can easily be adapted to applications requiring depths
greater than 2,048 when the x18 Input or x18 Output bus Width is selected, 4,096
for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the
IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the
IDT72T18125. When both x9 Input and x9 Output bus Widths are selected,
depths greater than 4,096 can be adapted for the IDT72T1845, 8,192 for the
IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875,
65,536 for the IDT72T1885, 131,072 for the IDT72T1895, 262,144 for the
IDT72T8105, 524,288 for the IDT72T18115 and 1,048,576 for the
IDT72T18125. In FWFT mode, the FIFOs can be connected in series (the data
outputs of one FIFO connected to the data inputs of the next) with no external
logic necessary. The resulting configuration provides a total depth equivalent
to the sum of the depths associated with each single FIFO. Figure 37 shows
a depth expansion using two IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125 devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain – no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the data
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for OR of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK period.
Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the OR flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for IR of the first
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the tSKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
54
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
ORDERING INFORMATION
XXXXX
X
XX
X
Device Type
Power
Speed
Package
X
X
Process /
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
BB
BB
Plastic Ball Grid Array, BB144 (72T1845/55/65/75/85/95 Only)
Plastic Ball Grid Array, BB240, BBG240 (72T18105/115/125 Only)
4-4
5
6-7
10(3)
Commercial Only
Commercial and Industrial
Commercial Only
Commercial Only
L
Low Power
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
2,048 x 18/4,096 x 9 ⎯ 2.5V TeraSync™ FIFO
4,096 x 18/8,192 x 9 ⎯ 2.5V TeraSync™ FIFO
8,192 x 18/16,384 x 9 ⎯ 2.5V TeraSync™ FIFO
16,384 x 18/32,768 x 9 ⎯ 2.5V TeraSync™ FIFO
32,768 x 18/65,536 x 9 ⎯ 2.5V TeraSync™ FIFO
65,536 x 18/131,072 x 9 ⎯ 2.5V TeraSync™ FIFO
131,072 x 18/262,144 x 9 ⎯ 2.5V TeraSync™ FIFO
262,144 x 18/524,288 x 9 ⎯ 2.5V TeraSync™ FIFO
524,288 x 18/1,048,576 x 9 ⎯ 2.5V TeraSync™ FIFO
Clock Cycle Time (tCLK)
Speed in Nanoseconds
5909 drw42
NOTES:
1. Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Green parts available. For specific speeds and packages contact your sales office.
3. Available for IDT72T18105/72T18115/72T18125 only.
ORDERABLE PART INFORMATION
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
72T1845L4-4BB
BB144
PBGA
C
4-4
5
72T1845L5BB
BB144
PBGA
C
5
72T1845L5BBI
BB144
PBGA
I
6-7
72T1845L6-7BB
BB144
PBGA
C
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
72T1855L4-4BB
BB144
PBGA
C
4-4
5
72T1855L5BB
BB144
PBGA
C
5
72T1855L5BBI
BB144
PBGA
6-7
72T1855L6-7BB
BB144
PBGA
Speed
(ns)
4-4
Speed
(ns)
4-4
Orderable Part ID
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
72T1865L4-4BB
BB144
PBGA
C
5
72T1865L5BB
BB144
PBGA
C
5
72T1865L5BBI
BB144
PBGA
I
6-7
72T1865L6-7BB
BB144
PBGA
C
Pkg.
Code
Pkg.
Type
Temp.
Grade
72T1875L4-4BB
BB144
PBGA
C
5
72T1875L5BB
BB144
PBGA
C
I
5
72T1875L5BBI
BB144
PBGA
I
C
6-7
72T1875L6-7BB
BB144
PBGA
C
55
Orderable Part ID
Orderable Part ID
ORDERABLE PART INFORMATION (CONTINUED)
Pkg.
Code
Pkg.
Type
Temp.
Grade
Speed
(ns)
72T1885L4-4BB
BB144
PBGA
C
4-4
72T18105L4-4BB
5
72T1885L5BB
BB144
PBGA
C
4-4
72T18105L4-4BBG
5
72T1885L5BBI
BB144
PBGA
I
5
72T18105L5BB
6-7
72T1885L6-7BB
BB144
PBGA
C
5
72T18105L5BBGI
Pkg.
Code
Pkg.
Type
Temp.
Grade
5
Speed
(ns)
4-4
Orderable Part ID
Speed
(ns)
Orderable Part ID
Pkg.
Code
Pkg.
Type
Temp.
Grade
BB240
PBGA
C
BBG240
PBGA
C
BB240
PBGA
C
BBG240
PBGA
I
72T18105L5BBI
BB240
PBGA
I
6-7
72T18105L6-7BB
BB240
PBGA
C
10
72T18105L10BB
BB240
PBGA
C
Pkg.
Code
Pkg.
Type
Temp.
Grade
72T18115L4-4BB
BB240
PBGA
C
Orderable Part ID
4-4
72T1895L4-4BB
BB144
PBGA
C
4-4
72T1895L4-4BBG
BB144
PBGA
C
4-4
72T1895L4-4BBG8
BB144
PBGA
C
Speed
(ns)
5
72T1895L5BB
BB144
PBGA
C
4-4
5
72T1895L5BBI
BB144
PBGA
I
5
72T18115L5BB
BB240
PBGA
C
5
72T1895L5BBI8
BB144
PBGA
I
5
72T18115L5BBI
BB240
PBGA
I
5
72T1895L5BBGI
BB144
PBGA
I
5
72T18115L5BBGI
BB240
PBGA
I
5
72T1895L5BBGI8
BB144
PBGA
I
6-7
72T18115L6-7BB
BB240
PBGA
C
72T1895L6-7BB
BB144
PBGA
C
10
72T18115L10BB
BB240
PBGA
C
Pkg.
Code
Pkg.
Type
Temp.
Grade
BB240
PBGA
C
BBG240
PBGA
C
BB240
PBGA
C
BBG240
PBGA
I
6-7
Speed
(ns)
DATASHEET DOCUMENT HISTORY
05/30/2001
07/09/2001
10/17/2001
11/19/2001
11/29/2001
01/15/2002
03/04/2002
06/05/2002
06/27/2002
02/11/2003
03/03/2003
09/02/2003
01/11/2007
02/10/2009
03/30/2017
05/30/2017
Orderable Part ID
Orderable Part ID
4-4
72T18125L4-4BB
4-4
72T18125L4-4BBG
5
72T18125L5BB
5
72T18125L5BBGI
5
72T18125L5BBI
BB240
PBGA
I
6-7
72T18125L6-7BB
BB240
PBGA
C
10
72T18125L10BB
BB240
PBGA
C
pg. 18.
pgs. 1, 7, 8, 19, and 50.
pgs. 1-6, 8, 10, 11, 13-20, 23, 24, 26, 27, 29, 34, 35, 36, 38-43, 49-51.
pgs. 1, 9, 12, 38, and 39.
pgs. 1, 38, and 39.
pg. 40.
pgs. 9, 10, 17, and 27.
pgs. 9, 10, and 14.
pg. 20.
pgs. 8, 9, and 31.
pgs. 1, 11-13, 29, and 31-33.
pgs. 7, 17, and 25.
pgs. 1, 12, 13, and 55.
pg. 55.
Partial Product Discontinuation Notice - Last time buy expires May 26, 2018.
PDN# SP-17-01, IDT72T1845/55/65/75/85/95
pgs. 1, 5, 55, and 56.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
56
for Tech Support:
408-360-1753
email: [email protected]